Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

947200

1

T3

92619

T4

49

T5

73

full_word

606049

1

T3

63234

T4

6

T5

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1552979	1			T3	155853		T4	55		T5	78
auto[TlIntgErrCmd]	95	1			T51	7		T53	3		T54	5
auto[TlIntgErrData]	90	1			T51	3		T53	4		T54	10
auto[TlIntgErrBoth]	85	1			T51	10		T53	3		T54	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262378

1

T3

24963

T4

55

T5

78

auto[1]

1290871

1

T3

130890

T16

498716

T17

104652

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	117567	1			T3	10092		T4	49		T5	73
auto[TlIntgErrNone]	partial	auto[1]	829384	1			T3	82527		T16	320656		T17	67534
auto[TlIntgErrNone]	full_word	auto[0]	144701	1			T3	14871		T4	6		T5	5
auto[TlIntgErrNone]	full_word	auto[1]	461327	1			T3	48363		T16	178060		T17	37118
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T51	4		T53	1		T54	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T51	3		T53	2		T54	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T111	1		T106	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T112	1		T113	1		T114	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T51	3		T53	3		T54	4
auto[TlIntgErrData]	partial	auto[1]	43	1			T54	5		T112	1		T105	5
auto[TlIntgErrData]	full_word	auto[0]	3	1			T53	1		T114	1		T107	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T54	1		T108	1		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	22	1			T51	2		T54	1		T62	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T51	8		T53	3		T54	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T107	1		T106	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T109	1		T115	1		T116	1