Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 45921 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 775610 1 T2 17 T3 17 T4 5



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 226042 1 T2 141 T3 170 T4 88
values[0x0] 292252 1 T15 74908 T16 38972 T17 23136
values[0x1] 303237 1 T15 77697 T16 40010 T17 23955



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 22696 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 798835 1 T2 83 T3 107 T4 45



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3093 1 T10 1 T12 9 T119 1
valid_sources[0x01] 3132 1 T10 1 T84 3 T20 1
valid_sources[0x02] 3295 1 T10 3 T14 8 T37 3
valid_sources[0x03] 3300 1 T5 2 T10 1 T20 1
valid_sources[0x04] 3323 1 T2 5 T10 1 T37 12
valid_sources[0x05] 3039 1 T2 5 T6 1 T10 1
valid_sources[0x06] 3321 1 T3 2 T5 1 T8 1
valid_sources[0x07] 3295 1 T3 2 T5 2 T119 2
valid_sources[0x08] 3410 1 T6 2 T37 5 T119 1
valid_sources[0x09] 3306 1 T10 1 T83 1 T84 2
valid_sources[0x0a] 3173 1 T10 2 T119 1 T27 3
valid_sources[0x0b] 3316 1 T3 1 T6 2 T10 1
valid_sources[0x0c] 3179 1 T6 2 T9 11 T83 1
valid_sources[0x0d] 3211 1 T3 5 T6 2 T84 1
valid_sources[0x0e] 3267 1 T3 1 T10 1 T14 2
valid_sources[0x0f] 3269 1 T84 4 T85 15 T119 4
valid_sources[0x10] 3167 1 T6 2 T84 1 T119 4
valid_sources[0x11] 3144 1 T5 1 T37 6 T84 1
valid_sources[0x12] 3144 1 T10 1 T37 8 T84 3
valid_sources[0x13] 3308 1 T2 2 T3 2 T10 1
valid_sources[0x14] 3179 1 T2 6 T6 1 T37 3
valid_sources[0x15] 3107 1 T6 2 T8 1 T37 6
valid_sources[0x16] 3262 1 T8 1 T37 3 T84 3
valid_sources[0x17] 3217 1 T9 8 T10 3 T83 1
valid_sources[0x18] 3215 1 T10 1 T11 1 T84 3
valid_sources[0x19] 3260 1 T3 2 T9 14 T11 1
valid_sources[0x1a] 3293 1 T3 2 T84 1 T119 2
valid_sources[0x1b] 3074 1 T3 1 T4 1 T10 1
valid_sources[0x1c] 3258 1 T83 2 T84 1 T119 1
valid_sources[0x1d] 3196 1 T6 1 T119 3 T20 1
valid_sources[0x1e] 3339 1 T10 4 T84 1 T119 1
valid_sources[0x1f] 3348 1 T6 2 T10 2 T84 1
valid_sources[0x20] 3325 1 T37 2 T83 1 T84 2
valid_sources[0x21] 3239 1 T3 12 T4 2 T10 1
valid_sources[0x22] 3281 1 T2 1 T14 7 T83 2
valid_sources[0x23] 3102 1 T10 1 T14 8 T11 5
valid_sources[0x24] 3047 1 T8 2 T10 1 T83 1
valid_sources[0x25] 3235 1 T10 1 T83 1 T119 1
valid_sources[0x26] 3057 1 T83 1 T84 3 T119 4
valid_sources[0x27] 3175 1 T4 16 T6 1 T10 1
valid_sources[0x28] 3208 1 T9 1 T38 56 T37 8
valid_sources[0x29] 3191 1 T10 4 T37 3 T83 1
valid_sources[0x2a] 3149 1 T5 1 T10 1 T11 3
valid_sources[0x2b] 3205 1 T5 1 T10 6 T37 4
valid_sources[0x2c] 3215 1 T10 2 T20 1 T57 1
valid_sources[0x2d] 3342 1 T2 1 T5 1 T10 2
valid_sources[0x2e] 3123 1 T10 1 T83 1 T119 2
valid_sources[0x2f] 3298 1 T5 1 T10 3 T37 1
valid_sources[0x30] 3317 1 T10 1 T37 3 T119 1
valid_sources[0x31] 3279 1 T3 2 T5 1 T8 3
valid_sources[0x32] 3289 1 T3 1 T6 1 T10 1
valid_sources[0x33] 3182 1 T5 1 T10 2 T14 11
valid_sources[0x34] 3215 1 T9 16 T10 2 T83 1
valid_sources[0x35] 3195 1 T3 3 T83 1 T84 3
valid_sources[0x36] 3155 1 T37 4 T84 3 T12 3
valid_sources[0x37] 3060 1 T8 2 T83 1 T84 5
valid_sources[0x38] 3196 1 T2 1 T10 2 T84 3
valid_sources[0x39] 2968 1 T3 4 T9 3 T37 3
valid_sources[0x3a] 3106 1 T6 3 T84 1 T119 2
valid_sources[0x3b] 3204 1 T8 1 T9 4 T10 1
valid_sources[0x3c] 3115 1 T5 1 T8 1 T10 1
valid_sources[0x3d] 3287 1 T2 1 T5 2 T10 1
valid_sources[0x3e] 3152 1 T2 2 T3 4 T37 15
valid_sources[0x3f] 3399 1 T3 3 T10 4 T37 3
valid_sources[0x40] 3221 1 T10 1 T37 6 T84 3
valid_sources[0x41] 3150 1 T2 3 T14 6 T84 3
valid_sources[0x42] 3311 1 T2 4 T10 5 T83 1
valid_sources[0x43] 3094 1 T3 1 T8 3 T10 1
valid_sources[0x44] 3087 1 T4 17 T10 1 T119 2
valid_sources[0x45] 3196 1 T10 6 T14 2 T83 1
valid_sources[0x46] 3283 1 T3 1 T8 7 T10 1
valid_sources[0x47] 3191 1 T5 1 T11 8 T85 29
valid_sources[0x48] 3171 1 T2 2 T3 1 T4 14
valid_sources[0x49] 3053 1 T6 6 T14 1 T119 1
valid_sources[0x4a] 3253 1 T2 2 T3 2 T10 1
valid_sources[0x4b] 3035 1 T10 3 T37 2 T84 1
valid_sources[0x4c] 3112 1 T6 5 T84 1 T119 1
valid_sources[0x4d] 3111 1 T5 2 T6 1 T9 4
valid_sources[0x4e] 3187 1 T3 2 T5 1 T8 2
valid_sources[0x4f] 3141 1 T2 2 T3 1 T10 5
valid_sources[0x50] 3032 1 T5 1 T37 2 T20 2
valid_sources[0x51] 3062 1 T10 2 T84 1 T85 6
valid_sources[0x52] 3326 1 T3 1 T9 13 T10 2
valid_sources[0x53] 3219 1 T2 5 T10 2 T21 1
valid_sources[0x54] 3187 1 T10 2 T37 4 T83 1
valid_sources[0x55] 3153 1 T6 3 T10 2 T37 6
valid_sources[0x56] 3240 1 T6 1 T10 1 T83 1
valid_sources[0x57] 3187 1 T9 12 T84 1 T15 805
valid_sources[0x58] 3223 1 T5 1 T10 4 T21 2
valid_sources[0x59] 3198 1 T2 3 T10 1 T37 3
valid_sources[0x5a] 3178 1 T3 1 T84 1 T119 2
valid_sources[0x5b] 3185 1 T5 1 T84 2 T12 7
valid_sources[0x5c] 3201 1 T5 1 T9 13 T10 2
valid_sources[0x5d] 3331 1 T8 2 T10 4 T37 5
valid_sources[0x5e] 3183 1 T10 1 T83 3 T84 4
valid_sources[0x5f] 3219 1 T5 1 T8 2 T14 2
valid_sources[0x60] 3340 1 T5 1 T83 1 T84 1
valid_sources[0x61] 3228 1 T5 1 T6 1 T10 4
valid_sources[0x62] 3267 1 T6 1 T9 6 T10 2
valid_sources[0x63] 3212 1 T10 1 T85 7 T119 1
valid_sources[0x64] 3127 1 T2 4 T37 3 T84 3
valid_sources[0x65] 3165 1 T2 3 T3 5 T14 3
valid_sources[0x66] 3161 1 T6 2 T37 4 T84 2
valid_sources[0x67] 3148 1 T10 1 T83 2 T119 1
valid_sources[0x68] 3247 1 T3 1 T6 1 T10 5
valid_sources[0x69] 3218 1 T3 3 T10 1 T37 3
valid_sources[0x6a] 3439 1 T6 1 T9 6 T37 1
valid_sources[0x6b] 3124 1 T2 8 T8 1 T14 3
valid_sources[0x6c] 3172 1 T10 1 T37 3 T84 1
valid_sources[0x6d] 3291 1 T4 19 T10 4 T83 1
valid_sources[0x6e] 3122 1 T4 2 T9 19 T10 4
valid_sources[0x6f] 3290 1 T9 16 T10 2 T83 1
valid_sources[0x70] 3311 1 T3 9 T10 3 T84 2
valid_sources[0x71] 3131 1 T3 2 T10 2 T37 12
valid_sources[0x72] 3195 1 T2 1 T3 5 T8 1
valid_sources[0x73] 3259 1 T2 4 T5 1 T8 1
valid_sources[0x74] 3058 1 T2 1 T6 1 T8 2
valid_sources[0x75] 3166 1 T3 2 T9 2 T10 1
valid_sources[0x76] 3406 1 T9 26 T20 1 T15 921
valid_sources[0x77] 3094 1 T8 1 T10 1 T83 2
valid_sources[0x78] 3342 1 T3 1 T6 1 T37 3
valid_sources[0x79] 3156 1 T5 1 T10 4 T84 1
valid_sources[0x7a] 3213 1 T5 1 T8 1 T10 1
valid_sources[0x7b] 3140 1 T5 4 T10 1 T37 3
valid_sources[0x7c] 3127 1 T10 1 T37 6 T84 3
valid_sources[0x7d] 3285 1 T6 1 T10 2 T84 1
valid_sources[0x7e] 3149 1 T6 4 T119 1 T55 16
valid_sources[0x7f] 3406 1 T10 1 T84 2 T119 2
valid_sources[0x80] 3112 1 T10 1 T83 1 T12 17



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 196017 1 T2 17 T3 17 T4 5
values[0x0] all_enables biggest_size 289645 1 T15 74209 T16 38658 T17 22953
values[0x1] all_enables biggest_size 289948 1 T15 74289 T16 38322 T17 22921


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 60967 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 609148 1 T1 1 T2 29 T3 31



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 171231 1 T1 1 T2 64 T3 64
values[0x0] 232154 1 T34 2 T35 4 T36 5
values[0x1] 266730 1 T34 1 T35 4 T36 4



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 28746 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 641369 1 T1 1 T2 35 T3 36



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2503 1 T4 1 T84 1 T20 1
valid_sources[0x01] 2775 1 T3 1 T38 2 T15 602
valid_sources[0x02] 3151 1 T14 1 T84 2 T15 682
valid_sources[0x03] 2423 1 T15 654 T16 383 T17 24
valid_sources[0x04] 2483 1 T84 3 T15 647 T72 1
valid_sources[0x05] 2681 1 T5 1 T84 1 T15 645
valid_sources[0x06] 3205 1 T3 1 T38 2 T84 2
valid_sources[0x07] 3224 1 T38 1 T15 582 T72 2
valid_sources[0x08] 1876 1 T14 1 T38 1 T15 635
valid_sources[0x09] 2417 1 T38 1 T15 659 T70 1
valid_sources[0x0a] 2545 1 T38 2 T12 1 T57 1
valid_sources[0x0b] 2536 1 T84 2 T55 21 T15 696
valid_sources[0x0c] 2688 1 T38 2 T15 703 T96 1
valid_sources[0x0d] 2111 1 T38 1 T84 1 T12 4
valid_sources[0x0e] 2301 1 T20 2 T15 701 T72 1
valid_sources[0x0f] 2869 1 T14 2 T12 2 T15 619
valid_sources[0x10] 2822 1 T4 3 T38 1 T15 623
valid_sources[0x11] 3150 1 T38 1 T84 1 T49 1
valid_sources[0x12] 2707 1 T84 2 T15 622 T96 1
valid_sources[0x13] 2833 1 T8 1 T15 636 T96 1
valid_sources[0x14] 2195 1 T38 1 T84 1 T15 614
valid_sources[0x15] 3426 1 T3 1 T8 2 T38 1
valid_sources[0x16] 2793 1 T8 1 T14 3 T84 1
valid_sources[0x17] 2764 1 T3 1 T5 2 T38 1
valid_sources[0x18] 3303 1 T38 2 T84 3 T15 610
valid_sources[0x19] 2371 1 T1 1 T38 3 T84 1
valid_sources[0x1a] 2627 1 T3 3 T4 2 T5 3
valid_sources[0x1b] 2674 1 T3 1 T15 623 T72 3
valid_sources[0x1c] 2536 1 T38 1 T49 1 T15 671
valid_sources[0x1d] 3094 1 T38 2 T84 1 T15 679
valid_sources[0x1e] 2478 1 T15 643 T72 1 T97 7
valid_sources[0x1f] 2678 1 T4 4 T84 2 T15 633
valid_sources[0x20] 2559 1 T38 1 T26 1 T84 1
valid_sources[0x21] 2209 1 T55 5 T15 613 T16 345
valid_sources[0x22] 2589 1 T8 6 T12 3 T57 2
valid_sources[0x23] 2589 1 T3 1 T84 1 T15 615
valid_sources[0x24] 2148 1 T38 1 T20 1 T15 641
valid_sources[0x25] 2424 1 T3 2 T15 676 T70 1
valid_sources[0x26] 3063 1 T20 1 T55 7 T15 632
valid_sources[0x27] 2545 1 T38 1 T57 1 T15 604
valid_sources[0x28] 2306 1 T5 2 T38 1 T20 1
valid_sources[0x29] 2484 1 T4 6 T38 2 T20 1
valid_sources[0x2a] 2507 1 T14 1 T49 1 T15 661
valid_sources[0x2b] 2628 1 T3 1 T57 2 T15 598
valid_sources[0x2c] 2646 1 T29 16 T15 656 T72 2
valid_sources[0x2d] 2931 1 T84 3 T12 3 T15 656
valid_sources[0x2e] 2528 1 T3 1 T5 1 T84 3
valid_sources[0x2f] 3020 1 T84 1 T20 1 T55 8
valid_sources[0x30] 1973 1 T15 674 T72 1 T136 1
valid_sources[0x31] 2390 1 T3 1 T38 1 T15 663
valid_sources[0x32] 4278 1 T38 2 T84 1 T12 1
valid_sources[0x33] 2576 1 T12 2 T20 1 T49 1
valid_sources[0x34] 3160 1 T84 1 T15 696 T70 2
valid_sources[0x35] 2811 1 T20 1 T15 618 T16 348
valid_sources[0x36] 2865 1 T84 1 T12 3 T15 677
valid_sources[0x37] 3010 1 T84 3 T15 703 T16 372
valid_sources[0x38] 2759 1 T4 2 T38 1 T20 2
valid_sources[0x39] 2840 1 T3 1 T14 1 T38 1
valid_sources[0x3a] 3285 1 T34 1 T84 2 T15 731
valid_sources[0x3b] 2788 1 T3 1 T20 1 T57 2
valid_sources[0x3c] 2804 1 T84 1 T20 2 T57 2
valid_sources[0x3d] 2061 1 T14 1 T57 1 T15 664
valid_sources[0x3e] 2217 1 T38 2 T84 1 T49 1
valid_sources[0x3f] 2497 1 T38 1 T15 688 T73 2
valid_sources[0x40] 3234 1 T55 1 T49 1 T15 613
valid_sources[0x41] 2582 1 T38 1 T84 1 T15 637
valid_sources[0x42] 2797 1 T84 1 T55 2 T28 15
valid_sources[0x43] 2656 1 T14 3 T38 1 T20 3
valid_sources[0x44] 2071 1 T5 1 T84 1 T57 1
valid_sources[0x45] 2467 1 T38 1 T84 1 T20 1
valid_sources[0x46] 2182 1 T38 1 T84 1 T15 670
valid_sources[0x47] 3651 1 T2 64 T15 612 T72 2
valid_sources[0x48] 3170 1 T38 2 T15 646 T70 2
valid_sources[0x49] 2490 1 T38 2 T84 1 T12 2
valid_sources[0x4a] 2734 1 T3 1 T84 2 T12 1
valid_sources[0x4b] 2286 1 T3 2 T84 1 T12 1
valid_sources[0x4c] 2394 1 T20 1 T15 691 T50 1
valid_sources[0x4d] 3426 1 T3 1 T14 3 T34 1
valid_sources[0x4e] 2463 1 T15 709 T50 1 T16 335
valid_sources[0x4f] 2408 1 T26 1 T15 656 T51 2
valid_sources[0x50] 2114 1 T38 1 T15 635 T30 1
valid_sources[0x51] 3446 1 T12 1 T55 1 T15 637
valid_sources[0x52] 2558 1 T5 2 T8 2 T14 2
valid_sources[0x53] 2822 1 T38 1 T84 1 T15 633
valid_sources[0x54] 2165 1 T3 1 T38 1 T84 1
valid_sources[0x55] 3016 1 T38 1 T15 660 T72 2
valid_sources[0x56] 2219 1 T15 651 T73 2 T81 1
valid_sources[0x57] 2754 1 T3 2 T38 1 T57 1
valid_sources[0x58] 2377 1 T84 3 T15 570 T72 1
valid_sources[0x59] 2193 1 T20 1 T15 649 T72 1
valid_sources[0x5a] 2442 1 T3 1 T84 1 T15 662
valid_sources[0x5b] 2527 1 T15 623 T16 302 T137 1
valid_sources[0x5c] 2332 1 T38 1 T15 639 T97 1
valid_sources[0x5d] 2986 1 T5 2 T14 3 T38 1
valid_sources[0x5e] 2445 1 T55 3 T15 656 T72 1
valid_sources[0x5f] 2155 1 T84 1 T20 1 T55 8
valid_sources[0x60] 2413 1 T15 591 T138 1 T16 352
valid_sources[0x61] 2387 1 T38 2 T12 1 T55 3
valid_sources[0x62] 2811 1 T84 1 T15 608 T72 1
valid_sources[0x63] 3016 1 T8 2 T38 1 T36 1
valid_sources[0x64] 3119 1 T84 2 T12 1 T20 1
valid_sources[0x65] 2326 1 T8 1 T84 2 T57 1
valid_sources[0x66] 3220 1 T15 605 T72 2 T59 1
valid_sources[0x67] 2487 1 T3 1 T5 1 T38 1
valid_sources[0x68] 2812 1 T38 2 T26 1 T12 1
valid_sources[0x69] 2609 1 T84 1 T15 613 T16 348
valid_sources[0x6a] 2647 1 T84 1 T25 1 T15 622
valid_sources[0x6b] 2264 1 T3 1 T14 1 T38 1
valid_sources[0x6c] 2655 1 T3 1 T4 2 T38 1
valid_sources[0x6d] 2990 1 T84 1 T15 645 T67 2
valid_sources[0x6e] 2837 1 T8 1 T84 3 T12 1
valid_sources[0x6f] 3146 1 T15 658 T72 2 T97 7
valid_sources[0x70] 2628 1 T49 1 T15 650 T16 334
valid_sources[0x71] 2438 1 T38 1 T15 701 T72 2
valid_sources[0x72] 2514 1 T12 1 T15 638 T16 389
valid_sources[0x73] 3636 1 T84 3 T15 689 T50 1
valid_sources[0x74] 2849 1 T5 1 T84 3 T12 2
valid_sources[0x75] 3154 1 T3 1 T5 2 T26 1
valid_sources[0x76] 2790 1 T38 1 T20 2 T49 1
valid_sources[0x77] 2829 1 T84 1 T15 573 T72 1
valid_sources[0x78] 2740 1 T38 1 T20 1 T15 663
valid_sources[0x79] 2734 1 T3 2 T38 1 T84 1
valid_sources[0x7a] 2372 1 T5 1 T14 1 T15 626
valid_sources[0x7b] 2659 1 T5 2 T38 2 T15 556
valid_sources[0x7c] 2629 1 T14 2 T38 1 T55 2
valid_sources[0x7d] 2495 1 T38 1 T84 1 T15 667
valid_sources[0x7e] 3143 1 T3 1 T84 2 T15 633
valid_sources[0x7f] 2255 1 T4 1 T38 3 T20 1
valid_sources[0x80] 2331 1 T5 1 T8 2 T84 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 155299 1 T1 1 T2 29 T3 31
values[0x0] all_enables biggest_size 227346 1 T35 3 T36 5 T58 3
values[0x1] all_enables biggest_size 226503 1 T34 1 T35 1 T36 1

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