Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1433388

1

T2

124

T3

153

T4

83

full_word

905663

1

T2

17

T3

17

T4

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2338781	1			T2	141		T3	170		T4	88
auto[TlIntgErrCmd]	100	1			T74	2		T75	4		T76	7
auto[TlIntgErrData]	95	1			T74	6		T75	3		T76	8
auto[TlIntgErrBoth]	75	1			T74	2		T75	3		T76	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

385297

1

T2

141

T3

170

T4

88

auto[1]

1953754

1

T15

502603

T16

254734

T17

153327

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	169971	1			T2	124		T3	153		T4	83
auto[TlIntgErrNone]	partial	auto[1]	1263169	1			T15	325456		T16	163574		T17	98794
auto[TlIntgErrNone]	full_word	auto[0]	215202	1			T2	17		T3	17		T4	5
auto[TlIntgErrNone]	full_word	auto[1]	690439	1			T15	177147		T16	91160		T17	54533
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T74	1		T75	2		T76	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T74	1		T75	2		T76	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T125	1		T130	1		T131	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T131	1		T132	1		T123	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T74	4		T75	2		T76	3
auto[TlIntgErrData]	partial	auto[1]	43	1			T74	2		T75	1		T76	4
auto[TlIntgErrData]	full_word	auto[0]	2	1			T76	1		T131	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T125	1		T133	2		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T74	1		T75	2		T76	3
auto[TlIntgErrBoth]	partial	auto[1]	36	1			T74	1		T76	1		T122	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T75	1		T132	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T76	1		T133	1		T134	1