Unified Coverage Report :: Group :: tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
rom_ctrl_kmac_cg	100.00	1	100	1	64	64

---

Group Instance : rom_ctrl_kmac_cg
Comment: KMAC interface behaviors

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rom_ctrl_kmac_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00

Variables for Group Instance rom_ctrl_kmac_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_kmac_done	3	0	3	100.00	100	1	1	0
cp_kmac_ready	4	0	4	100.00	100	1	1	0

Summary for Variable cp_kmac_done

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_kmac_done

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
kmac_first	388	1			T2	1		T3	1		T5	2
same_cycle	13	1			T20	1		T21	1		T22	1
rom_first	1187	1			T1	2		T2	4		T3	3

---

Summary for Variable cp_kmac_ready

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_kmac_ready

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stall_repeat	142146207	1			T1	254771		T2	646874		T3	544668
stall_long	14832895	1			T1	26978		T2	68337		T3	56799
stall_1	1613016	1			T1	1094		T2	2763		T3	1786
zero_delay_5	4714796	1			T6	6		T7	32744		T9	13