Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 32812 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 407410 1 T1 3 T3 15 T4 9



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 127906 1 T1 3 T3 122 T4 9
values[0x0] 153387 1 T26 10937 T27 34366 T28 19895
values[0x1] 158929 1 T26 11275 T27 35524 T28 20912



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 15738 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 424484 1 T1 3 T3 70 T4 9



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1792 1 T6 2 T8 1 T26 129
valid_sources[0x01] 1652 1 T7 1 T8 1 T9 1
valid_sources[0x02] 1731 1 T3 2 T6 3 T12 1
valid_sources[0x03] 1912 1 T3 1 T8 1 T35 1
valid_sources[0x04] 1712 1 T7 1 T12 9 T35 1
valid_sources[0x05] 1841 1 T7 1 T8 2 T35 2
valid_sources[0x06] 1575 1 T7 3 T36 3 T115 1
valid_sources[0x07] 1706 1 T8 1 T12 2 T35 1
valid_sources[0x08] 1757 1 T36 2 T116 1 T80 1
valid_sources[0x09] 1747 1 T3 1 T7 2 T35 3
valid_sources[0x0a] 1858 1 T9 1 T26 113 T56 1
valid_sources[0x0b] 1622 1 T3 1 T6 3 T7 2
valid_sources[0x0c] 1767 1 T3 1 T6 7 T7 2
valid_sources[0x0d] 1784 1 T3 1 T12 4 T36 1
valid_sources[0x0e] 1769 1 T3 1 T35 1 T36 2
valid_sources[0x0f] 1765 1 T3 2 T6 6 T8 1
valid_sources[0x10] 1780 1 T9 1 T12 6 T36 3
valid_sources[0x11] 1755 1 T3 2 T7 2 T8 1
valid_sources[0x12] 1667 1 T3 1 T8 1 T35 4
valid_sources[0x13] 1825 1 T7 1 T35 2 T39 13
valid_sources[0x14] 1698 1 T35 2 T26 118 T50 1
valid_sources[0x15] 1541 1 T7 1 T24 1 T117 2
valid_sources[0x16] 1730 1 T3 1 T7 1 T36 1
valid_sources[0x17] 1713 1 T35 3 T36 3 T24 1
valid_sources[0x18] 1572 1 T8 1 T115 1 T26 92
valid_sources[0x19] 1717 1 T8 2 T36 1 T40 1
valid_sources[0x1a] 1684 1 T3 1 T6 2 T7 2
valid_sources[0x1b] 1641 1 T6 3 T9 1 T37 4
valid_sources[0x1c] 1771 1 T7 1 T8 1 T35 5
valid_sources[0x1d] 1751 1 T3 1 T6 2 T35 1
valid_sources[0x1e] 1642 1 T6 1 T7 1 T9 2
valid_sources[0x1f] 1728 1 T7 1 T8 3 T35 1
valid_sources[0x20] 1641 1 T7 1 T116 2 T80 1
valid_sources[0x21] 1649 1 T3 1 T9 2 T35 3
valid_sources[0x22] 1655 1 T8 2 T12 4 T35 6
valid_sources[0x23] 1685 1 T9 1 T35 1 T36 4
valid_sources[0x24] 1747 1 T35 2 T36 2 T37 1
valid_sources[0x25] 1784 1 T7 1 T8 1 T36 1
valid_sources[0x26] 1687 1 T7 3 T8 1 T36 1
valid_sources[0x27] 1652 1 T8 2 T12 4 T35 4
valid_sources[0x28] 1764 1 T3 2 T7 4 T8 1
valid_sources[0x29] 1772 1 T35 5 T36 2 T81 2
valid_sources[0x2a] 1597 1 T3 1 T6 2 T7 3
valid_sources[0x2b] 1627 1 T8 2 T9 1 T35 1
valid_sources[0x2c] 1729 1 T6 4 T9 1 T35 1
valid_sources[0x2d] 1800 1 T8 1 T35 6 T40 6
valid_sources[0x2e] 1731 1 T6 1 T7 1 T8 1
valid_sources[0x2f] 1661 1 T7 1 T35 5 T36 2
valid_sources[0x30] 1797 1 T35 8 T36 1 T115 1
valid_sources[0x31] 1874 1 T7 2 T35 1 T26 123
valid_sources[0x32] 1801 1 T3 2 T8 3 T9 1
valid_sources[0x33] 1771 1 T8 1 T35 2 T36 2
valid_sources[0x34] 1609 1 T3 1 T6 6 T8 2
valid_sources[0x35] 1705 1 T6 1 T7 1 T12 1
valid_sources[0x36] 1804 1 T6 8 T35 2 T36 1
valid_sources[0x37] 1813 1 T12 8 T35 1 T115 1
valid_sources[0x38] 1846 1 T3 1 T8 3 T35 1
valid_sources[0x39] 1784 1 T8 1 T36 1 T37 2
valid_sources[0x3a] 1691 1 T8 1 T12 1 T36 1
valid_sources[0x3b] 1732 1 T9 1 T21 1 T79 1
valid_sources[0x3c] 1660 1 T6 6 T7 1 T8 1
valid_sources[0x3d] 1691 1 T3 1 T8 1 T36 1
valid_sources[0x3e] 1828 1 T7 2 T35 5 T80 2
valid_sources[0x3f] 1755 1 T12 4 T40 1 T115 1
valid_sources[0x40] 1854 1 T3 1 T7 1 T36 1
valid_sources[0x41] 1550 1 T6 5 T7 1 T35 1
valid_sources[0x42] 1584 1 T3 1 T7 2 T9 1
valid_sources[0x43] 1731 1 T6 3 T7 1 T9 1
valid_sources[0x44] 1638 1 T12 6 T35 1 T36 1
valid_sources[0x45] 1740 1 T3 1 T35 3 T36 1
valid_sources[0x46] 1735 1 T3 1 T8 1 T35 3
valid_sources[0x47] 1586 1 T9 1 T116 1 T26 106
valid_sources[0x48] 1649 1 T7 1 T35 1 T79 6
valid_sources[0x49] 1683 1 T116 1 T26 130 T50 3
valid_sources[0x4a] 1723 1 T8 1 T9 1 T12 1
valid_sources[0x4b] 1746 1 T7 1 T9 1 T12 8
valid_sources[0x4c] 1747 1 T3 1 T7 2 T8 1
valid_sources[0x4d] 1721 1 T7 4 T8 2 T12 1
valid_sources[0x4e] 1807 1 T3 1 T8 1 T35 2
valid_sources[0x4f] 1760 1 T3 1 T7 2 T8 1
valid_sources[0x50] 1854 1 T6 5 T8 1 T35 3
valid_sources[0x51] 1807 1 T6 8 T7 1 T8 1
valid_sources[0x52] 1789 1 T39 3 T115 1 T79 1
valid_sources[0x53] 1724 1 T6 2 T8 1 T12 4
valid_sources[0x54] 1740 1 T8 1 T9 1 T36 1
valid_sources[0x55] 1685 1 T3 1 T8 1 T9 2
valid_sources[0x56] 1651 1 T3 2 T6 1 T7 6
valid_sources[0x57] 1638 1 T36 1 T38 2 T39 1
valid_sources[0x58] 1779 1 T7 3 T36 1 T37 1
valid_sources[0x59] 1707 1 T6 1 T8 1 T9 1
valid_sources[0x5a] 1629 1 T6 4 T7 1 T8 1
valid_sources[0x5b] 1721 1 T6 1 T8 1 T37 6
valid_sources[0x5c] 1768 1 T3 1 T6 1 T12 2
valid_sources[0x5d] 1684 1 T7 1 T12 2 T35 3
valid_sources[0x5e] 1612 1 T3 1 T7 4 T8 1
valid_sources[0x5f] 1693 1 T3 2 T7 1 T35 2
valid_sources[0x60] 1671 1 T3 1 T7 2 T8 1
valid_sources[0x61] 1750 1 T3 4 T8 2 T9 1
valid_sources[0x62] 1773 1 T6 2 T35 3 T36 1
valid_sources[0x63] 1750 1 T3 1 T6 1 T8 1
valid_sources[0x64] 1680 1 T3 1 T7 1 T8 1
valid_sources[0x65] 1651 1 T3 2 T6 2 T36 1
valid_sources[0x66] 1675 1 T3 1 T9 1 T36 3
valid_sources[0x67] 1680 1 T7 1 T35 1 T36 3
valid_sources[0x68] 1650 1 T7 1 T35 5 T36 3
valid_sources[0x69] 1660 1 T6 2 T8 1 T12 2
valid_sources[0x6a] 1648 1 T6 7 T12 1 T35 3
valid_sources[0x6b] 1733 1 T6 5 T8 2 T12 9
valid_sources[0x6c] 1641 1 T7 3 T8 1 T35 2
valid_sources[0x6d] 1646 1 T3 1 T7 1 T8 1
valid_sources[0x6e] 1699 1 T35 3 T38 1 T79 1
valid_sources[0x6f] 1709 1 T6 3 T7 3 T8 4
valid_sources[0x70] 1659 1 T3 1 T6 4 T8 2
valid_sources[0x71] 1775 1 T7 2 T35 1 T36 1
valid_sources[0x72] 1746 1 T7 1 T35 1 T36 2
valid_sources[0x73] 1711 1 T7 1 T36 1 T24 1
valid_sources[0x74] 1756 1 T7 1 T8 1 T35 1
valid_sources[0x75] 1799 1 T35 3 T36 2 T115 1
valid_sources[0x76] 1635 1 T6 2 T7 2 T35 2
valid_sources[0x77] 1762 1 T24 2 T115 1 T26 148
valid_sources[0x78] 1926 1 T3 1 T6 6 T8 1
valid_sources[0x79] 1743 1 T7 2 T8 1 T9 1
valid_sources[0x7a] 1699 1 T3 1 T7 1 T35 1
valid_sources[0x7b] 1775 1 T3 1 T115 1 T80 1
valid_sources[0x7c] 1723 1 T3 2 T8 1 T12 3
valid_sources[0x7d] 1623 1 T36 1 T80 1 T26 94
valid_sources[0x7e] 1711 1 T7 3 T35 2 T24 1
valid_sources[0x7f] 1763 1 T12 2 T36 2 T79 1
valid_sources[0x80] 1829 1 T3 1 T6 6 T7 4



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 103558 1 T1 3 T3 15 T4 9
values[0x0] all_enables biggest_size 152007 1 T26 10846 T27 34076 T28 19684
values[0x1] all_enables biggest_size 151845 1 T26 10782 T27 33966 T28 19886


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 36693 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 326499 1 T1 15 T2 2 T4 8



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 94107 1 T1 32 T4 18 T5 31
values[0x0] 124286 1 T2 4 T31 1 T32 7
values[0x1] 144799 1 T2 5 T31 1 T32 3



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 17887 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 345305 1 T1 18 T2 2 T4 9



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1409 1 T8 1 T25 1 T117 1
valid_sources[0x01] 1523 1 T37 1 T80 1 T26 116
valid_sources[0x02] 1378 1 T26 96 T53 2 T27 264
valid_sources[0x03] 1355 1 T6 1 T39 4 T79 2
valid_sources[0x04] 1464 1 T8 1 T38 5 T26 102
valid_sources[0x05] 1326 1 T37 1 T25 2 T26 100
valid_sources[0x06] 1436 1 T80 1 T26 85 T64 1
valid_sources[0x07] 1380 1 T8 1 T31 2 T103 2
valid_sources[0x08] 1482 1 T41 1 T25 1 T80 2
valid_sources[0x09] 1417 1 T8 1 T21 2 T24 1
valid_sources[0x0a] 1487 1 T6 1 T26 81 T50 3
valid_sources[0x0b] 1451 1 T1 1 T25 2 T26 73
valid_sources[0x0c] 1349 1 T80 2 T81 1 T103 1
valid_sources[0x0d] 1358 1 T37 2 T80 1 T26 110
valid_sources[0x0e] 1465 1 T11 2 T25 1 T103 1
valid_sources[0x0f] 1551 1 T11 1 T23 2 T26 88
valid_sources[0x10] 1384 1 T79 2 T25 3 T117 1
valid_sources[0x11] 1384 1 T61 1 T26 105 T50 1
valid_sources[0x12] 1502 1 T6 3 T25 2 T26 111
valid_sources[0x13] 1474 1 T5 13 T8 3 T11 1
valid_sources[0x14] 1416 1 T6 1 T38 1 T21 1
valid_sources[0x15] 1332 1 T11 1 T80 1 T26 84
valid_sources[0x16] 1350 1 T6 2 T24 1 T117 1
valid_sources[0x17] 1433 1 T5 3 T39 1 T117 1
valid_sources[0x18] 1366 1 T24 1 T61 3 T117 1
valid_sources[0x19] 1481 1 T25 1 T26 128 T54 1
valid_sources[0x1a] 1368 1 T25 1 T117 1 T81 2
valid_sources[0x1b] 1415 1 T37 1 T40 3 T61 1
valid_sources[0x1c] 1400 1 T26 107 T30 1 T64 1
valid_sources[0x1d] 1315 1 T11 2 T26 73 T27 298
valid_sources[0x1e] 1387 1 T6 3 T23 1 T26 74
valid_sources[0x1f] 1442 1 T25 1 T80 1 T26 79
valid_sources[0x20] 1466 1 T25 2 T80 1 T103 2
valid_sources[0x21] 1373 1 T25 2 T26 90 T50 4
valid_sources[0x22] 1431 1 T24 1 T25 1 T80 1
valid_sources[0x23] 1389 1 T103 1 T26 119 T54 1
valid_sources[0x24] 1412 1 T6 1 T24 1 T25 2
valid_sources[0x25] 1550 1 T24 1 T80 3 T81 1
valid_sources[0x26] 1466 1 T8 2 T81 1 T26 119
valid_sources[0x27] 1404 1 T6 1 T103 1 T26 135
valid_sources[0x28] 1348 1 T37 1 T62 1 T26 64
valid_sources[0x29] 1520 1 T8 1 T26 105 T118 1
valid_sources[0x2a] 1446 1 T62 1 T25 1 T26 104
valid_sources[0x2b] 1415 1 T37 1 T26 110 T53 2
valid_sources[0x2c] 1388 1 T1 4 T39 2 T24 2
valid_sources[0x2d] 1425 1 T6 1 T25 1 T103 1
valid_sources[0x2e] 1468 1 T37 1 T61 1 T103 1
valid_sources[0x2f] 1460 1 T6 2 T23 1 T79 5
valid_sources[0x30] 1435 1 T80 1 T103 1 T26 99
valid_sources[0x31] 1449 1 T6 1 T26 78 T50 2
valid_sources[0x32] 1302 1 T11 1 T79 1 T103 1
valid_sources[0x33] 1446 1 T25 1 T26 132 T50 1
valid_sources[0x34] 1454 1 T6 1 T39 7 T26 81
valid_sources[0x35] 1299 1 T6 1 T25 1 T26 89
valid_sources[0x36] 1475 1 T103 2 T26 85 T53 2
valid_sources[0x37] 1367 1 T80 1 T26 103 T27 277
valid_sources[0x38] 1336 1 T62 1 T103 2 T26 70
valid_sources[0x39] 1392 1 T81 3 T26 103 T57 4
valid_sources[0x3a] 1301 1 T24 1 T26 77 T50 1
valid_sources[0x3b] 1468 1 T26 100 T119 1 T118 1
valid_sources[0x3c] 1364 1 T6 3 T80 1 T26 85
valid_sources[0x3d] 1435 1 T80 1 T26 77 T16 2
valid_sources[0x3e] 1423 1 T25 1 T26 85 T118 1
valid_sources[0x3f] 1334 1 T26 67 T50 1 T54 1
valid_sources[0x40] 1463 1 T10 1 T40 10 T24 1
valid_sources[0x41] 1399 1 T41 1 T80 1 T81 2
valid_sources[0x42] 1400 1 T2 1 T25 1 T80 1
valid_sources[0x43] 1403 1 T10 1 T26 100 T53 2
valid_sources[0x44] 1389 1 T25 1 T26 112 T42 2
valid_sources[0x45] 1389 1 T8 3 T117 1 T26 89
valid_sources[0x46] 1396 1 T26 80 T50 1 T42 2
valid_sources[0x47] 1307 1 T21 1 T25 2 T103 1
valid_sources[0x48] 1440 1 T2 1 T8 6 T37 2
valid_sources[0x49] 1436 1 T25 2 T80 1 T117 1
valid_sources[0x4a] 1410 1 T6 2 T81 2 T26 63
valid_sources[0x4b] 1467 1 T6 2 T25 1 T80 3
valid_sources[0x4c] 1352 1 T6 2 T26 59 T120 1
valid_sources[0x4d] 1563 1 T6 2 T26 144 T50 1
valid_sources[0x4e] 1479 1 T79 2 T117 1 T26 103
valid_sources[0x4f] 1377 1 T25 2 T80 1 T26 75
valid_sources[0x50] 1467 1 T24 1 T26 95 T27 307
valid_sources[0x51] 1499 1 T80 1 T26 127 T53 1
valid_sources[0x52] 1593 1 T41 1 T29 1 T81 6
valid_sources[0x53] 1391 1 T32 1 T26 73 T121 25
valid_sources[0x54] 1301 1 T6 2 T25 1 T80 2
valid_sources[0x55] 1438 1 T24 1 T25 2 T26 85
valid_sources[0x56] 1388 1 T8 3 T37 1 T117 1
valid_sources[0x57] 1484 1 T81 5 T26 77 T122 3
valid_sources[0x58] 1404 1 T6 3 T21 1 T26 89
valid_sources[0x59] 1397 1 T26 131 T54 2 T120 1
valid_sources[0x5a] 1367 1 T11 1 T37 1 T26 126
valid_sources[0x5b] 1369 1 T8 1 T21 1 T103 1
valid_sources[0x5c] 1344 1 T5 6 T80 1 T26 75
valid_sources[0x5d] 1450 1 T117 1 T103 1 T26 87
valid_sources[0x5e] 1456 1 T117 1 T26 89 T50 1
valid_sources[0x5f] 1376 1 T25 1 T26 82 T120 1
valid_sources[0x60] 1356 1 T37 1 T80 1 T26 99
valid_sources[0x61] 1551 1 T37 1 T21 1 T25 1
valid_sources[0x62] 1449 1 T26 111 T50 1 T53 1
valid_sources[0x63] 1555 1 T5 2 T8 1 T80 1
valid_sources[0x64] 1434 1 T25 1 T26 118 T64 1
valid_sources[0x65] 1375 1 T5 2 T8 2 T41 1
valid_sources[0x66] 1433 1 T25 1 T80 2 T26 117
valid_sources[0x67] 1326 1 T26 76 T50 1 T16 2
valid_sources[0x68] 1477 1 T80 2 T26 85 T50 2
valid_sources[0x69] 1561 1 T6 2 T26 110 T54 1
valid_sources[0x6a] 1385 1 T11 2 T80 1 T26 91
valid_sources[0x6b] 1417 1 T40 9 T26 74 T50 1
valid_sources[0x6c] 1405 1 T41 1 T80 1 T26 98
valid_sources[0x6d] 1322 1 T6 1 T79 1 T81 5
valid_sources[0x6e] 1410 1 T6 2 T23 1 T26 93
valid_sources[0x6f] 1367 1 T26 106 T50 1 T119 1
valid_sources[0x70] 1568 1 T79 3 T26 88 T27 373
valid_sources[0x71] 1385 1 T6 1 T24 1 T80 2
valid_sources[0x72] 1495 1 T11 1 T26 80 T50 1
valid_sources[0x73] 1398 1 T11 1 T24 1 T26 84
valid_sources[0x74] 1456 1 T61 1 T25 1 T26 77
valid_sources[0x75] 1394 1 T8 1 T37 1 T117 1
valid_sources[0x76] 1390 1 T11 1 T25 1 T26 100
valid_sources[0x77] 1399 1 T80 1 T103 1 T26 82
valid_sources[0x78] 1424 1 T8 2 T26 95 T50 1
valid_sources[0x79] 1352 1 T6 1 T8 1 T23 1
valid_sources[0x7a] 1561 1 T11 1 T25 1 T29 4
valid_sources[0x7b] 1306 1 T21 3 T29 2 T103 1
valid_sources[0x7c] 1473 1 T21 1 T24 1 T81 1
valid_sources[0x7d] 1392 1 T26 97 T122 2 T123 1
valid_sources[0x7e] 1465 1 T21 1 T25 3 T26 102
valid_sources[0x7f] 1454 1 T6 1 T80 1 T81 1
valid_sources[0x80] 1587 1 T7 96 T81 4 T26 86



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 83163 1 T1 15 T4 8 T5 12
values[0x0] all_enables biggest_size 121365 1 T32 3 T26 7836 T65 1
values[0x1] all_enables biggest_size 121971 1 T2 2 T31 1 T61 1

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