SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rom_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[1] | 1240410 | 0 | T1 | 2 | T3 | 122 | T4 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1240237 | 1 | T1 | 2 | T3 | 122 | T4 | 6 | ||||
values[1] | 15 | 1 | T49 | 1 | T58 | 2 | T67 | 1 | ||||
values[2] | 3 | 1 | T58 | 1 | T104 | 1 | T105 | 1 | ||||
values[3] | 98 | 1 | T45 | 6 | T49 | 7 | T58 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1240243 | 1 | T1 | 2 | T3 | 122 | T4 | 6 | ||||
values[1] | 15 | 1 | T49 | 2 | T58 | 1 | T67 | 1 | ||||
values[2] | 1 | 1 | T106 | 1 | - | - | - | - | ||||
values[3] | 93 | 1 | T45 | 4 | T49 | 12 | T58 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1240160 | 1 | T1 | 2 | T3 | 122 | T4 | 6 | ||||
auto[TlIntgErrCmd] | 83 | 1 | T45 | 4 | T49 | 4 | T58 | 3 | ||||
auto[TlIntgErrData] | 77 | 1 | T45 | 3 | T49 | 3 | T58 | 2 | ||||
auto[TlIntgErrBoth] | 90 | 1 | T45 | 3 | T49 | 13 | T58 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 1035885 | 0 | T1 | 32 | T2 | 9 | T4 | 18 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1035716 | 1 | T1 | 32 | T2 | 9 | T4 | 18 | ||||
values[1] | 16 | 1 | T49 | 1 | T106 | 2 | T107 | 1 | ||||
values[2] | 2 | 1 | T45 | 1 | T104 | 1 | - | - | ||||
values[3] | 71 | 1 | T45 | 2 | T49 | 7 | T58 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1035716 | 1 | T1 | 32 | T2 | 9 | T4 | 18 | ||||
values[1] | 16 | 1 | T49 | 1 | T58 | 1 | T106 | 1 | ||||
values[2] | 5 | 1 | T108 | 1 | T109 | 1 | T110 | 1 | ||||
values[3] | 78 | 1 | T45 | 6 | T49 | 10 | T58 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1035635 | 1 | T1 | 32 | T2 | 9 | T4 | 18 | ||||
auto[TlIntgErrCmd] | 81 | 1 | T49 | 6 | T58 | 2 | T67 | 3 | ||||
auto[TlIntgErrData] | 81 | 1 | T45 | 2 | T49 | 5 | T58 | 3 | ||||
auto[TlIntgErrBoth] | 88 | 1 | T45 | 8 | T49 | 9 | T58 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |