Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

764791

1

T3

107

T6

180

T7

179

full_word

475619

1

T1

2

T3

15

T4

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1240160	1			T1	2		T3	122		T4	6
auto[TlIntgErrCmd]	83	1			T45	4		T49	4		T58	3
auto[TlIntgErrData]	77	1			T45	3		T49	3		T58	2
auto[TlIntgErrBoth]	90	1			T45	3		T49	13		T58	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

210581

1

T1

2

T3

122

T4

6

auto[1]

1029829

1

T26

71873

T27

225026

T28

141691

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	97203	1			T3	107		T6	180		T7	179
auto[TlIntgErrNone]	partial	auto[1]	667363	1			T26	46204		T27	144375		T28	94014
auto[TlIntgErrNone]	full_word	auto[0]	113270	1			T1	2		T3	15		T4	6
auto[TlIntgErrNone]	full_word	auto[1]	362324	1			T26	25669		T27	80651		T28	47677
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T45	1		T58	1		T67	2
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T45	3		T49	3		T58	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T49	1		T111	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T106	1		T112	3		T110	1
auto[TlIntgErrData]	partial	auto[0]	32	1			T45	1		T49	1		T58	1
auto[TlIntgErrData]	partial	auto[1]	34	1			T45	2		T49	2		T58	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T108	1		T107	1		T113	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T106	1		T109	1		T110	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T45	2		T49	4		T58	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T45	1		T49	9		T58	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T109	1		T114	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T112	1		T108	1		T107	1