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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.59 96.97 93.16 97.88 100.00 98.69 98.04 98.37


Total test records in report: 453
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T303 /workspace/coverage/default/34.rom_ctrl_smoke.2304973698 May 30 12:49:09 PM PDT 24 May 30 12:49:36 PM PDT 24 2775772263 ps
T304 /workspace/coverage/default/26.rom_ctrl_smoke.2130028489 May 30 12:49:09 PM PDT 24 May 30 12:50:19 PM PDT 24 8255607488 ps
T305 /workspace/coverage/default/19.rom_ctrl_alert_test.1137887427 May 30 12:48:46 PM PDT 24 May 30 12:49:12 PM PDT 24 13310610640 ps
T55 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1007500264 May 30 12:48:55 PM PDT 24 May 30 01:30:13 PM PDT 24 128023349818 ps
T306 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.312166942 May 30 12:49:09 PM PDT 24 May 30 12:49:38 PM PDT 24 6192563943 ps
T307 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4220015979 May 30 12:49:02 PM PDT 24 May 30 12:58:47 PM PDT 24 55606188779 ps
T308 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2758632038 May 30 12:49:10 PM PDT 24 May 30 12:52:32 PM PDT 24 31357375705 ps
T309 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3573317481 May 30 12:48:49 PM PDT 24 May 30 12:49:02 PM PDT 24 1034593367 ps
T310 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1527899964 May 30 12:48:43 PM PDT 24 May 30 12:51:54 PM PDT 24 24906795523 ps
T311 /workspace/coverage/default/46.rom_ctrl_stress_all.3605917214 May 30 12:49:15 PM PDT 24 May 30 12:49:29 PM PDT 24 685407959 ps
T312 /workspace/coverage/default/41.rom_ctrl_smoke.2928000189 May 30 12:49:06 PM PDT 24 May 30 12:49:54 PM PDT 24 28972723183 ps
T313 /workspace/coverage/default/31.rom_ctrl_stress_all.7308452 May 30 12:49:02 PM PDT 24 May 30 12:49:53 PM PDT 24 2952706474 ps
T314 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1572882246 May 30 12:49:13 PM PDT 24 May 30 12:49:46 PM PDT 24 15106147145 ps
T315 /workspace/coverage/default/28.rom_ctrl_smoke.3023646604 May 30 12:49:02 PM PDT 24 May 30 12:49:22 PM PDT 24 1414601246 ps
T316 /workspace/coverage/default/16.rom_ctrl_alert_test.458258125 May 30 12:48:53 PM PDT 24 May 30 12:49:27 PM PDT 24 22528805612 ps
T317 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.467856825 May 30 12:49:11 PM PDT 24 May 30 12:49:44 PM PDT 24 4006723263 ps
T318 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3619563203 May 30 12:49:01 PM PDT 24 May 30 12:49:29 PM PDT 24 5506185224 ps
T319 /workspace/coverage/default/43.rom_ctrl_alert_test.2331163545 May 30 12:49:10 PM PDT 24 May 30 12:49:40 PM PDT 24 3557248137 ps
T320 /workspace/coverage/default/31.rom_ctrl_alert_test.2556625047 May 30 12:49:08 PM PDT 24 May 30 12:49:17 PM PDT 24 176173269 ps
T321 /workspace/coverage/default/46.rom_ctrl_smoke.3521609692 May 30 12:49:15 PM PDT 24 May 30 12:49:37 PM PDT 24 839350158 ps
T322 /workspace/coverage/default/21.rom_ctrl_smoke.3607550411 May 30 12:48:48 PM PDT 24 May 30 12:49:26 PM PDT 24 11386447749 ps
T323 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3770741823 May 30 12:48:33 PM PDT 24 May 30 12:49:17 PM PDT 24 3772215013 ps
T324 /workspace/coverage/default/42.rom_ctrl_smoke.2045444593 May 30 12:49:08 PM PDT 24 May 30 12:50:01 PM PDT 24 23931171203 ps
T325 /workspace/coverage/default/25.rom_ctrl_stress_all.2004354666 May 30 12:49:10 PM PDT 24 May 30 12:49:52 PM PDT 24 2723503439 ps
T326 /workspace/coverage/default/14.rom_ctrl_alert_test.536708090 May 30 12:48:44 PM PDT 24 May 30 12:49:16 PM PDT 24 36923117601 ps
T327 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2702689864 May 30 12:48:49 PM PDT 24 May 30 12:49:42 PM PDT 24 22383838013 ps
T328 /workspace/coverage/default/35.rom_ctrl_smoke.2300195260 May 30 12:49:09 PM PDT 24 May 30 12:49:43 PM PDT 24 9951623697 ps
T329 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.91271483 May 30 12:48:39 PM PDT 24 May 30 12:48:50 PM PDT 24 701012260 ps
T330 /workspace/coverage/default/37.rom_ctrl_stress_all.1806006073 May 30 12:49:09 PM PDT 24 May 30 12:52:14 PM PDT 24 84865392743 ps
T331 /workspace/coverage/default/10.rom_ctrl_stress_all.1130119003 May 30 12:48:41 PM PDT 24 May 30 12:49:23 PM PDT 24 16496489372 ps
T332 /workspace/coverage/default/15.rom_ctrl_smoke.1908370620 May 30 12:48:44 PM PDT 24 May 30 12:49:10 PM PDT 24 671509759 ps
T333 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.710858308 May 30 12:49:02 PM PDT 24 May 30 12:54:07 PM PDT 24 59928872490 ps
T334 /workspace/coverage/default/22.rom_ctrl_alert_test.2706550032 May 30 12:48:51 PM PDT 24 May 30 12:49:19 PM PDT 24 25688938624 ps
T39 /workspace/coverage/default/1.rom_ctrl_sec_cm.3086081927 May 30 12:48:30 PM PDT 24 May 30 12:52:20 PM PDT 24 318429135 ps
T335 /workspace/coverage/default/47.rom_ctrl_alert_test.2144693231 May 30 12:49:13 PM PDT 24 May 30 12:49:29 PM PDT 24 2214774246 ps
T336 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3403801402 May 30 12:48:59 PM PDT 24 May 30 12:49:43 PM PDT 24 5120475565 ps
T337 /workspace/coverage/default/6.rom_ctrl_alert_test.609698442 May 30 12:48:45 PM PDT 24 May 30 12:48:54 PM PDT 24 918570547 ps
T338 /workspace/coverage/default/42.rom_ctrl_alert_test.2262172077 May 30 12:49:16 PM PDT 24 May 30 12:49:31 PM PDT 24 4301866758 ps
T339 /workspace/coverage/default/32.rom_ctrl_alert_test.4284458107 May 30 12:49:08 PM PDT 24 May 30 12:49:36 PM PDT 24 36957648031 ps
T340 /workspace/coverage/default/12.rom_ctrl_stress_all.1150817659 May 30 12:48:55 PM PDT 24 May 30 12:49:57 PM PDT 24 11253363930 ps
T341 /workspace/coverage/default/45.rom_ctrl_alert_test.3211633058 May 30 12:49:08 PM PDT 24 May 30 12:49:24 PM PDT 24 9943566152 ps
T342 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1717192314 May 30 12:49:10 PM PDT 24 May 30 12:55:46 PM PDT 24 21742922308 ps
T343 /workspace/coverage/default/44.rom_ctrl_alert_test.3005179953 May 30 12:49:10 PM PDT 24 May 30 12:49:33 PM PDT 24 2130384434 ps
T344 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1258274610 May 30 12:49:01 PM PDT 24 May 30 12:49:33 PM PDT 24 7149961040 ps
T345 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2710261147 May 30 12:48:40 PM PDT 24 May 30 12:49:54 PM PDT 24 42339297894 ps
T346 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2900163956 May 30 12:48:58 PM PDT 24 May 30 12:49:14 PM PDT 24 1523428063 ps
T56 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1180464901 May 30 12:48:50 PM PDT 24 May 30 01:41:56 PM PDT 24 80468684853 ps
T347 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2817150500 May 30 12:48:30 PM PDT 24 May 30 12:56:46 PM PDT 24 54706853711 ps
T57 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1017690755 May 30 12:48:41 PM PDT 24 May 30 01:04:39 PM PDT 24 168298457628 ps
T348 /workspace/coverage/default/39.rom_ctrl_smoke.3980195984 May 30 12:49:01 PM PDT 24 May 30 12:49:44 PM PDT 24 2975293038 ps
T349 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1915355243 May 30 12:48:39 PM PDT 24 May 30 12:48:56 PM PDT 24 2063385496 ps
T350 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2564423909 May 30 12:49:11 PM PDT 24 May 30 12:49:32 PM PDT 24 1718111292 ps
T351 /workspace/coverage/default/28.rom_ctrl_stress_all.642371 May 30 12:48:52 PM PDT 24 May 30 12:49:54 PM PDT 24 6117309813 ps
T352 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3276417255 May 30 12:48:52 PM PDT 24 May 30 12:49:43 PM PDT 24 10015880232 ps
T353 /workspace/coverage/default/38.rom_ctrl_smoke.3596924942 May 30 12:49:01 PM PDT 24 May 30 12:49:50 PM PDT 24 59348679918 ps
T354 /workspace/coverage/default/43.rom_ctrl_smoke.2231408357 May 30 12:49:12 PM PDT 24 May 30 12:50:01 PM PDT 24 51402012726 ps
T355 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2009350782 May 30 12:49:17 PM PDT 24 May 30 12:56:14 PM PDT 24 608576707214 ps
T356 /workspace/coverage/default/23.rom_ctrl_stress_all.3694516958 May 30 12:49:07 PM PDT 24 May 30 12:51:37 PM PDT 24 12869952972 ps
T357 /workspace/coverage/default/20.rom_ctrl_smoke.2792463491 May 30 12:48:53 PM PDT 24 May 30 12:49:14 PM PDT 24 836342391 ps
T58 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.547342154 May 30 12:49:22 PM PDT 24 May 30 12:49:42 PM PDT 24 1232153138 ps
T64 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.502306615 May 30 12:49:53 PM PDT 24 May 30 12:52:27 PM PDT 24 380912263 ps
T358 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1741739876 May 30 12:49:52 PM PDT 24 May 30 12:50:05 PM PDT 24 331700834 ps
T67 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3196914540 May 30 12:49:30 PM PDT 24 May 30 12:51:49 PM PDT 24 27716782945 ps
T65 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3481200812 May 30 12:49:52 PM PDT 24 May 30 12:51:24 PM PDT 24 2060003343 ps
T359 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2275583727 May 30 12:50:07 PM PDT 24 May 30 12:50:21 PM PDT 24 1832033643 ps
T72 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.462079951 May 30 12:49:18 PM PDT 24 May 30 12:49:30 PM PDT 24 418888885 ps
T73 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.550292524 May 30 12:49:51 PM PDT 24 May 30 12:50:24 PM PDT 24 4295192114 ps
T66 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.825142206 May 30 12:49:10 PM PDT 24 May 30 12:51:52 PM PDT 24 1998024863 ps
T360 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2638103913 May 30 12:49:28 PM PDT 24 May 30 12:49:37 PM PDT 24 184970730 ps
T74 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3726635043 May 30 12:49:52 PM PDT 24 May 30 12:51:48 PM PDT 24 10656962100 ps
T113 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1869081743 May 30 12:49:20 PM PDT 24 May 30 12:49:37 PM PDT 24 7377855645 ps
T361 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1279467992 May 30 12:49:26 PM PDT 24 May 30 12:49:48 PM PDT 24 1790068442 ps
T362 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3779460769 May 30 12:49:51 PM PDT 24 May 30 12:50:16 PM PDT 24 12044155182 ps
T363 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1826918296 May 30 12:49:30 PM PDT 24 May 30 12:49:56 PM PDT 24 2812044702 ps
T106 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2207979490 May 30 12:49:29 PM PDT 24 May 30 12:49:50 PM PDT 24 2164834071 ps
T75 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.5763468 May 30 12:49:31 PM PDT 24 May 30 12:49:52 PM PDT 24 2089178489 ps
T107 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4276136251 May 30 12:49:50 PM PDT 24 May 30 12:50:28 PM PDT 24 15274176734 ps
T364 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4131035288 May 30 12:50:06 PM PDT 24 May 30 12:50:16 PM PDT 24 737954050 ps
T365 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2189408240 May 30 12:49:19 PM PDT 24 May 30 12:49:46 PM PDT 24 2404026688 ps
T118 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4239962145 May 30 12:49:34 PM PDT 24 May 30 12:51:02 PM PDT 24 1432390380 ps
T114 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2404901388 May 30 12:49:52 PM PDT 24 May 30 12:50:49 PM PDT 24 2061247098 ps
T76 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.563244465 May 30 12:49:23 PM PDT 24 May 30 12:50:19 PM PDT 24 2108132671 ps
T366 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2632443750 May 30 12:50:07 PM PDT 24 May 30 12:53:09 PM PDT 24 44152962577 ps
T367 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3051080450 May 30 12:49:31 PM PDT 24 May 30 12:49:51 PM PDT 24 1036114160 ps
T368 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3494407786 May 30 12:49:30 PM PDT 24 May 30 12:49:52 PM PDT 24 9757606092 ps
T369 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3070120755 May 30 12:49:53 PM PDT 24 May 30 12:50:32 PM PDT 24 4222186073 ps
T77 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3369685914 May 30 12:49:15 PM PDT 24 May 30 12:49:39 PM PDT 24 2573939906 ps
T119 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.89135527 May 30 12:50:08 PM PDT 24 May 30 12:51:41 PM PDT 24 4413894871 ps
T122 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2883186039 May 30 12:49:52 PM PDT 24 May 30 12:52:37 PM PDT 24 6346811242 ps
T370 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2307587140 May 30 12:49:50 PM PDT 24 May 30 12:50:18 PM PDT 24 3077081479 ps
T128 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.970066977 May 30 12:49:52 PM PDT 24 May 30 12:51:24 PM PDT 24 6511082661 ps
T78 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3771293867 May 30 12:49:28 PM PDT 24 May 30 12:49:37 PM PDT 24 167390940 ps
T79 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1120252068 May 30 12:49:35 PM PDT 24 May 30 12:49:50 PM PDT 24 3775126788 ps
T371 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.47583291 May 30 12:50:07 PM PDT 24 May 30 12:50:36 PM PDT 24 13781242879 ps
T80 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2755562251 May 30 12:49:10 PM PDT 24 May 30 12:50:06 PM PDT 24 1086303765 ps
T81 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3119556562 May 30 12:49:51 PM PDT 24 May 30 12:51:47 PM PDT 24 41143498668 ps
T372 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3659679755 May 30 12:49:29 PM PDT 24 May 30 12:49:54 PM PDT 24 3035891723 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1626481817 May 30 12:49:26 PM PDT 24 May 30 12:49:52 PM PDT 24 11961694645 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.744529177 May 30 12:49:23 PM PDT 24 May 30 12:49:50 PM PDT 24 12127781186 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3089867543 May 30 12:49:11 PM PDT 24 May 30 12:49:40 PM PDT 24 6231203551 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3115671309 May 30 12:49:21 PM PDT 24 May 30 12:49:53 PM PDT 24 16277814744 ps
T108 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1428298745 May 30 12:50:08 PM PDT 24 May 30 12:50:30 PM PDT 24 1323232529 ps
T121 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1853324229 May 30 12:49:52 PM PDT 24 May 30 12:51:20 PM PDT 24 6347444034 ps
T85 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1086701160 May 30 12:49:32 PM PDT 24 May 30 12:52:49 PM PDT 24 112378660910 ps
T377 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2962081292 May 30 12:49:17 PM PDT 24 May 30 12:49:56 PM PDT 24 4266283227 ps
T86 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.986042130 May 30 12:49:17 PM PDT 24 May 30 12:49:41 PM PDT 24 2517184523 ps
T378 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3156701800 May 30 12:49:17 PM PDT 24 May 30 12:51:08 PM PDT 24 101259560054 ps
T109 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1760158870 May 30 12:49:29 PM PDT 24 May 30 12:50:03 PM PDT 24 8786866136 ps
T379 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.988471392 May 30 12:49:53 PM PDT 24 May 30 12:51:24 PM PDT 24 2059013638 ps
T380 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3329844920 May 30 12:49:30 PM PDT 24 May 30 12:49:43 PM PDT 24 332043226 ps
T381 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.652607353 May 30 12:49:30 PM PDT 24 May 30 12:49:42 PM PDT 24 884059653 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.684449652 May 30 12:49:29 PM PDT 24 May 30 12:49:56 PM PDT 24 6223450157 ps
T120 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2357448470 May 30 12:49:29 PM PDT 24 May 30 12:52:05 PM PDT 24 672533227 ps
T383 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1898057412 May 30 12:49:28 PM PDT 24 May 30 12:49:37 PM PDT 24 366139790 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1292106036 May 30 12:49:28 PM PDT 24 May 30 12:49:50 PM PDT 24 2494431016 ps
T384 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2024685350 May 30 12:49:28 PM PDT 24 May 30 12:49:58 PM PDT 24 3580917789 ps
T385 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1925905126 May 30 12:49:54 PM PDT 24 May 30 12:50:10 PM PDT 24 1415439869 ps
T386 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2980466498 May 30 12:49:53 PM PDT 24 May 30 12:50:15 PM PDT 24 4445394126 ps
T387 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1467159236 May 30 12:49:32 PM PDT 24 May 30 12:49:53 PM PDT 24 2053966435 ps
T388 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1423366335 May 30 12:49:23 PM PDT 24 May 30 12:49:39 PM PDT 24 1169616108 ps
T389 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.70837554 May 30 12:49:51 PM PDT 24 May 30 12:50:22 PM PDT 24 15071283965 ps
T110 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3483179657 May 30 12:49:52 PM PDT 24 May 30 12:50:21 PM PDT 24 11632265765 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2215915571 May 30 12:49:28 PM PDT 24 May 30 12:49:52 PM PDT 24 10810820815 ps
T391 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2535485466 May 30 12:49:51 PM PDT 24 May 30 12:50:17 PM PDT 24 5811016731 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.396522411 May 30 12:49:10 PM PDT 24 May 30 12:49:37 PM PDT 24 3271518547 ps
T393 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1603982840 May 30 12:49:53 PM PDT 24 May 30 12:50:26 PM PDT 24 35529551169 ps
T88 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2347268267 May 30 12:49:29 PM PDT 24 May 30 12:49:58 PM PDT 24 41012912841 ps
T394 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3884246431 May 30 12:49:52 PM PDT 24 May 30 12:50:14 PM PDT 24 10380376681 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3808997170 May 30 12:49:18 PM PDT 24 May 30 12:51:04 PM PDT 24 8559045123 ps
T396 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1149438357 May 30 12:49:51 PM PDT 24 May 30 12:50:13 PM PDT 24 9146214975 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2730388754 May 30 12:49:17 PM PDT 24 May 30 12:49:32 PM PDT 24 4123676539 ps
T111 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1506464842 May 30 12:49:53 PM PDT 24 May 30 12:50:24 PM PDT 24 15407775363 ps
T125 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.447607398 May 30 12:49:25 PM PDT 24 May 30 12:52:15 PM PDT 24 8826849439 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2763596034 May 30 12:49:24 PM PDT 24 May 30 12:49:58 PM PDT 24 5426382955 ps
T399 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.723792949 May 30 12:49:39 PM PDT 24 May 30 12:50:01 PM PDT 24 1632089463 ps
T400 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.72203865 May 30 12:49:23 PM PDT 24 May 30 12:49:50 PM PDT 24 13133950422 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2759897067 May 30 12:49:28 PM PDT 24 May 30 12:50:03 PM PDT 24 13454825649 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4245943150 May 30 12:49:29 PM PDT 24 May 30 12:49:54 PM PDT 24 3458515737 ps
T403 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1372368813 May 30 12:49:29 PM PDT 24 May 30 12:49:53 PM PDT 24 9548948612 ps
T404 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3372072412 May 30 12:49:24 PM PDT 24 May 30 12:49:33 PM PDT 24 167534383 ps
T405 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4173462119 May 30 12:49:52 PM PDT 24 May 30 12:50:14 PM PDT 24 2046524477 ps
T406 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1940935722 May 30 12:49:53 PM PDT 24 May 30 12:50:07 PM PDT 24 167746288 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.87393732 May 30 12:49:17 PM PDT 24 May 30 12:49:33 PM PDT 24 5359669578 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2214720008 May 30 12:49:26 PM PDT 24 May 30 12:50:52 PM PDT 24 5322132455 ps
T409 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.54571863 May 30 12:50:10 PM PDT 24 May 30 12:50:36 PM PDT 24 12054859983 ps
T410 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1090881151 May 30 12:49:30 PM PDT 24 May 30 12:50:00 PM PDT 24 2970418140 ps
T89 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3113190099 May 30 12:49:22 PM PDT 24 May 30 12:49:51 PM PDT 24 3474469534 ps
T411 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3879225170 May 30 12:49:25 PM PDT 24 May 30 12:49:34 PM PDT 24 1374543145 ps
T90 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4262385988 May 30 12:49:51 PM PDT 24 May 30 12:50:48 PM PDT 24 2049237944 ps
T412 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1891630325 May 30 12:49:31 PM PDT 24 May 30 12:50:03 PM PDT 24 6710209709 ps
T413 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3733824681 May 30 12:49:29 PM PDT 24 May 30 12:49:50 PM PDT 24 7862805378 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.734643065 May 30 12:49:27 PM PDT 24 May 30 12:51:03 PM PDT 24 2632991532 ps
T91 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3027575771 May 30 12:49:23 PM PDT 24 May 30 12:49:31 PM PDT 24 326103866 ps
T415 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3655435539 May 30 12:49:54 PM PDT 24 May 30 12:50:27 PM PDT 24 18096148415 ps
T117 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2384279357 May 30 12:49:53 PM PDT 24 May 30 12:51:12 PM PDT 24 7195753639 ps
T416 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3850715798 May 30 12:49:51 PM PDT 24 May 30 12:51:14 PM PDT 24 655158201 ps
T417 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3249779505 May 30 12:50:07 PM PDT 24 May 30 12:50:37 PM PDT 24 3582261507 ps
T92 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4260141571 May 30 12:49:53 PM PDT 24 May 30 12:50:14 PM PDT 24 2249576985 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1028054777 May 30 12:49:26 PM PDT 24 May 30 12:49:35 PM PDT 24 345362429 ps
T419 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1703818066 May 30 12:49:22 PM PDT 24 May 30 12:49:37 PM PDT 24 1004165595 ps
T93 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2172273823 May 30 12:49:51 PM PDT 24 May 30 12:52:01 PM PDT 24 35009146169 ps
T94 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1160509761 May 30 12:49:26 PM PDT 24 May 30 12:50:21 PM PDT 24 4297308187 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2952339141 May 30 12:49:30 PM PDT 24 May 30 12:49:54 PM PDT 24 5487479325 ps
T421 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1009191372 May 30 12:49:31 PM PDT 24 May 30 12:49:51 PM PDT 24 4094425667 ps
T422 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.722954948 May 30 12:50:10 PM PDT 24 May 30 12:50:30 PM PDT 24 6261497245 ps
T423 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.433503868 May 30 12:49:53 PM PDT 24 May 30 12:50:18 PM PDT 24 3697075260 ps
T424 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1065379911 May 30 12:49:40 PM PDT 24 May 30 12:51:03 PM PDT 24 8299401039 ps
T425 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3140460403 May 30 12:49:54 PM PDT 24 May 30 12:50:04 PM PDT 24 338475483 ps
T126 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.197792138 May 30 12:49:37 PM PDT 24 May 30 12:52:24 PM PDT 24 13678840658 ps
T426 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4045971410 May 30 12:49:54 PM PDT 24 May 30 12:50:26 PM PDT 24 15370890928 ps
T95 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2150460724 May 30 12:49:29 PM PDT 24 May 30 12:50:27 PM PDT 24 5871557788 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2673569254 May 30 12:49:29 PM PDT 24 May 30 12:49:48 PM PDT 24 6818037617 ps
T428 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2238280791 May 30 12:50:07 PM PDT 24 May 30 12:50:42 PM PDT 24 8503625292 ps
T127 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2180923293 May 30 12:50:07 PM PDT 24 May 30 12:51:50 PM PDT 24 16622889557 ps
T429 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.784811727 May 30 12:49:32 PM PDT 24 May 30 12:49:45 PM PDT 24 740700452 ps
T123 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4113606083 May 30 12:49:22 PM PDT 24 May 30 12:52:14 PM PDT 24 3904910372 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.478191810 May 30 12:49:18 PM PDT 24 May 30 12:50:47 PM PDT 24 36992055203 ps
T124 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2938855192 May 30 12:49:34 PM PDT 24 May 30 12:52:07 PM PDT 24 493348474 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.158646386 May 30 12:49:16 PM PDT 24 May 30 12:49:26 PM PDT 24 167570064 ps
T432 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1193368886 May 30 12:49:30 PM PDT 24 May 30 12:49:52 PM PDT 24 1368377331 ps
T433 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1337674875 May 30 12:49:30 PM PDT 24 May 30 12:49:39 PM PDT 24 171077682 ps
T434 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1684581410 May 30 12:49:53 PM PDT 24 May 30 12:50:04 PM PDT 24 660929276 ps
T435 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3131001499 May 30 12:49:52 PM PDT 24 May 30 12:50:09 PM PDT 24 4733367794 ps
T436 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.589736089 May 30 12:49:31 PM PDT 24 May 30 12:51:08 PM PDT 24 10653314451 ps
T437 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.23165706 May 30 12:49:19 PM PDT 24 May 30 12:50:13 PM PDT 24 2352662868 ps
T438 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1421009749 May 30 12:49:53 PM PDT 24 May 30 12:50:11 PM PDT 24 859293254 ps
T439 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.608317717 May 30 12:49:18 PM PDT 24 May 30 12:49:55 PM PDT 24 14740944648 ps
T440 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2434195890 May 30 12:50:08 PM PDT 24 May 30 12:50:36 PM PDT 24 3111835807 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1616894109 May 30 12:49:20 PM PDT 24 May 30 12:49:38 PM PDT 24 5825316749 ps
T442 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1793624995 May 30 12:49:53 PM PDT 24 May 30 12:50:09 PM PDT 24 430980041 ps
T443 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4143055601 May 30 12:49:55 PM PDT 24 May 30 12:50:14 PM PDT 24 3747235592 ps
T444 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3665283319 May 30 12:49:52 PM PDT 24 May 30 12:50:18 PM PDT 24 3535235250 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1627045065 May 30 12:49:19 PM PDT 24 May 30 12:49:41 PM PDT 24 1444068315 ps
T96 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.606595024 May 30 12:49:17 PM PDT 24 May 30 12:49:32 PM PDT 24 2163192942 ps
T446 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2342678870 May 30 12:49:29 PM PDT 24 May 30 12:49:38 PM PDT 24 171367695 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1413285098 May 30 12:49:19 PM PDT 24 May 30 12:49:59 PM PDT 24 10229717564 ps
T448 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2022691791 May 30 12:49:30 PM PDT 24 May 30 12:49:58 PM PDT 24 5204238877 ps
T449 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.169289734 May 30 12:49:31 PM PDT 24 May 30 12:49:41 PM PDT 24 517006175 ps
T450 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.57990403 May 30 12:50:07 PM PDT 24 May 30 12:52:29 PM PDT 24 57173993047 ps
T451 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.405830756 May 30 12:49:30 PM PDT 24 May 30 12:49:52 PM PDT 24 2960402550 ps
T452 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1074438668 May 30 12:49:53 PM PDT 24 May 30 12:50:05 PM PDT 24 338787594 ps
T129 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3669336843 May 30 12:49:37 PM PDT 24 May 30 12:52:12 PM PDT 24 818096212 ps
T453 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4165480975 May 30 12:49:29 PM PDT 24 May 30 12:49:45 PM PDT 24 2049820445 ps

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2719010367
Short name T10
Test name
Test status
Simulation time 3074357749 ps
CPU time 195.52 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:52:09 PM PDT 24
Peak memory 240236 kb
Host smart-bc574ec2-28be-4e83-84aa-3e096ba5f216
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719010367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2719010367
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3921934908
Short name T12
Test name
Test status
Simulation time 38568666535 ps
CPU time 5095.81 seconds
Started May 30 12:49:01 PM PDT 24
Finished May 30 02:13:58 PM PDT 24
Peak memory 235860 kb
Host smart-7fdd02ee-b355-44ee-bac6-6fe31433554d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921934908 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3921934908
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4231403848
Short name T9
Test name
Test status
Simulation time 7932031801 ps
CPU time 32.64 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:26 PM PDT 24
Peak memory 211528 kb
Host smart-e0e960de-f7f0-4141-8e64-5f169efdd288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231403848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4231403848
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4205499235
Short name T30
Test name
Test status
Simulation time 36318789867 ps
CPU time 247.69 seconds
Started May 30 12:48:35 PM PDT 24
Finished May 30 12:52:44 PM PDT 24
Peak memory 240532 kb
Host smart-8326f989-90ca-4db3-a508-dc7928caf87c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205499235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4205499235
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3320780847
Short name T22
Test name
Test status
Simulation time 261697221354 ps
CPU time 390.76 seconds
Started May 30 12:48:50 PM PDT 24
Finished May 30 12:55:22 PM PDT 24
Peak memory 227708 kb
Host smart-9d08178f-98d7-4e78-9f1f-2e2869c47a97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320780847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3320780847
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4239962145
Short name T118
Test name
Test status
Simulation time 1432390380 ps
CPU time 87.43 seconds
Started May 30 12:49:34 PM PDT 24
Finished May 30 12:51:02 PM PDT 24
Peak memory 212352 kb
Host smart-c2c4d546-b05c-45c0-9326-138e0db029e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239962145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.4239962145
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.4123681825
Short name T19
Test name
Test status
Simulation time 22239942870 ps
CPU time 3159.43 seconds
Started May 30 12:49:01 PM PDT 24
Finished May 30 01:41:42 PM PDT 24
Peak memory 228724 kb
Host smart-3e1c8cfa-4932-45e4-a7ea-0721280bae27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123681825 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.4123681825
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.668824568
Short name T34
Test name
Test status
Simulation time 7069637708 ps
CPU time 228.46 seconds
Started May 30 12:48:27 PM PDT 24
Finished May 30 12:52:16 PM PDT 24
Peak memory 238520 kb
Host smart-24ea2695-b58c-4409-b3f8-c1e586e599f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668824568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.668824568
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4235721618
Short name T7
Test name
Test status
Simulation time 4304718947 ps
CPU time 34.21 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:49:28 PM PDT 24
Peak memory 212188 kb
Host smart-ff112879-b416-495e-868d-5965f96486a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235721618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4235721618
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3726635043
Short name T74
Test name
Test status
Simulation time 10656962100 ps
CPU time 115.68 seconds
Started May 30 12:49:52 PM PDT 24
Finished May 30 12:51:48 PM PDT 24
Peak memory 215720 kb
Host smart-6ba62d4d-64e2-49ec-b6a4-dd72f3fad7c0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726635043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3726635043
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2883186039
Short name T122
Test name
Test status
Simulation time 6346811242 ps
CPU time 164.73 seconds
Started May 30 12:49:52 PM PDT 24
Finished May 30 12:52:37 PM PDT 24
Peak memory 219496 kb
Host smart-4d95be03-371b-4f86-b799-7e93ef774dca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883186039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2883186039
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2357448470
Short name T120
Test name
Test status
Simulation time 672533227 ps
CPU time 154.51 seconds
Started May 30 12:49:29 PM PDT 24
Finished May 30 12:52:05 PM PDT 24
Peak memory 214000 kb
Host smart-317fd3eb-3e76-4a80-ac45-4d327f9ea7d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357448470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2357448470
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3069514821
Short name T8
Test name
Test status
Simulation time 14680920963 ps
CPU time 30.2 seconds
Started May 30 12:48:31 PM PDT 24
Finished May 30 12:49:02 PM PDT 24
Peak memory 212992 kb
Host smart-df5b1285-246d-47ee-ae2f-4973dc9ac597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069514821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3069514821
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4251325766
Short name T265
Test name
Test status
Simulation time 346201726 ps
CPU time 19.16 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 12:49:02 PM PDT 24
Peak memory 214768 kb
Host smart-0c9a288f-2f7e-4d73-b4ba-b491a5dd7f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251325766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4251325766
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.673731875
Short name T25
Test name
Test status
Simulation time 6541455347 ps
CPU time 30.99 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:49:34 PM PDT 24
Peak memory 215276 kb
Host smart-7ec7779a-852b-404a-818c-c8bc9339415a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673731875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.673731875
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1863879677
Short name T59
Test name
Test status
Simulation time 46166780805 ps
CPU time 95.72 seconds
Started May 30 12:49:12 PM PDT 24
Finished May 30 12:50:49 PM PDT 24
Peak memory 219452 kb
Host smart-fb9a661d-d587-4718-9fa6-9f074a05b8b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863879677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1863879677
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2150460724
Short name T95
Test name
Test status
Simulation time 5871557788 ps
CPU time 57.38 seconds
Started May 30 12:49:29 PM PDT 24
Finished May 30 12:50:27 PM PDT 24
Peak memory 214304 kb
Host smart-b8b46fc8-2fdc-4418-8087-9d44b14eefa0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150460724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2150460724
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.89135527
Short name T119
Test name
Test status
Simulation time 4413894871 ps
CPU time 90.54 seconds
Started May 30 12:50:08 PM PDT 24
Finished May 30 12:51:41 PM PDT 24
Peak memory 213888 kb
Host smart-2f3e80fc-f002-47bf-9284-f0d553da64fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89135527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_int
g_err.89135527
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2975520095
Short name T84
Test name
Test status
Simulation time 26353655819 ps
CPU time 66.89 seconds
Started May 30 12:48:32 PM PDT 24
Finished May 30 12:49:40 PM PDT 24
Peak memory 218776 kb
Host smart-df5da5fe-9f6b-424d-9b86-6727f56163f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975520095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2975520095
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1326003100
Short name T97
Test name
Test status
Simulation time 4170954813 ps
CPU time 34 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:49:44 PM PDT 24
Peak memory 211328 kb
Host smart-7d76bdb8-ee05-47d6-8fa5-e90acf551ce2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326003100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1326003100
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3744219411
Short name T18
Test name
Test status
Simulation time 228945302185 ps
CPU time 2093.5 seconds
Started May 30 12:48:58 PM PDT 24
Finished May 30 01:23:53 PM PDT 24
Peak memory 239612 kb
Host smart-002c2e3e-0696-4c3c-acbd-350e12a0678f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744219411 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3744219411
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3113190099
Short name T89
Test name
Test status
Simulation time 3474469534 ps
CPU time 28.41 seconds
Started May 30 12:49:22 PM PDT 24
Finished May 30 12:49:51 PM PDT 24
Peak memory 211840 kb
Host smart-06a8b1ea-e96a-4675-ae65-a74758988179
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113190099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3113190099
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1423366335
Short name T388
Test name
Test status
Simulation time 1169616108 ps
CPU time 15.54 seconds
Started May 30 12:49:23 PM PDT 24
Finished May 30 12:49:39 PM PDT 24
Peak memory 211148 kb
Host smart-589214a9-cc4b-4493-a5f0-784915bef5a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423366335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1423366335
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.608317717
Short name T439
Test name
Test status
Simulation time 14740944648 ps
CPU time 35.5 seconds
Started May 30 12:49:18 PM PDT 24
Finished May 30 12:49:55 PM PDT 24
Peak memory 212228 kb
Host smart-3d760baf-57ef-446f-8c82-257696a060cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608317717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.608317717
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1898057412
Short name T383
Test name
Test status
Simulation time 366139790 ps
CPU time 8.55 seconds
Started May 30 12:49:28 PM PDT 24
Finished May 30 12:49:37 PM PDT 24
Peak memory 216092 kb
Host smart-3f727b71-9cf9-49c2-99e4-60e6fdbf94f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898057412 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1898057412
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3369685914
Short name T77
Test name
Test status
Simulation time 2573939906 ps
CPU time 23.01 seconds
Started May 30 12:49:15 PM PDT 24
Finished May 30 12:49:39 PM PDT 24
Peak memory 211888 kb
Host smart-64810dcb-5335-4647-af86-926c04bdfce1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369685914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3369685914
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1028054777
Short name T418
Test name
Test status
Simulation time 345362429 ps
CPU time 8.23 seconds
Started May 30 12:49:26 PM PDT 24
Finished May 30 12:49:35 PM PDT 24
Peak memory 211084 kb
Host smart-7c641970-0c61-462e-b402-3a094726387d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028054777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1028054777
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.396522411
Short name T392
Test name
Test status
Simulation time 3271518547 ps
CPU time 25.92 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 12:49:37 PM PDT 24
Peak memory 211248 kb
Host smart-31220a29-81ff-4c60-aeb0-2bff8d84523d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396522411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
396522411
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2755562251
Short name T80
Test name
Test status
Simulation time 1086303765 ps
CPU time 55.21 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 12:50:06 PM PDT 24
Peak memory 214304 kb
Host smart-eba0011c-1c64-44ad-b442-1dace11ea044
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755562251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2755562251
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.158646386
Short name T431
Test name
Test status
Simulation time 167570064 ps
CPU time 8.29 seconds
Started May 30 12:49:16 PM PDT 24
Finished May 30 12:49:26 PM PDT 24
Peak memory 211124 kb
Host smart-4b596955-b5e7-4e40-a38b-55f70af4e5bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158646386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.158646386
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3089867543
Short name T375
Test name
Test status
Simulation time 6231203551 ps
CPU time 28.72 seconds
Started May 30 12:49:11 PM PDT 24
Finished May 30 12:49:40 PM PDT 24
Peak memory 217600 kb
Host smart-c9b206de-0610-47a4-a086-c1a732eee76c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089867543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3089867543
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.825142206
Short name T66
Test name
Test status
Simulation time 1998024863 ps
CPU time 161.28 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 12:51:52 PM PDT 24
Peak memory 213832 kb
Host smart-8f7015d2-9266-4111-924c-1efa25e0b277
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825142206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.825142206
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.72203865
Short name T400
Test name
Test status
Simulation time 13133950422 ps
CPU time 27.34 seconds
Started May 30 12:49:23 PM PDT 24
Finished May 30 12:49:50 PM PDT 24
Peak memory 211896 kb
Host smart-9f8fc425-0d0b-46bd-9d0b-71a3523d032b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72203865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasi
ng.72203865
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.606595024
Short name T96
Test name
Test status
Simulation time 2163192942 ps
CPU time 13.83 seconds
Started May 30 12:49:17 PM PDT 24
Finished May 30 12:49:32 PM PDT 24
Peak memory 219444 kb
Host smart-b65511d7-e99b-4441-81f1-bc1aaa44ae37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606595024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.606595024
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2962081292
Short name T377
Test name
Test status
Simulation time 4266283227 ps
CPU time 38.75 seconds
Started May 30 12:49:17 PM PDT 24
Finished May 30 12:49:56 PM PDT 24
Peak memory 211660 kb
Host smart-b0f946d9-810e-4a92-afbf-f8e12737bd2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962081292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2962081292
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2215915571
Short name T390
Test name
Test status
Simulation time 10810820815 ps
CPU time 24.06 seconds
Started May 30 12:49:28 PM PDT 24
Finished May 30 12:49:52 PM PDT 24
Peak memory 214564 kb
Host smart-426cac4a-b869-44ba-a904-4584b9d84de1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215915571 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2215915571
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.462079951
Short name T72
Test name
Test status
Simulation time 418888885 ps
CPU time 11 seconds
Started May 30 12:49:18 PM PDT 24
Finished May 30 12:49:30 PM PDT 24
Peak memory 211152 kb
Host smart-a8542d17-8bd5-4603-a067-78477b9e1277
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462079951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.462079951
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2730388754
Short name T397
Test name
Test status
Simulation time 4123676539 ps
CPU time 14.03 seconds
Started May 30 12:49:17 PM PDT 24
Finished May 30 12:49:32 PM PDT 24
Peak memory 211060 kb
Host smart-6d7e8557-743c-4458-8cf8-cc2123fcce07
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730388754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2730388754
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.87393732
Short name T407
Test name
Test status
Simulation time 5359669578 ps
CPU time 14.93 seconds
Started May 30 12:49:17 PM PDT 24
Finished May 30 12:49:33 PM PDT 24
Peak memory 211212 kb
Host smart-1d121632-32ae-47b4-b55d-5d21472e30e6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87393732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.87393732
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3156701800
Short name T378
Test name
Test status
Simulation time 101259560054 ps
CPU time 110.61 seconds
Started May 30 12:49:17 PM PDT 24
Finished May 30 12:51:08 PM PDT 24
Peak memory 213356 kb
Host smart-a7455802-d116-4588-ae89-20b01b714fb4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156701800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3156701800
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3733824681
Short name T413
Test name
Test status
Simulation time 7862805378 ps
CPU time 19.66 seconds
Started May 30 12:49:29 PM PDT 24
Finished May 30 12:49:50 PM PDT 24
Peak memory 212444 kb
Host smart-17236fff-5278-4781-9256-791fabd6f210
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733824681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3733824681
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2189408240
Short name T365
Test name
Test status
Simulation time 2404026688 ps
CPU time 25.69 seconds
Started May 30 12:49:19 PM PDT 24
Finished May 30 12:49:46 PM PDT 24
Peak memory 218344 kb
Host smart-40fc4126-fcfa-42cc-862b-425a5c5b2c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189408240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2189408240
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.447607398
Short name T125
Test name
Test status
Simulation time 8826849439 ps
CPU time 169.37 seconds
Started May 30 12:49:25 PM PDT 24
Finished May 30 12:52:15 PM PDT 24
Peak memory 214164 kb
Host smart-9f0b925f-a34b-4942-ac93-46d87f8b62b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447607398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.447607398
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2307587140
Short name T370
Test name
Test status
Simulation time 3077081479 ps
CPU time 26.68 seconds
Started May 30 12:49:50 PM PDT 24
Finished May 30 12:50:18 PM PDT 24
Peak memory 218664 kb
Host smart-c80b2120-857f-4a21-b874-d6b6d18559d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307587140 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2307587140
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1467159236
Short name T387
Test name
Test status
Simulation time 2053966435 ps
CPU time 20.42 seconds
Started May 30 12:49:32 PM PDT 24
Finished May 30 12:49:53 PM PDT 24
Peak memory 211456 kb
Host smart-5ab69e79-1e92-4081-8b48-01b3c29922c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467159236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1467159236
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.589736089
Short name T436
Test name
Test status
Simulation time 10653314451 ps
CPU time 96.31 seconds
Started May 30 12:49:31 PM PDT 24
Finished May 30 12:51:08 PM PDT 24
Peak memory 214504 kb
Host smart-b4eac711-3c51-453f-a486-b2084503c802
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589736089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.589736089
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4276136251
Short name T107
Test name
Test status
Simulation time 15274176734 ps
CPU time 36.76 seconds
Started May 30 12:49:50 PM PDT 24
Finished May 30 12:50:28 PM PDT 24
Peak memory 212768 kb
Host smart-b2194da4-8ca4-44a8-b945-6ecbd8fbcb6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276136251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4276136251
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1891630325
Short name T412
Test name
Test status
Simulation time 6710209709 ps
CPU time 31.14 seconds
Started May 30 12:49:31 PM PDT 24
Finished May 30 12:50:03 PM PDT 24
Peak memory 217780 kb
Host smart-14da2512-39d3-4367-a7b0-7f7e28018340
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891630325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1891630325
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.197792138
Short name T126
Test name
Test status
Simulation time 13678840658 ps
CPU time 166.61 seconds
Started May 30 12:49:37 PM PDT 24
Finished May 30 12:52:24 PM PDT 24
Peak memory 219368 kb
Host smart-f9cc92ef-1889-4ee1-9302-899050fdba50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197792138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.197792138
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3665283319
Short name T444
Test name
Test status
Simulation time 3535235250 ps
CPU time 25.39 seconds
Started May 30 12:49:52 PM PDT 24
Finished May 30 12:50:18 PM PDT 24
Peak memory 216780 kb
Host smart-23a5bbe8-eb7f-4ad6-8084-41f8eae3dc40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665283319 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3665283319
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3131001499
Short name T435
Test name
Test status
Simulation time 4733367794 ps
CPU time 15.6 seconds
Started May 30 12:49:52 PM PDT 24
Finished May 30 12:50:09 PM PDT 24
Peak memory 212020 kb
Host smart-d556d276-e7f6-49bd-80ea-798544fb24fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131001499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3131001499
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4143055601
Short name T443
Test name
Test status
Simulation time 3747235592 ps
CPU time 18.61 seconds
Started May 30 12:49:55 PM PDT 24
Finished May 30 12:50:14 PM PDT 24
Peak memory 212072 kb
Host smart-3cc083fe-81e9-4a14-b78d-d9dba6d9df97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143055601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4143055601
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1421009749
Short name T438
Test name
Test status
Simulation time 859293254 ps
CPU time 16.8 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:50:11 PM PDT 24
Peak memory 219452 kb
Host smart-e9f2ff7f-82bb-4f98-8c4a-fa7420e2fe2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421009749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1421009749
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3779460769
Short name T362
Test name
Test status
Simulation time 12044155182 ps
CPU time 24.33 seconds
Started May 30 12:49:51 PM PDT 24
Finished May 30 12:50:16 PM PDT 24
Peak memory 219452 kb
Host smart-fa607111-17fd-4700-889e-b550748770a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779460769 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3779460769
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.70837554
Short name T389
Test name
Test status
Simulation time 15071283965 ps
CPU time 29.91 seconds
Started May 30 12:49:51 PM PDT 24
Finished May 30 12:50:22 PM PDT 24
Peak memory 212052 kb
Host smart-346c1e42-db99-4e9b-8500-bcd81bf4ad87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70837554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.70837554
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3119556562
Short name T81
Test name
Test status
Simulation time 41143498668 ps
CPU time 115.34 seconds
Started May 30 12:49:51 PM PDT 24
Finished May 30 12:51:47 PM PDT 24
Peak memory 215424 kb
Host smart-ab906ace-8cce-45ed-9f4a-0ac5bf5e4c01
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119556562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3119556562
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3483179657
Short name T110
Test name
Test status
Simulation time 11632265765 ps
CPU time 27.8 seconds
Started May 30 12:49:52 PM PDT 24
Finished May 30 12:50:21 PM PDT 24
Peak memory 212708 kb
Host smart-184b8200-2dbe-4af8-8de2-4aaefe6d9c02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483179657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3483179657
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1793624995
Short name T442
Test name
Test status
Simulation time 430980041 ps
CPU time 14.57 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:50:09 PM PDT 24
Peak memory 217472 kb
Host smart-b753a534-d4d9-4293-b255-d3cb7b4011d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793624995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1793624995
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3481200812
Short name T65
Test name
Test status
Simulation time 2060003343 ps
CPU time 90.9 seconds
Started May 30 12:49:52 PM PDT 24
Finished May 30 12:51:24 PM PDT 24
Peak memory 213652 kb
Host smart-fc10c7ea-afa2-4e97-8ba4-7af98f1d97c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481200812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3481200812
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1684581410
Short name T434
Test name
Test status
Simulation time 660929276 ps
CPU time 9.95 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:50:04 PM PDT 24
Peak memory 213392 kb
Host smart-e5acbef9-24d5-4e2b-86f1-832c293b65fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684581410 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1684581410
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1506464842
Short name T111
Test name
Test status
Simulation time 15407775363 ps
CPU time 29.85 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:50:24 PM PDT 24
Peak memory 211864 kb
Host smart-aa1f3aa6-4683-4deb-a45e-9e85a383473f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506464842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1506464842
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4262385988
Short name T90
Test name
Test status
Simulation time 2049237944 ps
CPU time 55.54 seconds
Started May 30 12:49:51 PM PDT 24
Finished May 30 12:50:48 PM PDT 24
Peak memory 214320 kb
Host smart-38d77642-8676-458d-bf0b-32f713a29c7f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262385988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.4262385988
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3140460403
Short name T425
Test name
Test status
Simulation time 338475483 ps
CPU time 8.79 seconds
Started May 30 12:49:54 PM PDT 24
Finished May 30 12:50:04 PM PDT 24
Peak memory 211140 kb
Host smart-418dc601-a32a-4e80-b05a-a7d2a79e455c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140460403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3140460403
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1925905126
Short name T385
Test name
Test status
Simulation time 1415439869 ps
CPU time 15.52 seconds
Started May 30 12:49:54 PM PDT 24
Finished May 30 12:50:10 PM PDT 24
Peak memory 219484 kb
Host smart-a57adae4-79cf-43fa-adbc-76a030ce3d05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925905126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1925905126
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.970066977
Short name T128
Test name
Test status
Simulation time 6511082661 ps
CPU time 90.46 seconds
Started May 30 12:49:52 PM PDT 24
Finished May 30 12:51:24 PM PDT 24
Peak memory 219492 kb
Host smart-ee22f958-fbda-4cd9-a90e-54cfd8cb6b40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970066977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.970066977
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3884246431
Short name T394
Test name
Test status
Simulation time 10380376681 ps
CPU time 20.8 seconds
Started May 30 12:49:52 PM PDT 24
Finished May 30 12:50:14 PM PDT 24
Peak memory 217096 kb
Host smart-d52efc49-94ac-49d5-9b7d-647f09745074
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884246431 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3884246431
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1149438357
Short name T396
Test name
Test status
Simulation time 9146214975 ps
CPU time 21.99 seconds
Started May 30 12:49:51 PM PDT 24
Finished May 30 12:50:13 PM PDT 24
Peak memory 212052 kb
Host smart-8a387104-4feb-4883-8e2c-dfc1507c6409
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149438357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1149438357
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4045971410
Short name T426
Test name
Test status
Simulation time 15370890928 ps
CPU time 30.75 seconds
Started May 30 12:49:54 PM PDT 24
Finished May 30 12:50:26 PM PDT 24
Peak memory 212652 kb
Host smart-3085a69d-c2c8-47f2-8d45-220457f9cbfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045971410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4045971410
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.433503868
Short name T423
Test name
Test status
Simulation time 3697075260 ps
CPU time 23.73 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:50:18 PM PDT 24
Peak memory 219428 kb
Host smart-fa46f603-a947-4197-9fb3-dcd489284fea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433503868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.433503868
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.502306615
Short name T64
Test name
Test status
Simulation time 380912263 ps
CPU time 153.38 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:52:27 PM PDT 24
Peak memory 214176 kb
Host smart-3a816a34-b40c-494c-bffe-9d63cfaa1599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502306615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.502306615
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2980466498
Short name T386
Test name
Test status
Simulation time 4445394126 ps
CPU time 21.62 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:50:15 PM PDT 24
Peak memory 217348 kb
Host smart-ab0117d0-3688-460a-b03a-45fcf2a848a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980466498 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2980466498
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2535485466
Short name T391
Test name
Test status
Simulation time 5811016731 ps
CPU time 24.96 seconds
Started May 30 12:49:51 PM PDT 24
Finished May 30 12:50:17 PM PDT 24
Peak memory 211796 kb
Host smart-4a9e2af9-cbcc-4a2c-bc1a-dcd03e4e1b42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535485466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2535485466
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2172273823
Short name T93
Test name
Test status
Simulation time 35009146169 ps
CPU time 128.73 seconds
Started May 30 12:49:51 PM PDT 24
Finished May 30 12:52:01 PM PDT 24
Peak memory 213616 kb
Host smart-14288418-8e9c-4706-b7c9-98161ddbcb7a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172273823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2172273823
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4173462119
Short name T405
Test name
Test status
Simulation time 2046524477 ps
CPU time 20.9 seconds
Started May 30 12:49:52 PM PDT 24
Finished May 30 12:50:14 PM PDT 24
Peak memory 211892 kb
Host smart-6411d5c9-20d1-44ee-a624-4db5af3548bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173462119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4173462119
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1741739876
Short name T358
Test name
Test status
Simulation time 331700834 ps
CPU time 12.6 seconds
Started May 30 12:49:52 PM PDT 24
Finished May 30 12:50:05 PM PDT 24
Peak memory 217404 kb
Host smart-83d033c2-b637-4634-8d2b-ec61b7b21761
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741739876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1741739876
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1853324229
Short name T121
Test name
Test status
Simulation time 6347444034 ps
CPU time 86.97 seconds
Started May 30 12:49:52 PM PDT 24
Finished May 30 12:51:20 PM PDT 24
Peak memory 219368 kb
Host smart-ca8b2903-8736-4046-af00-88f05a79ee32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853324229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1853324229
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1603982840
Short name T393
Test name
Test status
Simulation time 35529551169 ps
CPU time 32.17 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:50:26 PM PDT 24
Peak memory 216340 kb
Host smart-55899a0c-8bf7-4cd5-8a33-b2d01c62bf69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603982840 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1603982840
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.550292524
Short name T73
Test name
Test status
Simulation time 4295192114 ps
CPU time 32.05 seconds
Started May 30 12:49:51 PM PDT 24
Finished May 30 12:50:24 PM PDT 24
Peak memory 212068 kb
Host smart-561896a5-b950-4d89-8a2c-9721ef350d62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550292524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.550292524
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2384279357
Short name T117
Test name
Test status
Simulation time 7195753639 ps
CPU time 78.2 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:51:12 PM PDT 24
Peak memory 213660 kb
Host smart-7bc90bb7-bed5-4ae1-ba8f-ffa964532728
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384279357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2384279357
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1074438668
Short name T452
Test name
Test status
Simulation time 338787594 ps
CPU time 10.71 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:50:05 PM PDT 24
Peak memory 211260 kb
Host smart-d1fe1ce7-0250-42e9-b866-42e691e52bf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074438668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1074438668
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1940935722
Short name T406
Test name
Test status
Simulation time 167746288 ps
CPU time 12.87 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:50:07 PM PDT 24
Peak memory 217704 kb
Host smart-fb0aa20f-06f0-4c26-acbc-c6f4411d46f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940935722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1940935722
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.988471392
Short name T379
Test name
Test status
Simulation time 2059013638 ps
CPU time 90.06 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:51:24 PM PDT 24
Peak memory 212484 kb
Host smart-8dc2e619-015d-49b1-813f-e0ed850259c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988471392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.988471392
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2434195890
Short name T440
Test name
Test status
Simulation time 3111835807 ps
CPU time 26.06 seconds
Started May 30 12:50:08 PM PDT 24
Finished May 30 12:50:36 PM PDT 24
Peak memory 218068 kb
Host smart-2200226d-b940-4eff-96d9-12eedb52295e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434195890 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2434195890
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4260141571
Short name T92
Test name
Test status
Simulation time 2249576985 ps
CPU time 20.38 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:50:14 PM PDT 24
Peak memory 211828 kb
Host smart-dc9e1881-bf6a-4bf5-8161-45220f8b6946
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260141571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4260141571
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2404901388
Short name T114
Test name
Test status
Simulation time 2061247098 ps
CPU time 55.64 seconds
Started May 30 12:49:52 PM PDT 24
Finished May 30 12:50:49 PM PDT 24
Peak memory 214288 kb
Host smart-1f758f70-ff76-4822-8b42-d12b1219e64a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404901388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2404901388
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3655435539
Short name T415
Test name
Test status
Simulation time 18096148415 ps
CPU time 31.84 seconds
Started May 30 12:49:54 PM PDT 24
Finished May 30 12:50:27 PM PDT 24
Peak memory 212856 kb
Host smart-810ff310-6506-4abd-8b4f-f36a3318f6e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655435539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3655435539
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3070120755
Short name T369
Test name
Test status
Simulation time 4222186073 ps
CPU time 37.46 seconds
Started May 30 12:49:53 PM PDT 24
Finished May 30 12:50:32 PM PDT 24
Peak memory 218660 kb
Host smart-8a624ad5-3155-45e2-9735-bdbe539fbd37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070120755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3070120755
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3850715798
Short name T416
Test name
Test status
Simulation time 655158201 ps
CPU time 82.18 seconds
Started May 30 12:49:51 PM PDT 24
Finished May 30 12:51:14 PM PDT 24
Peak memory 213676 kb
Host smart-e0d904b0-2dfe-4e34-a998-646dc88f6d71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850715798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3850715798
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3249779505
Short name T417
Test name
Test status
Simulation time 3582261507 ps
CPU time 28.56 seconds
Started May 30 12:50:07 PM PDT 24
Finished May 30 12:50:37 PM PDT 24
Peak memory 216572 kb
Host smart-ace1365d-a2c2-40ae-9d3a-cc6a823bac22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249779505 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3249779505
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.722954948
Short name T422
Test name
Test status
Simulation time 6261497245 ps
CPU time 17.89 seconds
Started May 30 12:50:10 PM PDT 24
Finished May 30 12:50:30 PM PDT 24
Peak memory 212420 kb
Host smart-2ca94a21-c7ff-43b0-99d5-06a50265eb1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722954948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.722954948
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2632443750
Short name T366
Test name
Test status
Simulation time 44152962577 ps
CPU time 180.29 seconds
Started May 30 12:50:07 PM PDT 24
Finished May 30 12:53:09 PM PDT 24
Peak memory 215420 kb
Host smart-1a131917-e0ca-43fb-acc7-4fc4a13fbb50
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632443750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2632443750
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2238280791
Short name T428
Test name
Test status
Simulation time 8503625292 ps
CPU time 33.15 seconds
Started May 30 12:50:07 PM PDT 24
Finished May 30 12:50:42 PM PDT 24
Peak memory 212552 kb
Host smart-a481b571-e6c2-4419-a9b5-b26ff0c11be0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238280791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2238280791
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2275583727
Short name T359
Test name
Test status
Simulation time 1832033643 ps
CPU time 12.01 seconds
Started May 30 12:50:07 PM PDT 24
Finished May 30 12:50:21 PM PDT 24
Peak memory 217316 kb
Host smart-baa0ce1f-e2df-4ebc-8516-f5b253f2e831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275583727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2275583727
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4131035288
Short name T364
Test name
Test status
Simulation time 737954050 ps
CPU time 8.86 seconds
Started May 30 12:50:06 PM PDT 24
Finished May 30 12:50:16 PM PDT 24
Peak memory 216428 kb
Host smart-c71f1340-10b9-4166-9895-c2e6f68c959a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131035288 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.4131035288
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.54571863
Short name T409
Test name
Test status
Simulation time 12054859983 ps
CPU time 24.12 seconds
Started May 30 12:50:10 PM PDT 24
Finished May 30 12:50:36 PM PDT 24
Peak memory 212140 kb
Host smart-5ef3b0c9-43dc-48d4-b370-11df1e1d9174
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54571863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.54571863
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.57990403
Short name T450
Test name
Test status
Simulation time 57173993047 ps
CPU time 141.12 seconds
Started May 30 12:50:07 PM PDT 24
Finished May 30 12:52:29 PM PDT 24
Peak memory 215412 kb
Host smart-ada58cac-81df-42dc-bd13-7127b2786fef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57990403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pas
sthru_mem_tl_intg_err.57990403
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1428298745
Short name T108
Test name
Test status
Simulation time 1323232529 ps
CPU time 19.95 seconds
Started May 30 12:50:08 PM PDT 24
Finished May 30 12:50:30 PM PDT 24
Peak memory 212120 kb
Host smart-c5557f7b-a4a5-4ee3-bfd1-2eea6ca1d482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428298745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1428298745
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.47583291
Short name T371
Test name
Test status
Simulation time 13781242879 ps
CPU time 27.31 seconds
Started May 30 12:50:07 PM PDT 24
Finished May 30 12:50:36 PM PDT 24
Peak memory 219480 kb
Host smart-4664af42-c8ad-43ef-81d2-4a3160856d93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47583291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.47583291
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2180923293
Short name T127
Test name
Test status
Simulation time 16622889557 ps
CPU time 101.59 seconds
Started May 30 12:50:07 PM PDT 24
Finished May 30 12:51:50 PM PDT 24
Peak memory 219464 kb
Host smart-f202b767-3197-4623-bd53-f77622493d4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180923293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2180923293
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3027575771
Short name T91
Test name
Test status
Simulation time 326103866 ps
CPU time 7.99 seconds
Started May 30 12:49:23 PM PDT 24
Finished May 30 12:49:31 PM PDT 24
Peak memory 211180 kb
Host smart-819596b3-d64d-48ba-8e66-c3226ebe9336
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027575771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3027575771
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1869081743
Short name T113
Test name
Test status
Simulation time 7377855645 ps
CPU time 16.98 seconds
Started May 30 12:49:20 PM PDT 24
Finished May 30 12:49:37 PM PDT 24
Peak memory 212116 kb
Host smart-7f4f9ace-fc0f-4381-a667-c0605d3e9ddd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869081743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1869081743
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1413285098
Short name T447
Test name
Test status
Simulation time 10229717564 ps
CPU time 39.41 seconds
Started May 30 12:49:19 PM PDT 24
Finished May 30 12:49:59 PM PDT 24
Peak memory 212032 kb
Host smart-1841a6a5-1b10-47f9-9a7d-e00fe9c56f7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413285098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1413285098
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2638103913
Short name T360
Test name
Test status
Simulation time 184970730 ps
CPU time 8.67 seconds
Started May 30 12:49:28 PM PDT 24
Finished May 30 12:49:37 PM PDT 24
Peak memory 216316 kb
Host smart-66e5cd3e-0963-4b86-b8ca-b865357d05eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638103913 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2638103913
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.744529177
Short name T374
Test name
Test status
Simulation time 12127781186 ps
CPU time 26.22 seconds
Started May 30 12:49:23 PM PDT 24
Finished May 30 12:49:50 PM PDT 24
Peak memory 212408 kb
Host smart-e8568e85-b943-4c04-b130-005dd5290e7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744529177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.744529177
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3115671309
Short name T376
Test name
Test status
Simulation time 16277814744 ps
CPU time 31.23 seconds
Started May 30 12:49:21 PM PDT 24
Finished May 30 12:49:53 PM PDT 24
Peak memory 211164 kb
Host smart-8da715fb-78fb-49dd-90f6-3af75bfcbd65
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115671309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3115671309
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1616894109
Short name T441
Test name
Test status
Simulation time 5825316749 ps
CPU time 17.09 seconds
Started May 30 12:49:20 PM PDT 24
Finished May 30 12:49:38 PM PDT 24
Peak memory 211224 kb
Host smart-322a1d93-fec7-4521-8fc0-618a0849c548
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616894109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1616894109
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.478191810
Short name T430
Test name
Test status
Simulation time 36992055203 ps
CPU time 88.56 seconds
Started May 30 12:49:18 PM PDT 24
Finished May 30 12:50:47 PM PDT 24
Peak memory 214256 kb
Host smart-a55784ea-abd8-4fcf-ad5f-65c1fdfe2aa5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478191810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.478191810
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.169289734
Short name T449
Test name
Test status
Simulation time 517006175 ps
CPU time 9.79 seconds
Started May 30 12:49:31 PM PDT 24
Finished May 30 12:49:41 PM PDT 24
Peak memory 211276 kb
Host smart-37c98c71-8fff-49c6-9da7-cc68e2d7855e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169289734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.169289734
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2763596034
Short name T398
Test name
Test status
Simulation time 5426382955 ps
CPU time 34.24 seconds
Started May 30 12:49:24 PM PDT 24
Finished May 30 12:49:58 PM PDT 24
Peak memory 217700 kb
Host smart-04fe3291-77c4-45f5-aca9-b75ae6fb1e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763596034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2763596034
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3808997170
Short name T395
Test name
Test status
Simulation time 8559045123 ps
CPU time 104.7 seconds
Started May 30 12:49:18 PM PDT 24
Finished May 30 12:51:04 PM PDT 24
Peak memory 214504 kb
Host smart-029fbaa6-f925-45bb-892b-31878ac9e468
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808997170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3808997170
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.684449652
Short name T382
Test name
Test status
Simulation time 6223450157 ps
CPU time 25.92 seconds
Started May 30 12:49:29 PM PDT 24
Finished May 30 12:49:56 PM PDT 24
Peak memory 219388 kb
Host smart-f1150e4c-260f-4084-b160-d135e66f09b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684449652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.684449652
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3771293867
Short name T78
Test name
Test status
Simulation time 167390940 ps
CPU time 8.59 seconds
Started May 30 12:49:28 PM PDT 24
Finished May 30 12:49:37 PM PDT 24
Peak memory 211264 kb
Host smart-ee4df2d0-3365-438b-84d6-086987054de3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771293867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3771293867
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2759897067
Short name T401
Test name
Test status
Simulation time 13454825649 ps
CPU time 34.78 seconds
Started May 30 12:49:28 PM PDT 24
Finished May 30 12:50:03 PM PDT 24
Peak memory 212184 kb
Host smart-2f2bfd4a-6de1-4b0b-970c-96ee1f119fa5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759897067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2759897067
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2024685350
Short name T384
Test name
Test status
Simulation time 3580917789 ps
CPU time 29.02 seconds
Started May 30 12:49:28 PM PDT 24
Finished May 30 12:49:58 PM PDT 24
Peak memory 217220 kb
Host smart-643a260f-ffb9-485e-a3f3-072d4cdc3beb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024685350 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2024685350
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.986042130
Short name T86
Test name
Test status
Simulation time 2517184523 ps
CPU time 22.58 seconds
Started May 30 12:49:17 PM PDT 24
Finished May 30 12:49:41 PM PDT 24
Peak memory 211284 kb
Host smart-ddce008c-415a-49fa-a858-30925a9bbbdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986042130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.986042130
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1337674875
Short name T433
Test name
Test status
Simulation time 171077682 ps
CPU time 7.85 seconds
Started May 30 12:49:30 PM PDT 24
Finished May 30 12:49:39 PM PDT 24
Peak memory 210936 kb
Host smart-fa531833-8b2e-4297-b0fc-93d87293c49d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337674875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1337674875
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2952339141
Short name T420
Test name
Test status
Simulation time 5487479325 ps
CPU time 23.12 seconds
Started May 30 12:49:30 PM PDT 24
Finished May 30 12:49:54 PM PDT 24
Peak memory 211236 kb
Host smart-e81a3dac-a337-4d87-a3ec-7bdb6cc702b8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952339141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2952339141
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3196914540
Short name T67
Test name
Test status
Simulation time 27716782945 ps
CPU time 138.14 seconds
Started May 30 12:49:30 PM PDT 24
Finished May 30 12:51:49 PM PDT 24
Peak memory 215292 kb
Host smart-b09ba46b-1950-439e-a050-fa4dcb809df4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196914540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3196914540
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2673569254
Short name T427
Test name
Test status
Simulation time 6818037617 ps
CPU time 17.9 seconds
Started May 30 12:49:29 PM PDT 24
Finished May 30 12:49:48 PM PDT 24
Peak memory 219384 kb
Host smart-c971e53b-0c58-4fb3-82f6-f13930a42f95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673569254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2673569254
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2022691791
Short name T448
Test name
Test status
Simulation time 5204238877 ps
CPU time 27.45 seconds
Started May 30 12:49:30 PM PDT 24
Finished May 30 12:49:58 PM PDT 24
Peak memory 218700 kb
Host smart-280813fa-603b-4e75-aafc-9e55ef6b5fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022691791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2022691791
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.734643065
Short name T414
Test name
Test status
Simulation time 2632991532 ps
CPU time 95.17 seconds
Started May 30 12:49:27 PM PDT 24
Finished May 30 12:51:03 PM PDT 24
Peak memory 213552 kb
Host smart-c33cec7e-6bcd-4351-84c6-764c3ec99976
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734643065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.734643065
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1292106036
Short name T87
Test name
Test status
Simulation time 2494431016 ps
CPU time 21.36 seconds
Started May 30 12:49:28 PM PDT 24
Finished May 30 12:49:50 PM PDT 24
Peak memory 211500 kb
Host smart-63f7515d-1c92-4d65-bbf0-f2277f45a9a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292106036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1292106036
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3659679755
Short name T372
Test name
Test status
Simulation time 3035891723 ps
CPU time 23.59 seconds
Started May 30 12:49:29 PM PDT 24
Finished May 30 12:49:54 PM PDT 24
Peak memory 211476 kb
Host smart-09d5d8a5-a135-4616-aaea-101d38eb887a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659679755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3659679755
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2347268267
Short name T88
Test name
Test status
Simulation time 41012912841 ps
CPU time 27.68 seconds
Started May 30 12:49:29 PM PDT 24
Finished May 30 12:49:58 PM PDT 24
Peak memory 212004 kb
Host smart-51d330ca-805c-4481-bf4a-cccb01bf20bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347268267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2347268267
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3494407786
Short name T368
Test name
Test status
Simulation time 9757606092 ps
CPU time 21.24 seconds
Started May 30 12:49:30 PM PDT 24
Finished May 30 12:49:52 PM PDT 24
Peak memory 219572 kb
Host smart-55d82831-3b3a-4179-b655-5fea65159f09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494407786 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3494407786
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1626481817
Short name T373
Test name
Test status
Simulation time 11961694645 ps
CPU time 24.72 seconds
Started May 30 12:49:26 PM PDT 24
Finished May 30 12:49:52 PM PDT 24
Peak memory 212168 kb
Host smart-90283d86-420d-41b3-aad4-d8e298c911f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626481817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1626481817
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3372072412
Short name T404
Test name
Test status
Simulation time 167534383 ps
CPU time 7.82 seconds
Started May 30 12:49:24 PM PDT 24
Finished May 30 12:49:33 PM PDT 24
Peak memory 210964 kb
Host smart-72f8d9b3-d8f2-4ba8-be70-bc0f803c265a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372072412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3372072412
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4245943150
Short name T402
Test name
Test status
Simulation time 3458515737 ps
CPU time 24.29 seconds
Started May 30 12:49:29 PM PDT 24
Finished May 30 12:49:54 PM PDT 24
Peak memory 211144 kb
Host smart-5ad5b9a0-14f6-4517-b739-d81af55fee1b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245943150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4245943150
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.23165706
Short name T437
Test name
Test status
Simulation time 2352662868 ps
CPU time 53.08 seconds
Started May 30 12:49:19 PM PDT 24
Finished May 30 12:50:13 PM PDT 24
Peak memory 213340 kb
Host smart-68c39429-45d7-4825-9361-32a003ef2ea2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23165706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pass
thru_mem_tl_intg_err.23165706
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1627045065
Short name T445
Test name
Test status
Simulation time 1444068315 ps
CPU time 20.73 seconds
Started May 30 12:49:19 PM PDT 24
Finished May 30 12:49:41 PM PDT 24
Peak memory 212324 kb
Host smart-b335c867-993a-40b4-bd7a-2dc491bb78f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627045065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1627045065
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3329844920
Short name T380
Test name
Test status
Simulation time 332043226 ps
CPU time 12.54 seconds
Started May 30 12:49:30 PM PDT 24
Finished May 30 12:49:43 PM PDT 24
Peak memory 217392 kb
Host smart-52383f61-252f-4f23-8dcf-76b649bb76fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329844920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3329844920
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2214720008
Short name T408
Test name
Test status
Simulation time 5322132455 ps
CPU time 85.34 seconds
Started May 30 12:49:26 PM PDT 24
Finished May 30 12:50:52 PM PDT 24
Peak memory 213836 kb
Host smart-0e50e69b-c570-495e-8630-69eec8cea00d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214720008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2214720008
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1703818066
Short name T419
Test name
Test status
Simulation time 1004165595 ps
CPU time 15.06 seconds
Started May 30 12:49:22 PM PDT 24
Finished May 30 12:49:37 PM PDT 24
Peak memory 219468 kb
Host smart-87c89e29-049a-4c2f-9ac7-29a97f51ad38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703818066 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1703818066
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3879225170
Short name T411
Test name
Test status
Simulation time 1374543145 ps
CPU time 8.01 seconds
Started May 30 12:49:25 PM PDT 24
Finished May 30 12:49:34 PM PDT 24
Peak memory 211120 kb
Host smart-ab296a01-4241-4328-818c-5aeedf4aefbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879225170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3879225170
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1160509761
Short name T94
Test name
Test status
Simulation time 4297308187 ps
CPU time 54.07 seconds
Started May 30 12:49:26 PM PDT 24
Finished May 30 12:50:21 PM PDT 24
Peak memory 214636 kb
Host smart-c955494d-ebc7-4fe0-b650-484965a0e21c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160509761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1160509761
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1090881151
Short name T410
Test name
Test status
Simulation time 2970418140 ps
CPU time 28.63 seconds
Started May 30 12:49:30 PM PDT 24
Finished May 30 12:50:00 PM PDT 24
Peak memory 212260 kb
Host smart-f26ce6e4-cd94-4b7b-a51b-ccdf155e5057
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090881151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1090881151
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1279467992
Short name T361
Test name
Test status
Simulation time 1790068442 ps
CPU time 21.77 seconds
Started May 30 12:49:26 PM PDT 24
Finished May 30 12:49:48 PM PDT 24
Peak memory 218192 kb
Host smart-97a68901-f41d-4474-abae-e30c0a61ffa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279467992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1279467992
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2342678870
Short name T446
Test name
Test status
Simulation time 171367695 ps
CPU time 8.53 seconds
Started May 30 12:49:29 PM PDT 24
Finished May 30 12:49:38 PM PDT 24
Peak memory 213812 kb
Host smart-ac97b913-d759-4446-acac-1641e3365837
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342678870 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2342678870
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1009191372
Short name T421
Test name
Test status
Simulation time 4094425667 ps
CPU time 19.45 seconds
Started May 30 12:49:31 PM PDT 24
Finished May 30 12:49:51 PM PDT 24
Peak memory 211868 kb
Host smart-772a2290-72c8-4a6b-bee3-d89375910edc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009191372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1009191372
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.563244465
Short name T76
Test name
Test status
Simulation time 2108132671 ps
CPU time 55.86 seconds
Started May 30 12:49:23 PM PDT 24
Finished May 30 12:50:19 PM PDT 24
Peak memory 214320 kb
Host smart-501640df-1e0b-4f9b-8f70-03dcdab06030
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563244465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.563244465
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1760158870
Short name T109
Test name
Test status
Simulation time 8786866136 ps
CPU time 32.29 seconds
Started May 30 12:49:29 PM PDT 24
Finished May 30 12:50:03 PM PDT 24
Peak memory 212548 kb
Host smart-817ea0f4-10e1-4963-8c59-6e7c04aeb469
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760158870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1760158870
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.547342154
Short name T58
Test name
Test status
Simulation time 1232153138 ps
CPU time 19.17 seconds
Started May 30 12:49:22 PM PDT 24
Finished May 30 12:49:42 PM PDT 24
Peak memory 217292 kb
Host smart-79a8717f-989f-40d0-9596-69faba30faf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547342154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.547342154
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4113606083
Short name T123
Test name
Test status
Simulation time 3904910372 ps
CPU time 171.02 seconds
Started May 30 12:49:22 PM PDT 24
Finished May 30 12:52:14 PM PDT 24
Peak memory 214068 kb
Host smart-621d3110-bb72-41c8-9987-5adc92b740bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113606083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.4113606083
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4165480975
Short name T453
Test name
Test status
Simulation time 2049820445 ps
CPU time 15.23 seconds
Started May 30 12:49:29 PM PDT 24
Finished May 30 12:49:45 PM PDT 24
Peak memory 216696 kb
Host smart-32129be7-3815-40e0-a205-890937a2a9db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165480975 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4165480975
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1372368813
Short name T403
Test name
Test status
Simulation time 9548948612 ps
CPU time 22.42 seconds
Started May 30 12:49:29 PM PDT 24
Finished May 30 12:49:53 PM PDT 24
Peak memory 212356 kb
Host smart-dd2ef2bd-f563-4528-9805-eedaabfb586d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372368813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1372368813
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1065379911
Short name T424
Test name
Test status
Simulation time 8299401039 ps
CPU time 82.47 seconds
Started May 30 12:49:40 PM PDT 24
Finished May 30 12:51:03 PM PDT 24
Peak memory 214700 kb
Host smart-2d7d5929-7627-469c-8a69-725891a63122
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065379911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1065379911
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.723792949
Short name T399
Test name
Test status
Simulation time 1632089463 ps
CPU time 20.96 seconds
Started May 30 12:49:39 PM PDT 24
Finished May 30 12:50:01 PM PDT 24
Peak memory 212228 kb
Host smart-282ec7b1-18b8-40fc-98d5-6ccba04175f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723792949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.723792949
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3051080450
Short name T367
Test name
Test status
Simulation time 1036114160 ps
CPU time 19.24 seconds
Started May 30 12:49:31 PM PDT 24
Finished May 30 12:49:51 PM PDT 24
Peak memory 218324 kb
Host smart-d592fd79-0098-461e-953c-904648ab4712
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051080450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3051080450
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2938855192
Short name T124
Test name
Test status
Simulation time 493348474 ps
CPU time 152.45 seconds
Started May 30 12:49:34 PM PDT 24
Finished May 30 12:52:07 PM PDT 24
Peak memory 214880 kb
Host smart-641578c4-f6db-41dd-9501-491fce1d9bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938855192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2938855192
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.652607353
Short name T381
Test name
Test status
Simulation time 884059653 ps
CPU time 11.53 seconds
Started May 30 12:49:30 PM PDT 24
Finished May 30 12:49:42 PM PDT 24
Peak memory 216032 kb
Host smart-e57f4781-f3fe-45ef-8ba8-eff9f51b46b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652607353 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.652607353
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1120252068
Short name T79
Test name
Test status
Simulation time 3775126788 ps
CPU time 14.36 seconds
Started May 30 12:49:35 PM PDT 24
Finished May 30 12:49:50 PM PDT 24
Peak memory 211308 kb
Host smart-50345340-d65b-4f6f-9262-bacd5e56d914
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120252068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1120252068
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1086701160
Short name T85
Test name
Test status
Simulation time 112378660910 ps
CPU time 196.21 seconds
Started May 30 12:49:32 PM PDT 24
Finished May 30 12:52:49 PM PDT 24
Peak memory 215428 kb
Host smart-038181b1-c3ef-48f7-8e21-77aded4e2ce4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086701160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1086701160
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.784811727
Short name T429
Test name
Test status
Simulation time 740700452 ps
CPU time 12.8 seconds
Started May 30 12:49:32 PM PDT 24
Finished May 30 12:49:45 PM PDT 24
Peak memory 211248 kb
Host smart-2e7997f6-7e41-47cf-9a3e-15e3c5823aaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784811727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.784811727
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1193368886
Short name T432
Test name
Test status
Simulation time 1368377331 ps
CPU time 21.33 seconds
Started May 30 12:49:30 PM PDT 24
Finished May 30 12:49:52 PM PDT 24
Peak memory 218748 kb
Host smart-3f3c74ae-4268-4e01-aa59-0a4d7b181f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193368886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1193368886
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3669336843
Short name T129
Test name
Test status
Simulation time 818096212 ps
CPU time 154.72 seconds
Started May 30 12:49:37 PM PDT 24
Finished May 30 12:52:12 PM PDT 24
Peak memory 213968 kb
Host smart-26b498bf-078d-4ab1-8f0c-99a973c2d606
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669336843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3669336843
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1826918296
Short name T363
Test name
Test status
Simulation time 2812044702 ps
CPU time 25.24 seconds
Started May 30 12:49:30 PM PDT 24
Finished May 30 12:49:56 PM PDT 24
Peak memory 216608 kb
Host smart-fb95a10c-4f04-4567-8ff1-121ea3e7f599
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826918296 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1826918296
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.5763468
Short name T75
Test name
Test status
Simulation time 2089178489 ps
CPU time 20.33 seconds
Started May 30 12:49:31 PM PDT 24
Finished May 30 12:49:52 PM PDT 24
Peak memory 211436 kb
Host smart-237e2df3-bf70-4c0e-9701-8227884e3dfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5763468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.5763468
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2207979490
Short name T106
Test name
Test status
Simulation time 2164834071 ps
CPU time 20.12 seconds
Started May 30 12:49:29 PM PDT 24
Finished May 30 12:49:50 PM PDT 24
Peak memory 211860 kb
Host smart-76ec00c3-4867-4c74-b0b5-6004922d7a87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207979490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2207979490
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.405830756
Short name T451
Test name
Test status
Simulation time 2960402550 ps
CPU time 20.87 seconds
Started May 30 12:49:30 PM PDT 24
Finished May 30 12:49:52 PM PDT 24
Peak memory 218608 kb
Host smart-3fb65f6c-d462-438f-82bc-fba97333269e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405830756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.405830756
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2056093611
Short name T283
Test name
Test status
Simulation time 9233143673 ps
CPU time 33.23 seconds
Started May 30 12:48:27 PM PDT 24
Finished May 30 12:49:02 PM PDT 24
Peak memory 211544 kb
Host smart-7958049b-ece5-427d-b985-42ec146f3923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056093611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2056093611
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2472964881
Short name T208
Test name
Test status
Simulation time 27424261047 ps
CPU time 332.08 seconds
Started May 30 12:48:30 PM PDT 24
Finished May 30 12:54:03 PM PDT 24
Peak memory 239932 kb
Host smart-059be1c7-785c-4adb-918c-57f4ecb2d914
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472964881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2472964881
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3234216807
Short name T166
Test name
Test status
Simulation time 4066747412 ps
CPU time 25.05 seconds
Started May 30 12:48:30 PM PDT 24
Finished May 30 12:48:57 PM PDT 24
Peak memory 212444 kb
Host smart-f9771447-bb89-4aae-a23d-1f0e7010d579
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3234216807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3234216807
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.219317976
Short name T33
Test name
Test status
Simulation time 1483235392 ps
CPU time 127.66 seconds
Started May 30 12:48:31 PM PDT 24
Finished May 30 12:50:40 PM PDT 24
Peak memory 237332 kb
Host smart-b6461e5c-2a45-4a65-9cee-12986d754331
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219317976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.219317976
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3322271740
Short name T200
Test name
Test status
Simulation time 4968155307 ps
CPU time 54.23 seconds
Started May 30 12:48:33 PM PDT 24
Finished May 30 12:49:28 PM PDT 24
Peak memory 216992 kb
Host smart-3b8b2391-a0b5-4c36-b923-57cd740e1483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322271740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3322271740
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2643553721
Short name T99
Test name
Test status
Simulation time 52870035346 ps
CPU time 137.98 seconds
Started May 30 12:48:30 PM PDT 24
Finished May 30 12:50:50 PM PDT 24
Peak memory 219120 kb
Host smart-c76fc87b-fcef-4216-815f-2ccdba1f2681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643553721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2643553721
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1759057188
Short name T280
Test name
Test status
Simulation time 32614689655 ps
CPU time 27.6 seconds
Started May 30 12:48:30 PM PDT 24
Finished May 30 12:48:59 PM PDT 24
Peak memory 211344 kb
Host smart-656f4e69-da97-4d38-8688-110ccf040c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759057188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1759057188
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1848875771
Short name T49
Test name
Test status
Simulation time 56412331543 ps
CPU time 523.4 seconds
Started May 30 12:48:29 PM PDT 24
Finished May 30 12:57:13 PM PDT 24
Peak memory 229672 kb
Host smart-1a91a05e-ab74-4282-824a-2d264bbf2453
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848875771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1848875771
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2770791414
Short name T262
Test name
Test status
Simulation time 35917081053 ps
CPU time 55.81 seconds
Started May 30 12:48:29 PM PDT 24
Finished May 30 12:49:26 PM PDT 24
Peak memory 215088 kb
Host smart-1b86b792-04e1-4a48-8369-5027f285e56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770791414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2770791414
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2202955588
Short name T284
Test name
Test status
Simulation time 358772626 ps
CPU time 10.26 seconds
Started May 30 12:48:30 PM PDT 24
Finished May 30 12:48:42 PM PDT 24
Peak memory 212280 kb
Host smart-a49c147b-bea1-4986-be4e-9b3bc6ef56fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2202955588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2202955588
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3086081927
Short name T39
Test name
Test status
Simulation time 318429135 ps
CPU time 228.33 seconds
Started May 30 12:48:30 PM PDT 24
Finished May 30 12:52:20 PM PDT 24
Peak memory 238084 kb
Host smart-e682152c-d516-4cb5-8e78-b7db1fd5f612
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086081927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3086081927
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2640532027
Short name T134
Test name
Test status
Simulation time 9382193346 ps
CPU time 52.36 seconds
Started May 30 12:48:27 PM PDT 24
Finished May 30 12:49:20 PM PDT 24
Peak memory 218464 kb
Host smart-d0675557-145b-4b41-bf16-236d2a058d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640532027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2640532027
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1124242519
Short name T290
Test name
Test status
Simulation time 13352699005 ps
CPU time 28.44 seconds
Started May 30 12:48:44 PM PDT 24
Finished May 30 12:49:13 PM PDT 24
Peak memory 212168 kb
Host smart-5a6de481-d0d0-48f9-adc7-984cf25afff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124242519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1124242519
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1831676629
Short name T302
Test name
Test status
Simulation time 4145482225 ps
CPU time 294.21 seconds
Started May 30 12:48:47 PM PDT 24
Finished May 30 12:53:42 PM PDT 24
Peak memory 240876 kb
Host smart-f26683f2-0fc6-4897-b763-21348ea5c13f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831676629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1831676629
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2788703754
Short name T180
Test name
Test status
Simulation time 262962751 ps
CPU time 12.59 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:06 PM PDT 24
Peak memory 212344 kb
Host smart-b0ea04d3-5cb9-4c32-9afe-cce7a98b689e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2788703754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2788703754
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.4106141551
Short name T237
Test name
Test status
Simulation time 1558455021 ps
CPU time 20.01 seconds
Started May 30 12:48:43 PM PDT 24
Finished May 30 12:49:03 PM PDT 24
Peak memory 216764 kb
Host smart-944d5f38-aa9c-45a5-b1d2-57ca8d2a18ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106141551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.4106141551
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1130119003
Short name T331
Test name
Test status
Simulation time 16496489372 ps
CPU time 41.26 seconds
Started May 30 12:48:41 PM PDT 24
Finished May 30 12:49:23 PM PDT 24
Peak memory 212732 kb
Host smart-2d4b078a-2321-41b6-8a50-a2ab68bd8b64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130119003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1130119003
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1911602689
Short name T167
Test name
Test status
Simulation time 3604722510 ps
CPU time 28.8 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:22 PM PDT 24
Peak memory 211364 kb
Host smart-131d4705-d700-41e6-b552-bf0824544ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911602689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1911602689
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1311417838
Short name T145
Test name
Test status
Simulation time 11117709270 ps
CPU time 288.52 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 12:53:31 PM PDT 24
Peak memory 217000 kb
Host smart-814387db-6502-4e5b-a1f2-5aeb2f23c320
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311417838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1311417838
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.115132160
Short name T272
Test name
Test status
Simulation time 16386137331 ps
CPU time 43.63 seconds
Started May 30 12:48:49 PM PDT 24
Finished May 30 12:49:35 PM PDT 24
Peak memory 215352 kb
Host smart-486b5883-b64e-42dd-b7ef-10c308cfd8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115132160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.115132160
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3152268479
Short name T292
Test name
Test status
Simulation time 180764283 ps
CPU time 10.75 seconds
Started May 30 12:48:47 PM PDT 24
Finished May 30 12:48:58 PM PDT 24
Peak memory 212240 kb
Host smart-570da4d5-ff69-4b47-8dec-300ea560ee6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3152268479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3152268479
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.4267474599
Short name T6
Test name
Test status
Simulation time 7093200430 ps
CPU time 49.67 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 12:49:32 PM PDT 24
Peak memory 217596 kb
Host smart-a4c2b3a1-b7d8-46a5-9d01-9cb528dd11de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267474599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.4267474599
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.992805594
Short name T229
Test name
Test status
Simulation time 30879857001 ps
CPU time 61.79 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 12:49:45 PM PDT 24
Peak memory 217812 kb
Host smart-f6ac8027-6b67-4076-82c4-54e0062f556b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992805594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.992805594
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.411297458
Short name T295
Test name
Test status
Simulation time 24677408967 ps
CPU time 21.54 seconds
Started May 30 12:48:43 PM PDT 24
Finished May 30 12:49:06 PM PDT 24
Peak memory 212308 kb
Host smart-3954d0fe-d8e4-4f91-8766-dcc9efa7958e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411297458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.411297458
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1527899964
Short name T310
Test name
Test status
Simulation time 24906795523 ps
CPU time 190.04 seconds
Started May 30 12:48:43 PM PDT 24
Finished May 30 12:51:54 PM PDT 24
Peak memory 237912 kb
Host smart-38ac6cc7-d623-4dd4-84ab-11070a85ef05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527899964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1527899964
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3276417255
Short name T352
Test name
Test status
Simulation time 10015880232 ps
CPU time 49.76 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:43 PM PDT 24
Peak memory 215104 kb
Host smart-7cdf1b35-2361-4544-8987-66c632fe3bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276417255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3276417255
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2730012460
Short name T249
Test name
Test status
Simulation time 2703842165 ps
CPU time 25.96 seconds
Started May 30 12:48:45 PM PDT 24
Finished May 30 12:49:12 PM PDT 24
Peak memory 211464 kb
Host smart-271e7aae-5263-44e1-8bfb-964f9dbf39c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2730012460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2730012460
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2313622392
Short name T257
Test name
Test status
Simulation time 11544903764 ps
CPU time 58.86 seconds
Started May 30 12:48:43 PM PDT 24
Finished May 30 12:49:43 PM PDT 24
Peak memory 217804 kb
Host smart-fa89d5e9-2efb-49e7-bfdc-5bed61e85c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313622392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2313622392
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1150817659
Short name T340
Test name
Test status
Simulation time 11253363930 ps
CPU time 61.71 seconds
Started May 30 12:48:55 PM PDT 24
Finished May 30 12:49:57 PM PDT 24
Peak memory 220804 kb
Host smart-6d9bbac9-c0f7-48b3-ab10-39bb95c8b3d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150817659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1150817659
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2965581864
Short name T160
Test name
Test status
Simulation time 495438267 ps
CPU time 12.01 seconds
Started May 30 12:48:44 PM PDT 24
Finished May 30 12:48:57 PM PDT 24
Peak memory 211248 kb
Host smart-4df34be0-6f5f-4cb7-87d4-66d752531b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965581864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2965581864
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4051040952
Short name T285
Test name
Test status
Simulation time 84175206707 ps
CPU time 984.12 seconds
Started May 30 12:48:40 PM PDT 24
Finished May 30 01:05:04 PM PDT 24
Peak memory 238340 kb
Host smart-8eb29028-111a-4d83-826d-e44f7c50e08c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051040952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4051040952
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1606691106
Short name T288
Test name
Test status
Simulation time 27175009246 ps
CPU time 58.16 seconds
Started May 30 12:48:49 PM PDT 24
Finished May 30 12:49:48 PM PDT 24
Peak memory 214968 kb
Host smart-2c4115b8-2fe3-41b7-9e78-b0f1fdebc9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606691106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1606691106
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2769598961
Short name T153
Test name
Test status
Simulation time 1923815431 ps
CPU time 21.93 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:16 PM PDT 24
Peak memory 212532 kb
Host smart-bc826c63-3936-412b-94a3-f9664f8c2885
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2769598961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2769598961
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.740497143
Short name T13
Test name
Test status
Simulation time 5655812571 ps
CPU time 55.55 seconds
Started May 30 12:48:43 PM PDT 24
Finished May 30 12:49:39 PM PDT 24
Peak memory 214720 kb
Host smart-ef3dad70-e0a1-4ed2-810a-67d52677db7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740497143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.740497143
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1711960023
Short name T207
Test name
Test status
Simulation time 10413600823 ps
CPU time 72.36 seconds
Started May 30 12:48:51 PM PDT 24
Finished May 30 12:50:05 PM PDT 24
Peak memory 219356 kb
Host smart-4f68a412-7fbb-477c-bb31-fc52ad0b9e60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711960023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1711960023
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.536708090
Short name T326
Test name
Test status
Simulation time 36923117601 ps
CPU time 30.98 seconds
Started May 30 12:48:44 PM PDT 24
Finished May 30 12:49:16 PM PDT 24
Peak memory 211308 kb
Host smart-ea94068f-4a2e-4b06-8d75-55af5b1de794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536708090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.536708090
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1701287051
Short name T104
Test name
Test status
Simulation time 59132347740 ps
CPU time 338 seconds
Started May 30 12:48:43 PM PDT 24
Finished May 30 12:54:22 PM PDT 24
Peak memory 234168 kb
Host smart-58643f80-058b-49ca-afc9-486963e0a058
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701287051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1701287051
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3644130239
Short name T294
Test name
Test status
Simulation time 7557176714 ps
CPU time 64.8 seconds
Started May 30 12:48:51 PM PDT 24
Finished May 30 12:49:57 PM PDT 24
Peak memory 215348 kb
Host smart-a5ab826d-1456-43e1-9ec5-6c57ffd19d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644130239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3644130239
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3573317481
Short name T309
Test name
Test status
Simulation time 1034593367 ps
CPU time 10.87 seconds
Started May 30 12:48:49 PM PDT 24
Finished May 30 12:49:02 PM PDT 24
Peak memory 212596 kb
Host smart-f84c974b-da7b-465a-a865-6427fce98325
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573317481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3573317481
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4189594705
Short name T150
Test name
Test status
Simulation time 12036933884 ps
CPU time 60.55 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 12:49:44 PM PDT 24
Peak memory 215472 kb
Host smart-dbbac40a-8fd7-4e01-bc7c-39046d203c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189594705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4189594705
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.673148900
Short name T83
Test name
Test status
Simulation time 34293297981 ps
CPU time 31.41 seconds
Started May 30 12:48:49 PM PDT 24
Finished May 30 12:49:22 PM PDT 24
Peak memory 214132 kb
Host smart-9707bfaf-e423-489b-b607-9ecd91f63b14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673148900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.673148900
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.131328819
Short name T158
Test name
Test status
Simulation time 1828993448 ps
CPU time 8.51 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:49:03 PM PDT 24
Peak memory 211220 kb
Host smart-e547616b-8344-4015-a434-ea43c87bf832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131328819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.131328819
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1448545840
Short name T286
Test name
Test status
Simulation time 252941404236 ps
CPU time 621.55 seconds
Started May 30 12:48:50 PM PDT 24
Finished May 30 12:59:13 PM PDT 24
Peak memory 240076 kb
Host smart-8cd3610f-0763-4181-8343-f5a380202b8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448545840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1448545840
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.270060704
Short name T37
Test name
Test status
Simulation time 9187693610 ps
CPU time 66.38 seconds
Started May 30 12:48:41 PM PDT 24
Finished May 30 12:49:48 PM PDT 24
Peak memory 215192 kb
Host smart-e34dffc1-60b1-4dc5-99d6-ce55999b493c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270060704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.270060704
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.919301010
Short name T298
Test name
Test status
Simulation time 4307136703 ps
CPU time 35.87 seconds
Started May 30 12:48:51 PM PDT 24
Finished May 30 12:49:28 PM PDT 24
Peak memory 211484 kb
Host smart-4fe1ef8b-62ed-4978-b7f4-1d1d3180700f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919301010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.919301010
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1908370620
Short name T332
Test name
Test status
Simulation time 671509759 ps
CPU time 24.67 seconds
Started May 30 12:48:44 PM PDT 24
Finished May 30 12:49:10 PM PDT 24
Peak memory 216712 kb
Host smart-cfb52740-1f96-47a8-95ba-edd008ebf12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908370620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1908370620
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3467816015
Short name T270
Test name
Test status
Simulation time 9450939808 ps
CPU time 72.29 seconds
Started May 30 12:48:55 PM PDT 24
Finished May 30 12:50:08 PM PDT 24
Peak memory 221148 kb
Host smart-15ff6149-16c1-4c42-88f2-df9803888cc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467816015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3467816015
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.458258125
Short name T316
Test name
Test status
Simulation time 22528805612 ps
CPU time 33.08 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:49:27 PM PDT 24
Peak memory 212276 kb
Host smart-d1b012ca-c71f-444c-bfe3-6fb0bafcf725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458258125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.458258125
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4100492695
Short name T135
Test name
Test status
Simulation time 322475500884 ps
CPU time 850.85 seconds
Started May 30 12:48:41 PM PDT 24
Finished May 30 01:02:52 PM PDT 24
Peak memory 239768 kb
Host smart-fae60fc1-67fd-4a62-8f58-9adc50895304
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100492695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4100492695
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3171319255
Short name T188
Test name
Test status
Simulation time 25931098822 ps
CPU time 56.22 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:49:50 PM PDT 24
Peak memory 215064 kb
Host smart-2dd23cee-3628-4f36-b1a2-3ea83b36cb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171319255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3171319255
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1163415620
Short name T142
Test name
Test status
Simulation time 3608911008 ps
CPU time 20.84 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:49:15 PM PDT 24
Peak memory 212396 kb
Host smart-90ceb5a9-4b9a-4c77-8ec3-8b080e1a2cd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1163415620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1163415620
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1186339967
Short name T169
Test name
Test status
Simulation time 359464392 ps
CPU time 19.27 seconds
Started May 30 12:48:56 PM PDT 24
Finished May 30 12:49:16 PM PDT 24
Peak memory 216864 kb
Host smart-8ed1388f-7e4b-4262-b094-2a66b3a028b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186339967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1186339967
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2218096224
Short name T240
Test name
Test status
Simulation time 35251134563 ps
CPU time 93.33 seconds
Started May 30 12:48:49 PM PDT 24
Finished May 30 12:50:24 PM PDT 24
Peak memory 220792 kb
Host smart-cdddc664-f391-4edb-967b-aab01b93e551
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218096224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2218096224
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3712465868
Short name T151
Test name
Test status
Simulation time 8239107262 ps
CPU time 33.03 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:26 PM PDT 24
Peak memory 212364 kb
Host smart-d53a0637-3f91-4e08-96e0-cd3f14487b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712465868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3712465868
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.353169497
Short name T51
Test name
Test status
Simulation time 212524171386 ps
CPU time 408.2 seconds
Started May 30 12:48:51 PM PDT 24
Finished May 30 12:55:41 PM PDT 24
Peak memory 237932 kb
Host smart-66a8f0df-d792-4dbd-855b-f0d544270751
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353169497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.353169497
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.409243427
Short name T147
Test name
Test status
Simulation time 2048266834 ps
CPU time 32.47 seconds
Started May 30 12:48:49 PM PDT 24
Finished May 30 12:49:23 PM PDT 24
Peak memory 214704 kb
Host smart-ec8385ef-15f7-4756-8d55-c5601fe1e4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409243427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.409243427
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3047393054
Short name T190
Test name
Test status
Simulation time 363162784 ps
CPU time 10.47 seconds
Started May 30 12:48:48 PM PDT 24
Finished May 30 12:48:59 PM PDT 24
Peak memory 211504 kb
Host smart-7101e59a-2da9-4cbf-bf6f-10a8d70d4be5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047393054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3047393054
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3610546541
Short name T212
Test name
Test status
Simulation time 1668651036 ps
CPU time 27.03 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 12:49:10 PM PDT 24
Peak memory 214772 kb
Host smart-e3c5b789-2a7b-4bab-b4fc-07145828c455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610546541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3610546541
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3561121461
Short name T227
Test name
Test status
Simulation time 23651259832 ps
CPU time 94 seconds
Started May 30 12:48:51 PM PDT 24
Finished May 30 12:50:26 PM PDT 24
Peak memory 219396 kb
Host smart-bf7d92b0-70dc-4888-b4f9-fbda3fc72a66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561121461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3561121461
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.770988375
Short name T220
Test name
Test status
Simulation time 3487862109 ps
CPU time 20 seconds
Started May 30 12:48:43 PM PDT 24
Finished May 30 12:49:04 PM PDT 24
Peak memory 211940 kb
Host smart-4008ae54-e2bd-4515-9ccb-eafd6608e1ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770988375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.770988375
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2617731422
Short name T301
Test name
Test status
Simulation time 6129607208 ps
CPU time 265.03 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:53:18 PM PDT 24
Peak memory 229808 kb
Host smart-a028fdaf-a2a2-45e2-9fc0-3568c69e1e1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617731422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2617731422
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.408414637
Short name T21
Test name
Test status
Simulation time 551539565 ps
CPU time 18.92 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:12 PM PDT 24
Peak memory 214712 kb
Host smart-363b10d7-dbb3-41b1-9ca3-ca77dac907f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408414637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.408414637
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3418925810
Short name T218
Test name
Test status
Simulation time 3827760768 ps
CPU time 31.88 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:25 PM PDT 24
Peak memory 211512 kb
Host smart-b835798d-0f4e-4944-9c08-8db9ec8a5e85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3418925810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3418925810
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2025248236
Short name T205
Test name
Test status
Simulation time 6259637102 ps
CPU time 63.31 seconds
Started May 30 12:48:51 PM PDT 24
Finished May 30 12:49:55 PM PDT 24
Peak memory 218468 kb
Host smart-cdab69e6-272a-4fd6-a9a4-3c337d0e957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025248236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2025248236
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1506706920
Short name T82
Test name
Test status
Simulation time 24939114551 ps
CPU time 67.35 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:50:01 PM PDT 24
Peak memory 218068 kb
Host smart-295e55e5-5dc5-464d-8b64-59f2032a5097
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506706920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1506706920
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1137887427
Short name T305
Test name
Test status
Simulation time 13310610640 ps
CPU time 24.48 seconds
Started May 30 12:48:46 PM PDT 24
Finished May 30 12:49:12 PM PDT 24
Peak memory 211428 kb
Host smart-8b2cd6b7-5c54-44a4-98d3-02bb19e88e46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137887427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1137887427
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1817402306
Short name T256
Test name
Test status
Simulation time 49271656149 ps
CPU time 202.75 seconds
Started May 30 12:48:46 PM PDT 24
Finished May 30 12:52:10 PM PDT 24
Peak memory 215912 kb
Host smart-8a032542-b79e-4a66-b470-5ef14f560336
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817402306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1817402306
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2574857700
Short name T43
Test name
Test status
Simulation time 17214442992 ps
CPU time 61.84 seconds
Started May 30 12:48:48 PM PDT 24
Finished May 30 12:49:50 PM PDT 24
Peak memory 215068 kb
Host smart-f8a1bb92-3fd7-43f5-ad6a-1db889941cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574857700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2574857700
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4005271293
Short name T182
Test name
Test status
Simulation time 26425752997 ps
CPU time 32.82 seconds
Started May 30 12:48:49 PM PDT 24
Finished May 30 12:49:22 PM PDT 24
Peak memory 211808 kb
Host smart-b4afba5c-d0cd-413c-a71f-6a817cac0f9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005271293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4005271293
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3173979054
Short name T254
Test name
Test status
Simulation time 17072043275 ps
CPU time 83.15 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:50:17 PM PDT 24
Peak memory 216908 kb
Host smart-71029365-5e6c-4528-9799-4cb098756532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173979054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3173979054
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3541008504
Short name T299
Test name
Test status
Simulation time 10908480311 ps
CPU time 157.05 seconds
Started May 30 12:48:46 PM PDT 24
Finished May 30 12:51:24 PM PDT 24
Peak memory 219392 kb
Host smart-49004186-59dc-4c03-9e38-0294263754ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541008504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3541008504
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4193415670
Short name T71
Test name
Test status
Simulation time 2177966212 ps
CPU time 10.77 seconds
Started May 30 12:48:28 PM PDT 24
Finished May 30 12:48:41 PM PDT 24
Peak memory 211244 kb
Host smart-191bec81-970f-45e5-88cb-39d5727b1ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193415670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4193415670
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2817150500
Short name T347
Test name
Test status
Simulation time 54706853711 ps
CPU time 494.41 seconds
Started May 30 12:48:30 PM PDT 24
Finished May 30 12:56:46 PM PDT 24
Peak memory 235892 kb
Host smart-3467d41f-c93d-431a-bac1-593a93b6cbd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817150500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2817150500
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.874657873
Short name T235
Test name
Test status
Simulation time 7681419356 ps
CPU time 42.91 seconds
Started May 30 12:48:30 PM PDT 24
Finished May 30 12:49:15 PM PDT 24
Peak memory 215196 kb
Host smart-77e56090-9252-4b45-9659-5c81145911a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874657873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.874657873
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.585560081
Short name T259
Test name
Test status
Simulation time 2672699743 ps
CPU time 14.79 seconds
Started May 30 12:48:30 PM PDT 24
Finished May 30 12:48:46 PM PDT 24
Peak memory 211540 kb
Host smart-2a3b810d-5169-4940-b5c6-07a8a28b3e74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585560081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.585560081
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2330595445
Short name T35
Test name
Test status
Simulation time 923658947 ps
CPU time 117.94 seconds
Started May 30 12:48:29 PM PDT 24
Finished May 30 12:50:28 PM PDT 24
Peak memory 238556 kb
Host smart-f5c1ae65-9529-4eca-a56d-e2a7205853d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330595445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2330595445
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2008153213
Short name T278
Test name
Test status
Simulation time 30530599615 ps
CPU time 75.46 seconds
Started May 30 12:48:26 PM PDT 24
Finished May 30 12:49:42 PM PDT 24
Peak memory 217180 kb
Host smart-3552da3e-9409-45c3-a164-c4d0d37c4709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008153213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2008153213
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3224794749
Short name T176
Test name
Test status
Simulation time 1755952156 ps
CPU time 64.11 seconds
Started May 30 12:48:28 PM PDT 24
Finished May 30 12:49:34 PM PDT 24
Peak memory 219168 kb
Host smart-9bdae23a-c4d5-48b3-bec2-96ec6f060cbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224794749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3224794749
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1423037448
Short name T139
Test name
Test status
Simulation time 1500992675 ps
CPU time 8.13 seconds
Started May 30 12:48:41 PM PDT 24
Finished May 30 12:48:50 PM PDT 24
Peak memory 211052 kb
Host smart-daf631a8-f6ca-4ee3-90f5-cc1de3c8f333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423037448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1423037448
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.399356396
Short name T226
Test name
Test status
Simulation time 540975322345 ps
CPU time 1018.45 seconds
Started May 30 12:48:57 PM PDT 24
Finished May 30 01:05:56 PM PDT 24
Peak memory 239860 kb
Host smart-6dd2aeba-8bf3-4b23-9d07-ad804b19baac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399356396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.399356396
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.923911678
Short name T234
Test name
Test status
Simulation time 27416319580 ps
CPU time 61.6 seconds
Started May 30 12:49:03 PM PDT 24
Finished May 30 12:50:06 PM PDT 24
Peak memory 215088 kb
Host smart-2d2bf0ee-f4b1-4c57-a764-dad8c6c8c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923911678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.923911678
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1946153742
Short name T296
Test name
Test status
Simulation time 4727371687 ps
CPU time 24.4 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:49:19 PM PDT 24
Peak memory 211552 kb
Host smart-88391760-d5f5-4475-8130-8a7a6090e901
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1946153742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1946153742
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2792463491
Short name T357
Test name
Test status
Simulation time 836342391 ps
CPU time 20.26 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:49:14 PM PDT 24
Peak memory 216700 kb
Host smart-c2a9c82f-75db-4b61-bfa1-ac23e0d3fa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792463491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2792463491
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1829886064
Short name T17
Test name
Test status
Simulation time 15591864764 ps
CPU time 180.36 seconds
Started May 30 12:48:46 PM PDT 24
Finished May 30 12:51:47 PM PDT 24
Peak memory 220980 kb
Host smart-60d3e068-b30f-42c2-89da-e0c36b3ab86e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829886064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1829886064
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3549658306
Short name T210
Test name
Test status
Simulation time 545482461442 ps
CPU time 778.35 seconds
Started May 30 12:48:48 PM PDT 24
Finished May 30 01:01:47 PM PDT 24
Peak memory 240160 kb
Host smart-50a1566b-1298-4bb7-8259-454c1930200c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549658306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3549658306
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3662254383
Short name T179
Test name
Test status
Simulation time 1835076780 ps
CPU time 19.41 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:12 PM PDT 24
Peak memory 214748 kb
Host smart-a05ac535-453f-4358-87bf-2ce906099662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662254383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3662254383
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3192853414
Short name T115
Test name
Test status
Simulation time 16718886330 ps
CPU time 36.04 seconds
Started May 30 12:48:49 PM PDT 24
Finished May 30 12:49:26 PM PDT 24
Peak memory 211420 kb
Host smart-f510172e-f2a2-4fbd-81b2-264b86399251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3192853414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3192853414
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3607550411
Short name T322
Test name
Test status
Simulation time 11386447749 ps
CPU time 36.96 seconds
Started May 30 12:48:48 PM PDT 24
Finished May 30 12:49:26 PM PDT 24
Peak memory 215528 kb
Host smart-c389d564-09ed-4a7e-9e7c-696b35046798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607550411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3607550411
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1541637613
Short name T170
Test name
Test status
Simulation time 6083643995 ps
CPU time 46.64 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:49:41 PM PDT 24
Peak memory 218192 kb
Host smart-306e69f4-443b-42cf-be00-92ebc1336928
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541637613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1541637613
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2706550032
Short name T334
Test name
Test status
Simulation time 25688938624 ps
CPU time 27.37 seconds
Started May 30 12:48:51 PM PDT 24
Finished May 30 12:49:19 PM PDT 24
Peak memory 212152 kb
Host smart-eac24379-a57d-4154-8db1-9c7d84d5e0c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706550032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2706550032
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.940842869
Short name T233
Test name
Test status
Simulation time 24859047330 ps
CPU time 57.09 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:49:51 PM PDT 24
Peak memory 215068 kb
Host smart-df4a009e-e08c-4d0b-ac0d-72be64b1e01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940842869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.940842869
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2822329364
Short name T194
Test name
Test status
Simulation time 588851233 ps
CPU time 10.7 seconds
Started May 30 12:48:50 PM PDT 24
Finished May 30 12:49:02 PM PDT 24
Peak memory 212236 kb
Host smart-8731a7be-39d5-4e5b-92a8-743b303a0a05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822329364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2822329364
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3921607532
Short name T196
Test name
Test status
Simulation time 21285135598 ps
CPU time 55.32 seconds
Started May 30 12:48:45 PM PDT 24
Finished May 30 12:49:41 PM PDT 24
Peak memory 218148 kb
Host smart-b8279d94-a97e-432e-b996-41f8b80b11b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921607532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3921607532
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2498216592
Short name T144
Test name
Test status
Simulation time 348991949 ps
CPU time 13.67 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:49:08 PM PDT 24
Peak memory 211104 kb
Host smart-82ba5dbd-7d03-4305-afaf-5427dbc65b9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498216592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2498216592
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.4084407939
Short name T1
Test name
Test status
Simulation time 12562606303 ps
CPU time 20.25 seconds
Started May 30 12:49:11 PM PDT 24
Finished May 30 12:49:32 PM PDT 24
Peak memory 211252 kb
Host smart-646b5cd2-b55a-422a-9cd1-5e4fbd024afb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084407939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.4084407939
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4058144616
Short name T244
Test name
Test status
Simulation time 18980790054 ps
CPU time 320.22 seconds
Started May 30 12:48:51 PM PDT 24
Finished May 30 12:54:13 PM PDT 24
Peak memory 217896 kb
Host smart-182c8131-211b-4532-87cb-5b28606ebc20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058144616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4058144616
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2702689864
Short name T327
Test name
Test status
Simulation time 22383838013 ps
CPU time 51.08 seconds
Started May 30 12:48:49 PM PDT 24
Finished May 30 12:49:42 PM PDT 24
Peak memory 214144 kb
Host smart-8a568bfd-a59b-4994-88bf-dfbc7a7d4246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702689864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2702689864
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4122940596
Short name T14
Test name
Test status
Simulation time 3733651689 ps
CPU time 20.9 seconds
Started May 30 12:48:49 PM PDT 24
Finished May 30 12:49:12 PM PDT 24
Peak memory 211488 kb
Host smart-d020aa21-c2d7-4f95-b961-54c8a23da095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122940596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4122940596
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2065128751
Short name T61
Test name
Test status
Simulation time 7786137685 ps
CPU time 63.56 seconds
Started May 30 12:48:47 PM PDT 24
Finished May 30 12:49:52 PM PDT 24
Peak memory 217460 kb
Host smart-38ef1ba6-34bc-4e1e-8e90-e24ddc904ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065128751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2065128751
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3694516958
Short name T356
Test name
Test status
Simulation time 12869952972 ps
CPU time 148.45 seconds
Started May 30 12:49:07 PM PDT 24
Finished May 30 12:51:37 PM PDT 24
Peak memory 227768 kb
Host smart-6943211a-73e2-4837-92a0-7f8d0c725faf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694516958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3694516958
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1325717378
Short name T214
Test name
Test status
Simulation time 3747615626 ps
CPU time 30.37 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:24 PM PDT 24
Peak memory 211936 kb
Host smart-eb9e926d-6d3e-4457-970e-59cd2808d88d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325717378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1325717378
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.951642324
Short name T232
Test name
Test status
Simulation time 4755917467 ps
CPU time 48.94 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:42 PM PDT 24
Peak memory 213088 kb
Host smart-dec69878-a03c-4347-821e-45db0a4bffbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951642324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.951642324
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3652844635
Short name T189
Test name
Test status
Simulation time 27039104076 ps
CPU time 33.18 seconds
Started May 30 12:49:05 PM PDT 24
Finished May 30 12:49:39 PM PDT 24
Peak memory 212968 kb
Host smart-1c18118a-c7f5-47d1-b2f8-38349ff5fec3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652844635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3652844635
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3787216163
Short name T184
Test name
Test status
Simulation time 802915215 ps
CPU time 20 seconds
Started May 30 12:49:07 PM PDT 24
Finished May 30 12:49:28 PM PDT 24
Peak memory 216608 kb
Host smart-c35fda5f-9ca6-46ae-91d5-88426461c091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787216163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3787216163
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.26044308
Short name T291
Test name
Test status
Simulation time 12273216108 ps
CPU time 30.22 seconds
Started May 30 12:49:08 PM PDT 24
Finished May 30 12:49:39 PM PDT 24
Peak memory 212712 kb
Host smart-7faf1328-383d-4b42-b978-b1ff196662e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26044308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 24.rom_ctrl_stress_all.26044308
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1571646061
Short name T54
Test name
Test status
Simulation time 52582360536 ps
CPU time 6955.98 seconds
Started May 30 12:48:57 PM PDT 24
Finished May 30 02:44:54 PM PDT 24
Peak memory 234468 kb
Host smart-c9f3ea76-348b-46ff-85d3-e9b8ba31ad60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571646061 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1571646061
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.606953368
Short name T197
Test name
Test status
Simulation time 1720252142 ps
CPU time 10.93 seconds
Started May 30 12:48:50 PM PDT 24
Finished May 30 12:49:02 PM PDT 24
Peak memory 211244 kb
Host smart-3d8a9347-8ae9-422f-936b-5a4862e5aead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606953368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.606953368
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1775903822
Short name T32
Test name
Test status
Simulation time 336587828852 ps
CPU time 943.68 seconds
Started May 30 12:48:56 PM PDT 24
Finished May 30 01:04:41 PM PDT 24
Peak memory 217252 kb
Host smart-1c985121-3fee-45ff-95f1-6702c728f200
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775903822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1775903822
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2901217592
Short name T27
Test name
Test status
Simulation time 8373193440 ps
CPU time 64.65 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:58 PM PDT 24
Peak memory 214604 kb
Host smart-2bc27358-1399-447b-9dfe-be5017044370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901217592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2901217592
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3457294368
Short name T102
Test name
Test status
Simulation time 2018710959 ps
CPU time 14.15 seconds
Started May 30 12:48:59 PM PDT 24
Finished May 30 12:49:14 PM PDT 24
Peak memory 211484 kb
Host smart-4e467519-608e-4bdf-af16-4af52efa1575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457294368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3457294368
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2268292076
Short name T5
Test name
Test status
Simulation time 6205102118 ps
CPU time 61.76 seconds
Started May 30 12:48:51 PM PDT 24
Finished May 30 12:49:53 PM PDT 24
Peak memory 217564 kb
Host smart-6d8500c8-3983-4d1b-b997-b8a0c055cbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268292076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2268292076
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2004354666
Short name T325
Test name
Test status
Simulation time 2723503439 ps
CPU time 41.12 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 12:49:52 PM PDT 24
Peak memory 212884 kb
Host smart-849c3553-7637-4683-a8f6-75046399a999
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004354666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2004354666
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2117119383
Short name T242
Test name
Test status
Simulation time 5105950544 ps
CPU time 17.88 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:49:21 PM PDT 24
Peak memory 212180 kb
Host smart-6589b218-b078-4cd6-a01a-5c73926d1f82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117119383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2117119383
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.710858308
Short name T333
Test name
Test status
Simulation time 59928872490 ps
CPU time 303.74 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:54:07 PM PDT 24
Peak memory 240624 kb
Host smart-7114090f-09ab-4a52-9485-e8ef0b216d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710858308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.710858308
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1137862555
Short name T181
Test name
Test status
Simulation time 117111959791 ps
CPU time 73.3 seconds
Started May 30 12:48:57 PM PDT 24
Finished May 30 12:50:11 PM PDT 24
Peak memory 214024 kb
Host smart-2c024b0c-f5a1-4cf1-b727-26c1d130ea0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137862555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1137862555
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.312166942
Short name T306
Test name
Test status
Simulation time 6192563943 ps
CPU time 27.53 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:49:38 PM PDT 24
Peak memory 211832 kb
Host smart-e0c78e61-0b6f-481e-97fd-244bc2206bca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312166942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.312166942
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2130028489
Short name T304
Test name
Test status
Simulation time 8255607488 ps
CPU time 69.47 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:50:19 PM PDT 24
Peak memory 218424 kb
Host smart-373e97cf-fe33-4897-8bde-b36b7f8eb5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130028489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2130028489
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3210081476
Short name T241
Test name
Test status
Simulation time 774313502 ps
CPU time 21.02 seconds
Started May 30 12:48:55 PM PDT 24
Finished May 30 12:49:16 PM PDT 24
Peak memory 211208 kb
Host smart-d1b827f3-046c-48fa-89a1-ef0391b02b48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210081476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3210081476
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1180464901
Short name T56
Test name
Test status
Simulation time 80468684853 ps
CPU time 3184.76 seconds
Started May 30 12:48:50 PM PDT 24
Finished May 30 01:41:56 PM PDT 24
Peak memory 252308 kb
Host smart-3307fec8-9947-4c56-adc8-efa8f7c391d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180464901 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1180464901
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1110132510
Short name T263
Test name
Test status
Simulation time 2154017518 ps
CPU time 20.65 seconds
Started May 30 12:48:59 PM PDT 24
Finished May 30 12:49:20 PM PDT 24
Peak memory 211896 kb
Host smart-5bf42016-f0fe-4794-9d53-3dceaabe2527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110132510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1110132510
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1768454201
Short name T23
Test name
Test status
Simulation time 32894095434 ps
CPU time 427.16 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:56:17 PM PDT 24
Peak memory 240528 kb
Host smart-599f4355-9f87-46cc-870e-2afd779974bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768454201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1768454201
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3869580415
Short name T199
Test name
Test status
Simulation time 6911594774 ps
CPU time 36.26 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:29 PM PDT 24
Peak memory 215128 kb
Host smart-9096df5a-cab9-4977-be71-8db5b1a1b533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869580415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3869580415
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.251806803
Short name T222
Test name
Test status
Simulation time 12470952834 ps
CPU time 30.84 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 12:49:42 PM PDT 24
Peak memory 211964 kb
Host smart-181534cf-78c9-4f68-a5c3-703ec40fee30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251806803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.251806803
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.675761763
Short name T149
Test name
Test status
Simulation time 9067692479 ps
CPU time 46.18 seconds
Started May 30 12:48:56 PM PDT 24
Finished May 30 12:49:43 PM PDT 24
Peak memory 218616 kb
Host smart-8c222436-2b3f-42c6-b233-2889b9a73913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675761763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.675761763
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.625183744
Short name T187
Test name
Test status
Simulation time 33459149674 ps
CPU time 340.14 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:54:50 PM PDT 24
Peak memory 223028 kb
Host smart-16075d63-c579-4f0b-9470-4fb6838b4a24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625183744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.625183744
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.989599186
Short name T63
Test name
Test status
Simulation time 169169035 ps
CPU time 8.48 seconds
Started May 30 12:48:54 PM PDT 24
Finished May 30 12:49:03 PM PDT 24
Peak memory 211204 kb
Host smart-c36d5faf-dcc4-4dac-a05c-ecca1708f1ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989599186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.989599186
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4220015979
Short name T307
Test name
Test status
Simulation time 55606188779 ps
CPU time 583.69 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:58:47 PM PDT 24
Peak memory 239872 kb
Host smart-c023fdbe-cf86-4a38-97f7-1d68e7fb2b60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220015979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4220015979
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4256688211
Short name T105
Test name
Test status
Simulation time 4993673436 ps
CPU time 48.45 seconds
Started May 30 12:49:01 PM PDT 24
Finished May 30 12:49:50 PM PDT 24
Peak memory 214256 kb
Host smart-3b799706-d8fb-4340-ab35-6919e5f3418f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256688211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.4256688211
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1258274610
Short name T344
Test name
Test status
Simulation time 7149961040 ps
CPU time 30.62 seconds
Started May 30 12:49:01 PM PDT 24
Finished May 30 12:49:33 PM PDT 24
Peak memory 211524 kb
Host smart-7558e83a-ea26-4639-85a1-bf5a44062048
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258274610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1258274610
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3023646604
Short name T315
Test name
Test status
Simulation time 1414601246 ps
CPU time 19.26 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:49:22 PM PDT 24
Peak memory 216484 kb
Host smart-482892b2-7ba0-4026-b6f4-2d4de0bd9c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023646604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3023646604
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.642371
Short name T351
Test name
Test status
Simulation time 6117309813 ps
CPU time 61.81 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:54 PM PDT 24
Peak memory 219272 kb
Host smart-46f17dbc-7263-4cca-b34e-08a41e41e139
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.rom_ctrl_stress_all.642371
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4243867060
Short name T3
Test name
Test status
Simulation time 35053332213 ps
CPU time 30.44 seconds
Started May 30 12:48:56 PM PDT 24
Finished May 30 12:49:27 PM PDT 24
Peak memory 212184 kb
Host smart-b33483db-c11f-41ba-a3ab-e2b99285ee63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243867060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4243867060
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1915400132
Short name T266
Test name
Test status
Simulation time 15611987723 ps
CPU time 291.36 seconds
Started May 30 12:48:55 PM PDT 24
Finished May 30 12:53:47 PM PDT 24
Peak memory 239640 kb
Host smart-eb34c986-92a5-4d21-9de0-b0814724f164
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915400132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1915400132
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1734167125
Short name T239
Test name
Test status
Simulation time 30750930281 ps
CPU time 65.41 seconds
Started May 30 12:49:07 PM PDT 24
Finished May 30 12:50:13 PM PDT 24
Peak memory 214964 kb
Host smart-a3f8c4d3-e5d6-4459-b4ec-11855e79d4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734167125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1734167125
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3619563203
Short name T318
Test name
Test status
Simulation time 5506185224 ps
CPU time 26.77 seconds
Started May 30 12:49:01 PM PDT 24
Finished May 30 12:49:29 PM PDT 24
Peak memory 212716 kb
Host smart-fbf3aea7-9f78-4cd0-9ea9-45d79056bdec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619563203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3619563203
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1249646420
Short name T162
Test name
Test status
Simulation time 364592914 ps
CPU time 19.81 seconds
Started May 30 12:48:55 PM PDT 24
Finished May 30 12:49:15 PM PDT 24
Peak memory 213712 kb
Host smart-b5fd5cc5-cce1-4f9c-b497-033e88e01864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249646420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1249646420
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3547287282
Short name T174
Test name
Test status
Simulation time 833605675 ps
CPU time 15.05 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 12:49:26 PM PDT 24
Peak memory 213528 kb
Host smart-06b12af1-b0b2-471c-bf5b-3b60cc0bf089
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547287282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3547287282
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1623965522
Short name T70
Test name
Test status
Simulation time 9216937204 ps
CPU time 22.67 seconds
Started May 30 12:48:27 PM PDT 24
Finished May 30 12:48:51 PM PDT 24
Peak memory 211412 kb
Host smart-456b3a58-5bdc-4bf4-9756-2faa30d7f950
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623965522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1623965522
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.293406621
Short name T50
Test name
Test status
Simulation time 227162586105 ps
CPU time 603.84 seconds
Started May 30 12:48:31 PM PDT 24
Finished May 30 12:58:37 PM PDT 24
Peak memory 227748 kb
Host smart-e8b6a9e4-9262-4cd9-9897-60e293261f89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293406621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.293406621
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.485783182
Short name T161
Test name
Test status
Simulation time 3418581624 ps
CPU time 40.09 seconds
Started May 30 12:48:27 PM PDT 24
Finished May 30 12:49:09 PM PDT 24
Peak memory 214748 kb
Host smart-a92108ec-16ef-4414-97f8-fb2e908a8af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485783182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.485783182
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3865369771
Short name T268
Test name
Test status
Simulation time 6929051238 ps
CPU time 21.2 seconds
Started May 30 12:48:32 PM PDT 24
Finished May 30 12:48:54 PM PDT 24
Peak memory 211744 kb
Host smart-efedce51-b995-4898-9c64-226080110c60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865369771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3865369771
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.735376546
Short name T300
Test name
Test status
Simulation time 27443857811 ps
CPU time 56.33 seconds
Started May 30 12:48:29 PM PDT 24
Finished May 30 12:49:27 PM PDT 24
Peak memory 217624 kb
Host smart-9689d957-2ef3-4704-8a00-5e6c50ed8009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735376546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.735376546
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.521754101
Short name T225
Test name
Test status
Simulation time 14802031293 ps
CPU time 149.96 seconds
Started May 30 12:48:28 PM PDT 24
Finished May 30 12:50:59 PM PDT 24
Peak memory 227600 kb
Host smart-bd47a086-8bee-4b19-894b-21fc85b93369
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521754101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.521754101
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.646331913
Short name T53
Test name
Test status
Simulation time 84561730585 ps
CPU time 804.56 seconds
Started May 30 12:48:29 PM PDT 24
Finished May 30 01:01:55 PM PDT 24
Peak memory 235912 kb
Host smart-893ccd45-66cf-4801-afe0-182afb5a9123
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646331913 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.646331913
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1955096660
Short name T202
Test name
Test status
Simulation time 17502028137 ps
CPU time 33.39 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:49:36 PM PDT 24
Peak memory 211388 kb
Host smart-3d750d20-dc15-4cc4-937a-1c81cc1ae562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955096660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1955096660
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1167006509
Short name T203
Test name
Test status
Simulation time 4986829882 ps
CPU time 361.24 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 12:55:13 PM PDT 24
Peak memory 219600 kb
Host smart-7ea16141-3ddb-4619-9956-fda1002edb79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167006509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1167006509
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1712522678
Short name T4
Test name
Test status
Simulation time 1651845321 ps
CPU time 19.15 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:49:29 PM PDT 24
Peak memory 214764 kb
Host smart-17315bdf-d1ed-41cd-8716-9503a91e6ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712522678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1712522678
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.221212655
Short name T101
Test name
Test status
Simulation time 14293403800 ps
CPU time 30.44 seconds
Started May 30 12:48:57 PM PDT 24
Finished May 30 12:49:28 PM PDT 24
Peak memory 211432 kb
Host smart-22a2d8c7-9860-47fe-8d1e-82d65b1e2592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221212655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.221212655
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1628760756
Short name T141
Test name
Test status
Simulation time 8777027282 ps
CPU time 28.27 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:49:38 PM PDT 24
Peak memory 218012 kb
Host smart-f29214ee-409e-47da-aff7-38f5201bb489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628760756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1628760756
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2223546442
Short name T163
Test name
Test status
Simulation time 2417029192 ps
CPU time 29.2 seconds
Started May 30 12:48:57 PM PDT 24
Finished May 30 12:49:27 PM PDT 24
Peak memory 213560 kb
Host smart-d3f120a6-7d30-46e4-85aa-6736e4c90493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223546442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2223546442
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2556625047
Short name T320
Test name
Test status
Simulation time 176173269 ps
CPU time 8.39 seconds
Started May 30 12:49:08 PM PDT 24
Finished May 30 12:49:17 PM PDT 24
Peak memory 211220 kb
Host smart-0f2d6377-8dd3-4b5a-adc5-614c46576660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556625047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2556625047
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3889415566
Short name T191
Test name
Test status
Simulation time 64753664544 ps
CPU time 799.65 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 01:02:31 PM PDT 24
Peak memory 240860 kb
Host smart-bc5504a4-f3bb-4a63-b722-ee4f9e7fbb03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889415566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3889415566
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.830267001
Short name T177
Test name
Test status
Simulation time 688565706 ps
CPU time 19.11 seconds
Started May 30 12:48:59 PM PDT 24
Finished May 30 12:49:19 PM PDT 24
Peak memory 214724 kb
Host smart-e755b817-c7ae-4462-b205-2b9b3a7868f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830267001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.830267001
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4074198929
Short name T171
Test name
Test status
Simulation time 9177699713 ps
CPU time 24.24 seconds
Started May 30 12:48:58 PM PDT 24
Finished May 30 12:49:23 PM PDT 24
Peak memory 211408 kb
Host smart-e7d56ea5-6f2f-4eb3-b341-ed63522c5a46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074198929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4074198929
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.4015481778
Short name T204
Test name
Test status
Simulation time 5080077394 ps
CPU time 56.78 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:50:06 PM PDT 24
Peak memory 215140 kb
Host smart-bed01508-7054-40b1-8a4e-5b900e6cbc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015481778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.4015481778
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.7308452
Short name T313
Test name
Test status
Simulation time 2952706474 ps
CPU time 49.6 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:49:53 PM PDT 24
Peak memory 219292 kb
Host smart-9c549ceb-9f2a-48b8-bd56-03ace86b7457
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7308452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.rom_ctrl_stress_all.7308452
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4284458107
Short name T339
Test name
Test status
Simulation time 36957648031 ps
CPU time 27.29 seconds
Started May 30 12:49:08 PM PDT 24
Finished May 30 12:49:36 PM PDT 24
Peak memory 211340 kb
Host smart-eb971a8f-90fd-454b-9796-6636e14b8ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284458107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4284458107
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2323690693
Short name T247
Test name
Test status
Simulation time 330819002768 ps
CPU time 619.06 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:59:22 PM PDT 24
Peak memory 219080 kb
Host smart-7d1a2860-28fd-44a3-8cb0-1c6b920bc776
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323690693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2323690693
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3044643201
Short name T193
Test name
Test status
Simulation time 23902402530 ps
CPU time 54.95 seconds
Started May 30 12:49:05 PM PDT 24
Finished May 30 12:50:01 PM PDT 24
Peak memory 215156 kb
Host smart-741f2a47-6fcf-4469-a0df-8bec92d224b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044643201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3044643201
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.436863398
Short name T116
Test name
Test status
Simulation time 4442475125 ps
CPU time 24.46 seconds
Started May 30 12:49:05 PM PDT 24
Finished May 30 12:49:30 PM PDT 24
Peak memory 211480 kb
Host smart-d6bed21a-f8d3-43d2-88a6-f3ab38b52d32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=436863398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.436863398
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1857603929
Short name T243
Test name
Test status
Simulation time 19742639562 ps
CPU time 38.63 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:49:42 PM PDT 24
Peak memory 218092 kb
Host smart-61cac11d-6e2c-4283-ab74-6eadf8330c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857603929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1857603929
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.232033847
Short name T136
Test name
Test status
Simulation time 10806672011 ps
CPU time 95.09 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:50:29 PM PDT 24
Peak memory 219284 kb
Host smart-c969a1ac-8e29-4187-a2a8-dfbddd417406
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232033847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.232033847
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3533070241
Short name T103
Test name
Test status
Simulation time 5715799429 ps
CPU time 16.97 seconds
Started May 30 12:49:01 PM PDT 24
Finished May 30 12:49:19 PM PDT 24
Peak memory 211312 kb
Host smart-8b4c7b74-3e1e-4e3c-9022-dcb7790ce7bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533070241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3533070241
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2758632038
Short name T308
Test name
Test status
Simulation time 31357375705 ps
CPU time 201.03 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 12:52:32 PM PDT 24
Peak memory 236788 kb
Host smart-f977f6a4-b738-4147-89bc-b3efb98aa9f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758632038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2758632038
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3010092454
Short name T273
Test name
Test status
Simulation time 14110422590 ps
CPU time 30.81 seconds
Started May 30 12:49:06 PM PDT 24
Finished May 30 12:49:37 PM PDT 24
Peak memory 211696 kb
Host smart-f18ef73d-180f-43a1-a550-5b0520738c72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010092454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3010092454
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2996875507
Short name T41
Test name
Test status
Simulation time 2139050701 ps
CPU time 20.7 seconds
Started May 30 12:48:59 PM PDT 24
Finished May 30 12:49:21 PM PDT 24
Peak memory 216884 kb
Host smart-e61e705e-5d01-428d-b226-b06dcb4b312b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996875507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2996875507
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3920029291
Short name T60
Test name
Test status
Simulation time 717773322 ps
CPU time 41.86 seconds
Started May 30 12:49:08 PM PDT 24
Finished May 30 12:49:51 PM PDT 24
Peak memory 219256 kb
Host smart-63496efc-38eb-40c4-b143-381ab8667f44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920029291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3920029291
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1697853936
Short name T245
Test name
Test status
Simulation time 338767821 ps
CPU time 8.35 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:49:12 PM PDT 24
Peak memory 211292 kb
Host smart-9abf3639-27f0-4fd4-8a04-7a6febfd9871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697853936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1697853936
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3155044219
Short name T230
Test name
Test status
Simulation time 840605868856 ps
CPU time 607.61 seconds
Started May 30 12:48:59 PM PDT 24
Finished May 30 12:59:08 PM PDT 24
Peak memory 229672 kb
Host smart-421e5b4d-45ca-4512-8779-544f67828ad6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155044219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3155044219
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3403801402
Short name T336
Test name
Test status
Simulation time 5120475565 ps
CPU time 42.79 seconds
Started May 30 12:48:59 PM PDT 24
Finished May 30 12:49:43 PM PDT 24
Peak memory 215792 kb
Host smart-33f7d092-adb3-4acc-aa64-29c93a6e6df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403801402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3403801402
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.234508515
Short name T44
Test name
Test status
Simulation time 7249864163 ps
CPU time 21.49 seconds
Started May 30 12:48:54 PM PDT 24
Finished May 30 12:49:17 PM PDT 24
Peak memory 212896 kb
Host smart-96d2728b-925d-43f6-bab4-6067652c1e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=234508515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.234508515
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2304973698
Short name T303
Test name
Test status
Simulation time 2775772263 ps
CPU time 25.57 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:49:36 PM PDT 24
Peak memory 217932 kb
Host smart-f785a893-61b6-4295-90be-57834bcd351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304973698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2304973698
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2044083225
Short name T16
Test name
Test status
Simulation time 7910503859 ps
CPU time 70.93 seconds
Started May 30 12:49:01 PM PDT 24
Finished May 30 12:50:13 PM PDT 24
Peak memory 218256 kb
Host smart-e6fa7e6f-6e97-475a-b599-5cf6b44c2007
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044083225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2044083225
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2949526937
Short name T293
Test name
Test status
Simulation time 1595182989 ps
CPU time 17.66 seconds
Started May 30 12:49:08 PM PDT 24
Finished May 30 12:49:26 PM PDT 24
Peak memory 211724 kb
Host smart-b2650cde-51a7-4804-98ed-7211259559da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949526937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2949526937
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.735350209
Short name T24
Test name
Test status
Simulation time 622995170891 ps
CPU time 739.03 seconds
Started May 30 12:49:03 PM PDT 24
Finished May 30 01:01:23 PM PDT 24
Peak memory 217664 kb
Host smart-5111e72c-ae51-4174-b0bb-a4f1e1e5f4d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735350209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.735350209
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3424057863
Short name T20
Test name
Test status
Simulation time 28812238896 ps
CPU time 48.96 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:49:59 PM PDT 24
Peak memory 215116 kb
Host smart-c8486766-11da-42d0-85d5-948b67fbbc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424057863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3424057863
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1814164737
Short name T154
Test name
Test status
Simulation time 8906597739 ps
CPU time 34.47 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:49:38 PM PDT 24
Peak memory 212608 kb
Host smart-0dd761f2-8701-402a-8345-b4b2bb291941
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1814164737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1814164737
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2300195260
Short name T328
Test name
Test status
Simulation time 9951623697 ps
CPU time 32.8 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:49:43 PM PDT 24
Peak memory 217780 kb
Host smart-54ae5037-ba53-45b1-84aa-2a9424e12d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300195260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2300195260
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1610964192
Short name T11
Test name
Test status
Simulation time 1066722378 ps
CPU time 32.64 seconds
Started May 30 12:49:05 PM PDT 24
Finished May 30 12:49:38 PM PDT 24
Peak memory 219176 kb
Host smart-a4c40280-15c4-49e4-a0bd-fd7791e40197
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610964192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1610964192
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.178204702
Short name T269
Test name
Test status
Simulation time 14220162596 ps
CPU time 21.38 seconds
Started May 30 12:48:57 PM PDT 24
Finished May 30 12:49:19 PM PDT 24
Peak memory 211348 kb
Host smart-4cef6af0-b585-4340-a357-3b2c7159e0c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178204702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.178204702
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1278576948
Short name T281
Test name
Test status
Simulation time 75720210430 ps
CPU time 786.85 seconds
Started May 30 12:48:58 PM PDT 24
Finished May 30 01:02:05 PM PDT 24
Peak memory 224700 kb
Host smart-f9e110df-b1db-4b4f-b050-f856f182beb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278576948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1278576948
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1297823411
Short name T137
Test name
Test status
Simulation time 22184160016 ps
CPU time 54.53 seconds
Started May 30 12:48:59 PM PDT 24
Finished May 30 12:49:54 PM PDT 24
Peak memory 215000 kb
Host smart-ef1fbb83-fb8b-4775-9dfe-99d634911101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297823411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1297823411
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2900163956
Short name T346
Test name
Test status
Simulation time 1523428063 ps
CPU time 15.22 seconds
Started May 30 12:48:58 PM PDT 24
Finished May 30 12:49:14 PM PDT 24
Peak memory 212208 kb
Host smart-9dce1d84-a9f3-4862-bdf7-87efc785c114
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2900163956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2900163956
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2084598161
Short name T258
Test name
Test status
Simulation time 4597186976 ps
CPU time 45.3 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:49:56 PM PDT 24
Peak memory 218100 kb
Host smart-376a70bf-5b67-473b-a375-1ab2e956886d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084598161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2084598161
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2612262953
Short name T215
Test name
Test status
Simulation time 57397953564 ps
CPU time 235.9 seconds
Started May 30 12:49:08 PM PDT 24
Finished May 30 12:53:05 PM PDT 24
Peak memory 220596 kb
Host smart-df255b7b-9a68-41d1-92f7-5f84de729688
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612262953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2612262953
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2619930830
Short name T100
Test name
Test status
Simulation time 24675163420 ps
CPU time 24.52 seconds
Started May 30 12:48:54 PM PDT 24
Finished May 30 12:49:19 PM PDT 24
Peak memory 211396 kb
Host smart-042067a9-2e7e-47fa-9664-dc69ccacf2e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619930830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2619930830
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.342819191
Short name T206
Test name
Test status
Simulation time 6492408847 ps
CPU time 199.45 seconds
Started May 30 12:49:07 PM PDT 24
Finished May 30 12:52:27 PM PDT 24
Peak memory 226204 kb
Host smart-05770b9d-70ad-487b-ab2f-a82e0326b329
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342819191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.342819191
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.138897250
Short name T47
Test name
Test status
Simulation time 1319656565 ps
CPU time 19.74 seconds
Started May 30 12:48:54 PM PDT 24
Finished May 30 12:49:15 PM PDT 24
Peak memory 214744 kb
Host smart-2f7e1162-e752-4db8-9fa6-b5b8f782e0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138897250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.138897250
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2900386903
Short name T42
Test name
Test status
Simulation time 727548681 ps
CPU time 10.34 seconds
Started May 30 12:49:05 PM PDT 24
Finished May 30 12:49:16 PM PDT 24
Peak memory 212680 kb
Host smart-8041c68e-f039-438b-afa0-33ca24d10f3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2900386903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2900386903
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1806006073
Short name T330
Test name
Test status
Simulation time 84865392743 ps
CPU time 183.83 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:52:14 PM PDT 24
Peak memory 222352 kb
Host smart-2e759b62-b507-43d5-b426-19593825243e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806006073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1806006073
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3679863710
Short name T52
Test name
Test status
Simulation time 55045670626 ps
CPU time 2030.53 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 01:23:02 PM PDT 24
Peak memory 240272 kb
Host smart-21412c3a-cbab-4a65-ae12-50d5d506fa79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679863710 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3679863710
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1452924773
Short name T69
Test name
Test status
Simulation time 174276824 ps
CPU time 8.32 seconds
Started May 30 12:49:01 PM PDT 24
Finished May 30 12:49:10 PM PDT 24
Peak memory 211228 kb
Host smart-90a52497-be27-40a1-aa98-9d9760d86e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452924773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1452924773
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3276290218
Short name T248
Test name
Test status
Simulation time 16175098452 ps
CPU time 250.23 seconds
Started May 30 12:49:01 PM PDT 24
Finished May 30 12:53:12 PM PDT 24
Peak memory 224604 kb
Host smart-2dd64152-4fc0-4060-8d48-3bc90d079dad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276290218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3276290218
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.747777929
Short name T251
Test name
Test status
Simulation time 589489930 ps
CPU time 13.73 seconds
Started May 30 12:48:59 PM PDT 24
Finished May 30 12:49:14 PM PDT 24
Peak memory 211388 kb
Host smart-e58a8659-3b24-4cdd-80bd-43e401365248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=747777929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.747777929
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3596924942
Short name T353
Test name
Test status
Simulation time 59348679918 ps
CPU time 48.32 seconds
Started May 30 12:49:01 PM PDT 24
Finished May 30 12:49:50 PM PDT 24
Peak memory 217636 kb
Host smart-c8c0e68c-0143-448a-82e5-c62fa1472ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596924942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3596924942
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.759798338
Short name T282
Test name
Test status
Simulation time 12673051779 ps
CPU time 48.52 seconds
Started May 30 12:48:52 PM PDT 24
Finished May 30 12:49:42 PM PDT 24
Peak memory 216184 kb
Host smart-44236450-2b36-40ac-b625-93811c878c21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759798338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.759798338
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2633337785
Short name T209
Test name
Test status
Simulation time 688902403 ps
CPU time 8.71 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:49:12 PM PDT 24
Peak memory 211228 kb
Host smart-f6d7ef9f-f49c-4252-a876-25d0bf2398bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633337785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2633337785
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2503824772
Short name T287
Test name
Test status
Simulation time 127649571218 ps
CPU time 671.64 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 01:00:14 PM PDT 24
Peak memory 233956 kb
Host smart-51d508f0-ac6f-4701-abb8-f90c09bdc59f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503824772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2503824772
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.199555743
Short name T173
Test name
Test status
Simulation time 335938691 ps
CPU time 19.35 seconds
Started May 30 12:48:55 PM PDT 24
Finished May 30 12:49:15 PM PDT 24
Peak memory 214780 kb
Host smart-d390f812-e4e7-4fdb-a339-8c6eb60726f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199555743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.199555743
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.132879942
Short name T152
Test name
Test status
Simulation time 7748446075 ps
CPU time 33.01 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:49:36 PM PDT 24
Peak memory 211860 kb
Host smart-b21e73fd-63ec-4673-9f9e-c35578a32711
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=132879942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.132879942
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3980195984
Short name T348
Test name
Test status
Simulation time 2975293038 ps
CPU time 42.03 seconds
Started May 30 12:49:01 PM PDT 24
Finished May 30 12:49:44 PM PDT 24
Peak memory 217616 kb
Host smart-fe6c4e12-e563-4ca6-ba93-662f7b11c58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980195984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3980195984
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4200621760
Short name T155
Test name
Test status
Simulation time 6643741762 ps
CPU time 73.04 seconds
Started May 30 12:49:01 PM PDT 24
Finished May 30 12:50:15 PM PDT 24
Peak memory 218296 kb
Host smart-8cb96b65-4fc4-411a-af9f-d6fb6bebc2d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200621760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4200621760
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.4294069196
Short name T159
Test name
Test status
Simulation time 12401442395 ps
CPU time 25.06 seconds
Started May 30 12:48:26 PM PDT 24
Finished May 30 12:48:52 PM PDT 24
Peak memory 212136 kb
Host smart-540c3d69-ec82-4a19-a5ac-89b158376f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294069196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4294069196
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.982583788
Short name T29
Test name
Test status
Simulation time 16178745564 ps
CPU time 144.94 seconds
Started May 30 12:48:31 PM PDT 24
Finished May 30 12:50:58 PM PDT 24
Peak memory 235736 kb
Host smart-7b55cccb-449f-486a-8d22-2d2f8a23f428
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982583788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.982583788
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3770741823
Short name T323
Test name
Test status
Simulation time 3772215013 ps
CPU time 43.28 seconds
Started May 30 12:48:33 PM PDT 24
Finished May 30 12:49:17 PM PDT 24
Peak memory 214728 kb
Host smart-9a179a41-2447-4df6-a251-47c6f2b66c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770741823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3770741823
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1491307699
Short name T201
Test name
Test status
Simulation time 1056269465 ps
CPU time 12.06 seconds
Started May 30 12:48:27 PM PDT 24
Finished May 30 12:48:40 PM PDT 24
Peak memory 211604 kb
Host smart-102977b2-2b8e-4d10-a3aa-16f373f89508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491307699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1491307699
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2146716301
Short name T38
Test name
Test status
Simulation time 18198153006 ps
CPU time 131.7 seconds
Started May 30 12:48:34 PM PDT 24
Finished May 30 12:50:46 PM PDT 24
Peak memory 236840 kb
Host smart-2429c190-cece-4b07-820a-e99fce39b124
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146716301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2146716301
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1356507961
Short name T183
Test name
Test status
Simulation time 17868765978 ps
CPU time 48.52 seconds
Started May 30 12:48:31 PM PDT 24
Finished May 30 12:49:21 PM PDT 24
Peak memory 217392 kb
Host smart-831628b8-8c0a-4c67-a500-b2ac2fc43596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356507961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1356507961
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.741910091
Short name T143
Test name
Test status
Simulation time 28983606352 ps
CPU time 65.11 seconds
Started May 30 12:48:31 PM PDT 24
Finished May 30 12:49:37 PM PDT 24
Peak memory 217936 kb
Host smart-f6db5cad-cf66-4abc-9209-37703cf919a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741910091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.741910091
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1912503318
Short name T165
Test name
Test status
Simulation time 9479341775 ps
CPU time 23.2 seconds
Started May 30 12:49:02 PM PDT 24
Finished May 30 12:49:27 PM PDT 24
Peak memory 212244 kb
Host smart-c4b00bf0-927f-414d-8cf6-9e1ae6d8e32b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912503318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1912503318
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3817202831
Short name T221
Test name
Test status
Simulation time 17471715321 ps
CPU time 154.31 seconds
Started May 30 12:49:01 PM PDT 24
Finished May 30 12:51:37 PM PDT 24
Peak memory 227960 kb
Host smart-35646b90-3781-4e48-a5b6-9f7726a072fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817202831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3817202831
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1572633676
Short name T195
Test name
Test status
Simulation time 17886129122 ps
CPU time 67.6 seconds
Started May 30 12:48:56 PM PDT 24
Finished May 30 12:50:04 PM PDT 24
Peak memory 215052 kb
Host smart-02142474-2f6e-4946-b691-4e26cbf6cb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572633676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1572633676
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.958132199
Short name T260
Test name
Test status
Simulation time 3563302124 ps
CPU time 44.18 seconds
Started May 30 12:48:53 PM PDT 24
Finished May 30 12:49:38 PM PDT 24
Peak memory 215772 kb
Host smart-e0ef0411-cc97-40b3-b5ce-9a0e999d2046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958132199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.958132199
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1478843212
Short name T133
Test name
Test status
Simulation time 54035642443 ps
CPU time 56.81 seconds
Started May 30 12:48:55 PM PDT 24
Finished May 30 12:49:53 PM PDT 24
Peak memory 218868 kb
Host smart-570a62c2-0e62-4aff-8f74-3f1643fa6433
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478843212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1478843212
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.801073255
Short name T175
Test name
Test status
Simulation time 1412089684 ps
CPU time 16.79 seconds
Started May 30 12:49:13 PM PDT 24
Finished May 30 12:49:31 PM PDT 24
Peak memory 211920 kb
Host smart-8141db70-25de-484b-bdaa-4cd5451a003c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801073255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.801073255
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2009350782
Short name T355
Test name
Test status
Simulation time 608576707214 ps
CPU time 416.53 seconds
Started May 30 12:49:17 PM PDT 24
Finished May 30 12:56:14 PM PDT 24
Peak memory 228356 kb
Host smart-66c66602-79f3-4655-96a5-e88bc109379b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009350782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2009350782
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3485454047
Short name T289
Test name
Test status
Simulation time 10697583517 ps
CPU time 50.73 seconds
Started May 30 12:49:15 PM PDT 24
Finished May 30 12:50:06 PM PDT 24
Peak memory 215032 kb
Host smart-4ae2b270-6d99-4996-825e-27bce3731e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485454047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3485454047
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2516163419
Short name T264
Test name
Test status
Simulation time 1887515408 ps
CPU time 22.06 seconds
Started May 30 12:49:06 PM PDT 24
Finished May 30 12:49:29 PM PDT 24
Peak memory 212324 kb
Host smart-d5f838ad-e23f-430f-8e3e-300e3695572e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516163419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2516163419
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2928000189
Short name T312
Test name
Test status
Simulation time 28972723183 ps
CPU time 47.25 seconds
Started May 30 12:49:06 PM PDT 24
Finished May 30 12:49:54 PM PDT 24
Peak memory 217288 kb
Host smart-b4502b7b-1ada-41a8-b96f-500258455fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928000189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2928000189
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1544399642
Short name T274
Test name
Test status
Simulation time 1096769637 ps
CPU time 61.81 seconds
Started May 30 12:48:58 PM PDT 24
Finished May 30 12:50:01 PM PDT 24
Peak memory 220912 kb
Host smart-d8b85fde-598e-4c08-8fe4-184bd806bad8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544399642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1544399642
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2262172077
Short name T338
Test name
Test status
Simulation time 4301866758 ps
CPU time 14.17 seconds
Started May 30 12:49:16 PM PDT 24
Finished May 30 12:49:31 PM PDT 24
Peak memory 211424 kb
Host smart-bddc8ee1-1fae-42a6-8daf-07ffcb71467d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262172077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2262172077
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.937396571
Short name T48
Test name
Test status
Simulation time 32492741561 ps
CPU time 366.96 seconds
Started May 30 12:49:12 PM PDT 24
Finished May 30 12:55:20 PM PDT 24
Peak memory 237852 kb
Host smart-a0679ad8-1497-42b4-ab9c-285cd7b7376b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937396571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.937396571
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3921384394
Short name T178
Test name
Test status
Simulation time 9158472965 ps
CPU time 49.16 seconds
Started May 30 12:49:07 PM PDT 24
Finished May 30 12:49:57 PM PDT 24
Peak memory 215108 kb
Host smart-16c73558-4f8e-46e1-8469-dfa901ed5152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921384394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3921384394
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1422733219
Short name T224
Test name
Test status
Simulation time 2651019448 ps
CPU time 18.19 seconds
Started May 30 12:49:12 PM PDT 24
Finished May 30 12:49:31 PM PDT 24
Peak memory 211284 kb
Host smart-8dccd71f-f01c-4af6-9c92-20c76eb8e30d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422733219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1422733219
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2045444593
Short name T324
Test name
Test status
Simulation time 23931171203 ps
CPU time 52.58 seconds
Started May 30 12:49:08 PM PDT 24
Finished May 30 12:50:01 PM PDT 24
Peak memory 218184 kb
Host smart-834b6901-15f8-49fa-9b50-61eff046eae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045444593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2045444593
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1361258725
Short name T213
Test name
Test status
Simulation time 17496693304 ps
CPU time 66.48 seconds
Started May 30 12:49:13 PM PDT 24
Finished May 30 12:50:20 PM PDT 24
Peak memory 222332 kb
Host smart-b4990921-d515-4db8-b0b9-8f37bec8d83c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361258725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1361258725
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2331163545
Short name T319
Test name
Test status
Simulation time 3557248137 ps
CPU time 28.95 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 12:49:40 PM PDT 24
Peak memory 211868 kb
Host smart-cbb15c2f-44ef-4ec7-96ed-131a5d29c358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331163545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2331163545
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1371792824
Short name T31
Test name
Test status
Simulation time 6112854427 ps
CPU time 180.49 seconds
Started May 30 12:49:11 PM PDT 24
Finished May 30 12:52:13 PM PDT 24
Peak memory 229872 kb
Host smart-4ac3256d-cc81-46e0-bad6-7fea7656febe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371792824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1371792824
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3514386507
Short name T236
Test name
Test status
Simulation time 17824678898 ps
CPU time 47.68 seconds
Started May 30 12:49:13 PM PDT 24
Finished May 30 12:50:01 PM PDT 24
Peak memory 213864 kb
Host smart-915b2a80-a958-4ce2-ab9a-c4845c9bdfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514386507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3514386507
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2838572363
Short name T2
Test name
Test status
Simulation time 16024803920 ps
CPU time 33.11 seconds
Started May 30 12:49:17 PM PDT 24
Finished May 30 12:49:51 PM PDT 24
Peak memory 212968 kb
Host smart-4f42e16f-d9bd-4a78-a3c8-2e440cf72fad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838572363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2838572363
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2231408357
Short name T354
Test name
Test status
Simulation time 51402012726 ps
CPU time 47.49 seconds
Started May 30 12:49:12 PM PDT 24
Finished May 30 12:50:01 PM PDT 24
Peak memory 216928 kb
Host smart-e9c25521-861d-431e-abc9-80331d22ac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231408357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2231408357
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1496903306
Short name T219
Test name
Test status
Simulation time 30094216160 ps
CPU time 134.02 seconds
Started May 30 12:49:12 PM PDT 24
Finished May 30 12:51:27 PM PDT 24
Peak memory 223012 kb
Host smart-d2725b45-5aeb-454d-93ba-cef3485802a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496903306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1496903306
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3005179953
Short name T343
Test name
Test status
Simulation time 2130384434 ps
CPU time 21.91 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 12:49:33 PM PDT 24
Peak memory 211776 kb
Host smart-8e9ffe84-072c-47ca-a344-d66cc7e97a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005179953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3005179953
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.829948687
Short name T223
Test name
Test status
Simulation time 131853433636 ps
CPU time 364.6 seconds
Started May 30 12:49:15 PM PDT 24
Finished May 30 12:55:20 PM PDT 24
Peak memory 237584 kb
Host smart-88bf4838-eb64-4e49-aae3-2e49de789863
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829948687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.829948687
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.329633071
Short name T250
Test name
Test status
Simulation time 25966012139 ps
CPU time 56.47 seconds
Started May 30 12:49:14 PM PDT 24
Finished May 30 12:50:11 PM PDT 24
Peak memory 215168 kb
Host smart-5881ceb5-1387-41d5-a47e-ee0f02a5a975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329633071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.329633071
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1572882246
Short name T314
Test name
Test status
Simulation time 15106147145 ps
CPU time 32.37 seconds
Started May 30 12:49:13 PM PDT 24
Finished May 30 12:49:46 PM PDT 24
Peak memory 211416 kb
Host smart-7691b9ae-7e0f-4983-b4e5-a2e29486da3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1572882246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1572882246
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1455589651
Short name T186
Test name
Test status
Simulation time 915613893 ps
CPU time 11.36 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 12:49:22 PM PDT 24
Peak memory 213212 kb
Host smart-6c92cca0-18f3-4ee9-adc8-e634630c4537
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455589651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1455589651
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3211633058
Short name T341
Test name
Test status
Simulation time 9943566152 ps
CPU time 15.25 seconds
Started May 30 12:49:08 PM PDT 24
Finished May 30 12:49:24 PM PDT 24
Peak memory 211336 kb
Host smart-2f599644-4399-484b-8d08-dce493a9a6af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211633058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3211633058
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1717192314
Short name T342
Test name
Test status
Simulation time 21742922308 ps
CPU time 394.47 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 12:55:46 PM PDT 24
Peak memory 225712 kb
Host smart-50c6edc3-7485-4516-bc22-fce9c05d4651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717192314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1717192314
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.467856825
Short name T317
Test name
Test status
Simulation time 4006723263 ps
CPU time 32.44 seconds
Started May 30 12:49:11 PM PDT 24
Finished May 30 12:49:44 PM PDT 24
Peak memory 214680 kb
Host smart-5db23281-ec65-46f1-b99e-32138ca495b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467856825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.467856825
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2564423909
Short name T350
Test name
Test status
Simulation time 1718111292 ps
CPU time 20.19 seconds
Started May 30 12:49:11 PM PDT 24
Finished May 30 12:49:32 PM PDT 24
Peak memory 211244 kb
Host smart-74c355e3-b04c-4f59-99fb-12610d76fa6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2564423909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2564423909
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3832798707
Short name T148
Test name
Test status
Simulation time 5983673081 ps
CPU time 52.67 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 12:50:04 PM PDT 24
Peak memory 217120 kb
Host smart-e923ac01-24e8-414d-9fc9-5efa8a761504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832798707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3832798707
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.304138211
Short name T271
Test name
Test status
Simulation time 1518639036 ps
CPU time 23.98 seconds
Started May 30 12:49:15 PM PDT 24
Finished May 30 12:49:40 PM PDT 24
Peak memory 217948 kb
Host smart-662c5897-d43c-44f2-9ea8-4ebdc65f623f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304138211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.304138211
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.711913018
Short name T36
Test name
Test status
Simulation time 3325165416 ps
CPU time 19.69 seconds
Started May 30 12:49:16 PM PDT 24
Finished May 30 12:49:37 PM PDT 24
Peak memory 211712 kb
Host smart-acc01c96-1fdd-45ef-a12e-1556094a9a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711913018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.711913018
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2318188340
Short name T45
Test name
Test status
Simulation time 71941574087 ps
CPU time 684.52 seconds
Started May 30 12:49:14 PM PDT 24
Finished May 30 01:00:39 PM PDT 24
Peak memory 234004 kb
Host smart-5a2f2021-f999-46b1-b8c0-311369c5a6b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318188340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2318188340
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.996713227
Short name T40
Test name
Test status
Simulation time 16721585531 ps
CPU time 68.73 seconds
Started May 30 12:49:21 PM PDT 24
Finished May 30 12:50:30 PM PDT 24
Peak memory 215168 kb
Host smart-3e77a798-f768-40cd-b5c5-359e646e1e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996713227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.996713227
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.946443407
Short name T231
Test name
Test status
Simulation time 2544308368 ps
CPU time 24.84 seconds
Started May 30 12:49:16 PM PDT 24
Finished May 30 12:49:41 PM PDT 24
Peak memory 212264 kb
Host smart-20ee3f6c-c521-4bd2-8708-52539ebfdaff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946443407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.946443407
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3521609692
Short name T321
Test name
Test status
Simulation time 839350158 ps
CPU time 20.41 seconds
Started May 30 12:49:15 PM PDT 24
Finished May 30 12:49:37 PM PDT 24
Peak memory 216448 kb
Host smart-62e41772-8830-4c72-a8ff-037110c6b1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521609692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3521609692
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3605917214
Short name T311
Test name
Test status
Simulation time 685407959 ps
CPU time 13.54 seconds
Started May 30 12:49:15 PM PDT 24
Finished May 30 12:49:29 PM PDT 24
Peak memory 211064 kb
Host smart-2f5ef5ba-1f6e-4ab2-ad7f-de4c148cd4f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605917214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3605917214
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2144693231
Short name T335
Test name
Test status
Simulation time 2214774246 ps
CPU time 15.19 seconds
Started May 30 12:49:13 PM PDT 24
Finished May 30 12:49:29 PM PDT 24
Peak memory 211384 kb
Host smart-d579f748-e951-4237-90eb-7f1eadf0dbe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144693231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2144693231
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2850423388
Short name T131
Test name
Test status
Simulation time 800026865751 ps
CPU time 407.97 seconds
Started May 30 12:49:21 PM PDT 24
Finished May 30 12:56:10 PM PDT 24
Peak memory 240564 kb
Host smart-11f910ae-41d7-45a3-91f5-15c3955602cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850423388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2850423388
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2861795842
Short name T156
Test name
Test status
Simulation time 5355090439 ps
CPU time 51.14 seconds
Started May 30 12:49:16 PM PDT 24
Finished May 30 12:50:08 PM PDT 24
Peak memory 215172 kb
Host smart-5abbc373-1cbe-40c1-850e-047bd842d253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861795842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2861795842
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3807360275
Short name T261
Test name
Test status
Simulation time 8207868687 ps
CPU time 33.57 seconds
Started May 30 12:49:11 PM PDT 24
Finished May 30 12:49:46 PM PDT 24
Peak memory 211544 kb
Host smart-cef9f3a3-a31a-4697-b884-66615bab605d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807360275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3807360275
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1448967971
Short name T267
Test name
Test status
Simulation time 6948296036 ps
CPU time 67.27 seconds
Started May 30 12:49:11 PM PDT 24
Finished May 30 12:50:19 PM PDT 24
Peak memory 217236 kb
Host smart-bee0188f-77ef-428d-9d7d-0b7b1c4accf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448967971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1448967971
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2307886606
Short name T297
Test name
Test status
Simulation time 7017705216 ps
CPU time 78.45 seconds
Started May 30 12:49:12 PM PDT 24
Finished May 30 12:50:31 PM PDT 24
Peak memory 219840 kb
Host smart-21102b6c-0889-4491-bb99-8ac671b92ad1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307886606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2307886606
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.192155680
Short name T157
Test name
Test status
Simulation time 688753270 ps
CPU time 8.47 seconds
Started May 30 12:49:14 PM PDT 24
Finished May 30 12:49:23 PM PDT 24
Peak memory 211204 kb
Host smart-133188e6-1774-4419-9b5c-bf7b15d38a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192155680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.192155680
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2220582253
Short name T277
Test name
Test status
Simulation time 37041638147 ps
CPU time 191.19 seconds
Started May 30 12:49:11 PM PDT 24
Finished May 30 12:52:23 PM PDT 24
Peak memory 240804 kb
Host smart-b39a130d-5796-4f43-98d1-49c30e993b32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220582253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2220582253
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.599320003
Short name T98
Test name
Test status
Simulation time 92897923855 ps
CPU time 70.26 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:50:20 PM PDT 24
Peak memory 214304 kb
Host smart-68fbe254-6565-4f74-b483-2981e3f0d02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599320003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.599320003
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3973411494
Short name T216
Test name
Test status
Simulation time 4632029790 ps
CPU time 17.23 seconds
Started May 30 12:49:12 PM PDT 24
Finished May 30 12:49:31 PM PDT 24
Peak memory 211528 kb
Host smart-63846496-31cc-404e-88df-af2bc424b7ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3973411494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3973411494
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2155708309
Short name T238
Test name
Test status
Simulation time 15450510550 ps
CPU time 68.75 seconds
Started May 30 12:49:12 PM PDT 24
Finished May 30 12:50:22 PM PDT 24
Peak memory 216824 kb
Host smart-ad16e73c-3b25-4f75-aebf-787785ff93d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155708309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2155708309
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3716062857
Short name T198
Test name
Test status
Simulation time 6876017450 ps
CPU time 23.83 seconds
Started May 30 12:49:13 PM PDT 24
Finished May 30 12:49:38 PM PDT 24
Peak memory 212304 kb
Host smart-7620d5fb-c7c3-40ea-8759-5f01a61a2f7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716062857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3716062857
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1045937795
Short name T252
Test name
Test status
Simulation time 53715970456 ps
CPU time 692.51 seconds
Started May 30 12:49:10 PM PDT 24
Finished May 30 01:00:43 PM PDT 24
Peak memory 235736 kb
Host smart-72c31347-e9d2-4ae1-8ed9-9c5b0d38232c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045937795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1045937795
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.73497252
Short name T26
Test name
Test status
Simulation time 9526642663 ps
CPU time 46.96 seconds
Started May 30 12:49:08 PM PDT 24
Finished May 30 12:49:56 PM PDT 24
Peak memory 215244 kb
Host smart-1fed4f29-ebb9-4b54-8df4-b2d5a41d0cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73497252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.73497252
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2855510097
Short name T112
Test name
Test status
Simulation time 2321382055 ps
CPU time 24.54 seconds
Started May 30 12:49:09 PM PDT 24
Finished May 30 12:49:35 PM PDT 24
Peak memory 211460 kb
Host smart-4800bb1e-922d-472a-944b-3c8d9a61a317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2855510097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2855510097
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.313164416
Short name T276
Test name
Test status
Simulation time 41111899770 ps
CPU time 44.17 seconds
Started May 30 12:49:11 PM PDT 24
Finished May 30 12:49:56 PM PDT 24
Peak memory 217364 kb
Host smart-44d85945-68a7-4ce5-b807-950ab4913298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313164416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.313164416
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1138333603
Short name T138
Test name
Test status
Simulation time 6956902839 ps
CPU time 69.01 seconds
Started May 30 12:49:12 PM PDT 24
Finished May 30 12:50:22 PM PDT 24
Peak memory 219260 kb
Host smart-7287b04d-3d49-4672-a9a1-a94015c56dab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138333603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1138333603
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2370032553
Short name T68
Test name
Test status
Simulation time 2867181407 ps
CPU time 25.03 seconds
Started May 30 12:48:43 PM PDT 24
Finished May 30 12:49:09 PM PDT 24
Peak memory 211840 kb
Host smart-99f1debd-82a8-4557-91eb-df41541ef97f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370032553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2370032553
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2144437441
Short name T192
Test name
Test status
Simulation time 7694385259 ps
CPU time 41.29 seconds
Started May 30 12:48:30 PM PDT 24
Finished May 30 12:49:13 PM PDT 24
Peak memory 215476 kb
Host smart-f69712ca-f1a7-48ad-91c2-3f7281723590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144437441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2144437441
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4107559952
Short name T146
Test name
Test status
Simulation time 8231192017 ps
CPU time 33.4 seconds
Started May 30 12:48:30 PM PDT 24
Finished May 30 12:49:05 PM PDT 24
Peak memory 212568 kb
Host smart-8948d147-3fc0-4801-bb3b-e166ac564ff8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107559952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4107559952
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2348770026
Short name T172
Test name
Test status
Simulation time 2302732982 ps
CPU time 20.37 seconds
Started May 30 12:48:31 PM PDT 24
Finished May 30 12:48:53 PM PDT 24
Peak memory 217036 kb
Host smart-7b257258-8d09-4109-b88d-8a6eca9ca76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348770026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2348770026
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.609698442
Short name T337
Test name
Test status
Simulation time 918570547 ps
CPU time 8.3 seconds
Started May 30 12:48:45 PM PDT 24
Finished May 30 12:48:54 PM PDT 24
Peak memory 211272 kb
Host smart-331adc24-c99f-4c3c-9273-6c367dd57e67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609698442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.609698442
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1662612832
Short name T279
Test name
Test status
Simulation time 83514989852 ps
CPU time 487.88 seconds
Started May 30 12:48:54 PM PDT 24
Finished May 30 12:57:03 PM PDT 24
Peak memory 217776 kb
Host smart-217dc267-af6d-4f6c-9b8e-253a6d621df0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662612832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1662612832
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2710261147
Short name T345
Test name
Test status
Simulation time 42339297894 ps
CPU time 73.25 seconds
Started May 30 12:48:40 PM PDT 24
Finished May 30 12:49:54 PM PDT 24
Peak memory 215024 kb
Host smart-4ab64aec-0e27-4896-941f-ec92c0092738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710261147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2710261147
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.91271483
Short name T329
Test name
Test status
Simulation time 701012260 ps
CPU time 10.57 seconds
Started May 30 12:48:39 PM PDT 24
Finished May 30 12:48:50 PM PDT 24
Peak memory 212464 kb
Host smart-cde36c26-f7bd-429f-a2b1-e84c5796a38c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91271483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.91271483
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2773907256
Short name T255
Test name
Test status
Simulation time 26198536490 ps
CPU time 67.99 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 12:49:50 PM PDT 24
Peak memory 218776 kb
Host smart-b46fcbb6-251e-45f0-81d7-3b46e2ad6e27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773907256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2773907256
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1017690755
Short name T57
Test name
Test status
Simulation time 168298457628 ps
CPU time 957.13 seconds
Started May 30 12:48:41 PM PDT 24
Finished May 30 01:04:39 PM PDT 24
Peak memory 234496 kb
Host smart-6b870f7e-1a8b-4bdd-a589-7a3a49103243
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017690755 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1017690755
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2555690870
Short name T246
Test name
Test status
Simulation time 3925040574 ps
CPU time 19.15 seconds
Started May 30 12:48:40 PM PDT 24
Finished May 30 12:49:00 PM PDT 24
Peak memory 211372 kb
Host smart-895ffde4-9aed-466f-86be-2b44c6415a54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555690870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2555690870
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3949183593
Short name T15
Test name
Test status
Simulation time 73083737440 ps
CPU time 687.33 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 01:00:10 PM PDT 24
Peak memory 225596 kb
Host smart-994fa290-daf0-41aa-af94-ea90d66cfb72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949183593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3949183593
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2104917597
Short name T28
Test name
Test status
Simulation time 9861195193 ps
CPU time 50.93 seconds
Started May 30 12:48:50 PM PDT 24
Finished May 30 12:49:42 PM PDT 24
Peak memory 213868 kb
Host smart-77870189-d40e-47c3-bc05-76b1532c27a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104917597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2104917597
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1915355243
Short name T349
Test name
Test status
Simulation time 2063385496 ps
CPU time 16.35 seconds
Started May 30 12:48:39 PM PDT 24
Finished May 30 12:48:56 PM PDT 24
Peak memory 211532 kb
Host smart-36087814-60f3-4f79-a9b7-2ff9dd0211d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1915355243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1915355243
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.927522345
Short name T62
Test name
Test status
Simulation time 1280826968 ps
CPU time 20.51 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 12:49:03 PM PDT 24
Peak memory 217612 kb
Host smart-502962df-1d7c-43a6-8575-1183dee9989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927522345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.927522345
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3768932585
Short name T211
Test name
Test status
Simulation time 3456733281 ps
CPU time 18.7 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 12:49:02 PM PDT 24
Peak memory 213544 kb
Host smart-6a092570-5ede-486f-880c-031dbee7e59c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768932585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3768932585
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1007500264
Short name T55
Test name
Test status
Simulation time 128023349818 ps
CPU time 2476.02 seconds
Started May 30 12:48:55 PM PDT 24
Finished May 30 01:30:13 PM PDT 24
Peak memory 251828 kb
Host smart-331dde46-dc94-468d-891d-f8e63c082730
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007500264 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1007500264
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2339868127
Short name T168
Test name
Test status
Simulation time 7533430359 ps
CPU time 20.6 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 12:49:03 PM PDT 24
Peak memory 211412 kb
Host smart-143753aa-cb70-4e63-a7e6-29a8d9b32d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339868127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2339868127
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1790419808
Short name T140
Test name
Test status
Simulation time 339211947908 ps
CPU time 879.27 seconds
Started May 30 12:48:49 PM PDT 24
Finished May 30 01:03:30 PM PDT 24
Peak memory 237868 kb
Host smart-14cc9670-7a63-4749-af9d-00c22f05161c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790419808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1790419808
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.758604500
Short name T228
Test name
Test status
Simulation time 11495872934 ps
CPU time 27.67 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 12:49:10 PM PDT 24
Peak memory 215028 kb
Host smart-d9bb9938-4487-44d1-96f5-22a841a4ca02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758604500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.758604500
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1214017169
Short name T253
Test name
Test status
Simulation time 11422956923 ps
CPU time 30.46 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 12:49:13 PM PDT 24
Peak memory 211804 kb
Host smart-b2222374-0048-486b-915c-43077c9183c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214017169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1214017169
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3937595576
Short name T164
Test name
Test status
Simulation time 5872306361 ps
CPU time 65.54 seconds
Started May 30 12:48:40 PM PDT 24
Finished May 30 12:49:46 PM PDT 24
Peak memory 217352 kb
Host smart-6a2f98fd-0754-475d-9319-794f511d2911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937595576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3937595576
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.841664195
Short name T132
Test name
Test status
Simulation time 2411268392 ps
CPU time 34.72 seconds
Started May 30 12:48:41 PM PDT 24
Finished May 30 12:49:16 PM PDT 24
Peak memory 219068 kb
Host smart-28bd9d4f-6861-4bc7-97ac-f5db78009681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841664195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.841664195
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2102013100
Short name T275
Test name
Test status
Simulation time 4129815176 ps
CPU time 32.98 seconds
Started May 30 12:48:42 PM PDT 24
Finished May 30 12:49:16 PM PDT 24
Peak memory 211684 kb
Host smart-89ad505d-31b1-4de1-8da0-6729648f4185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102013100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2102013100
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2037889246
Short name T130
Test name
Test status
Simulation time 5633842817 ps
CPU time 146.96 seconds
Started May 30 12:48:54 PM PDT 24
Finished May 30 12:51:22 PM PDT 24
Peak memory 237920 kb
Host smart-d5281288-161f-481d-ae55-be028542c552
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037889246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2037889246
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1543457623
Short name T185
Test name
Test status
Simulation time 6520516911 ps
CPU time 53.16 seconds
Started May 30 12:48:49 PM PDT 24
Finished May 30 12:49:44 PM PDT 24
Peak memory 215076 kb
Host smart-9e049f06-d975-477b-bd7e-2e89e20d76a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543457623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1543457623
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3804138799
Short name T217
Test name
Test status
Simulation time 6006447905 ps
CPU time 54.99 seconds
Started May 30 12:48:41 PM PDT 24
Finished May 30 12:49:37 PM PDT 24
Peak memory 215196 kb
Host smart-67fb368a-b795-40d1-ab18-7b657cb1f65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804138799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3804138799
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1802896559
Short name T46
Test name
Test status
Simulation time 6633767351 ps
CPU time 63.06 seconds
Started May 30 12:48:50 PM PDT 24
Finished May 30 12:49:54 PM PDT 24
Peak memory 219356 kb
Host smart-279ffba0-57ef-4230-9431-a75ee9fa36a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802896559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1802896559
Directory /workspace/9.rom_ctrl_stress_all/latest
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