Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

854090

1

T1

46

T3

62

T4

159

full_word

543118

1

T1

6

T2

2

T3

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1396908	1			T1	52		T2	2		T3	71
auto[TlIntgErrCmd]	94	1			T49	8		T55	2		T56	3
auto[TlIntgErrData]	93	1			T49	8		T55	3		T56	1
auto[TlIntgErrBoth]	113	1			T49	4		T55	5		T56	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232937

1

T1

52

T2

2

T3

71

auto[1]

1164271

1

T11

110310

T14

199202

T15

303264

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	103669	1			T1	46		T3	62		T4	159
auto[TlIntgErrNone]	partial	auto[1]	750148	1			T11	70021		T14	128124		T15	195856
auto[TlIntgErrNone]	full_word	auto[0]	129139	1			T1	6		T2	2		T3	9
auto[TlIntgErrNone]	full_word	auto[1]	413952	1			T11	40289		T14	71078		T15	107408
auto[TlIntgErrCmd]	partial	auto[0]	27	1			T49	1		T56	1		T105	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T49	7		T55	1		T56	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T113	1		T108	1		T109	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T55	1		T56	1		T106	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T49	4		T55	2		T105	2
auto[TlIntgErrData]	partial	auto[1]	41	1			T49	4		T55	1		T56	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T112	1		T114	1		T115	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T116	1		T107	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T49	1		T55	2		T56	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T49	3		T55	1		T56	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T55	2		T106	1		T117	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T56	1		T118	1		T119	3