Line Coverage for Module :
rom_ctrl
| Line No. | Total | Covered | Percent |
TOTAL | | 65 | 65 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 127 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 415 | 1 | 1 | 100.00 |
CONT_ASSIGN | 415 | 1 | 1 | 100.00 |
CONT_ASSIGN | 415 | 1 | 1 | 100.00 |
CONT_ASSIGN | 415 | 1 | 1 | 100.00 |
CONT_ASSIGN | 415 | 1 | 1 | 100.00 |
CONT_ASSIGN | 415 | 1 | 1 | 100.00 |
CONT_ASSIGN | 415 | 1 | 1 | 100.00 |
CONT_ASSIGN | 415 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 427 | 1 | 1 | 100.00 |
CONT_ASSIGN | 430 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 433 | 1 | 1 | 100.00 |
CONT_ASSIGN | 438 | 1 | 1 | 100.00 |
CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
125 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
1 |
1 |
131 |
1 |
1 |
212 |
1 |
1 |
258 |
1 |
1 |
313 |
1 |
1 |
414 |
8 |
8 |
415 |
8 |
8 |
417 |
8 |
8 |
418 |
8 |
8 |
420 |
8 |
8 |
421 |
8 |
8 |
425 |
1 |
1 |
427 |
1 |
1 |
430 |
1 |
1 |
431 |
1 |
1 |
432 |
1 |
1 |
433 |
1 |
1 |
438 |
1 |
1 |
442 |
1 |
1 |
Cond Coverage for Module :
rom_ctrl
| Total | Covered | Percent |
Conditions | 58 | 57 | 98.28 |
Logical | 58 | 57 | 98.28 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 212
EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 258
EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
---------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T25,T27 |
1 | 1 | Covered | T1,T2,T3 |
LINE 418
EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 418
SUB-EXPRESSION (0 == exp_digest_idx)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 418
EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 418
SUB-EXPRESSION (1 == exp_digest_idx)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 418
EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 418
SUB-EXPRESSION (2 == exp_digest_idx)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 418
EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 418
SUB-EXPRESSION (3 == exp_digest_idx)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 418
EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 418
SUB-EXPRESSION (4 == exp_digest_idx)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 418
EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 418
SUB-EXPRESSION (5 == exp_digest_idx)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 418
EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 418
SUB-EXPRESSION (6 == exp_digest_idx)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 418
EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 418
SUB-EXPRESSION (7 == exp_digest_idx)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 425
EXPRESSION (rom_integrity_error | reg_integrity_error)
---------1--------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T28,T30,T31 |
1 | 0 | Not Covered | |
LINE 427
EXPRESSION (checker_alert | mux_alert)
------1------ ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T25,T27 |
1 | 0 | Covered | T2,T10,T28 |
LINE 438
EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T32 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T7,T32 |
LINE 442
EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
---------1--------- ------2------ ----3----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T2,T25,T27 |
0 | 1 | 0 | Covered | T2,T10,T28 |
1 | 0 | 0 | Covered | T28,T30,T31 |
Toggle Coverage for Module :
rom_ctrl
| Total | Covered | Percent |
Totals |
61 |
56 |
91.80 |
Total Bits |
2882 |
2805 |
97.33 |
Total Bits 0->1 |
1441 |
1402 |
97.29 |
Total Bits 1->0 |
1441 |
1403 |
97.36 |
| | | |
Ports |
61 |
56 |
91.80 |
Port Bits |
2882 |
2805 |
97.33 |
Port Bits 0->1 |
1441 |
1402 |
97.29 |
Port Bits 1->0 |
1441 |
1403 |
97.36 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rom_cfg_i.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
rom_cfg_i.cfg_en |
No |
No |
|
No |
|
INPUT |
rom_tl_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rom_tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
rom_tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
rom_tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T6,T11,T12 |
Yes |
T6,T11,T12 |
INPUT |
rom_tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
rom_tl_i.a_data[31:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
rom_tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
rom_tl_i.a_address[31:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
rom_tl_i.a_source[7:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
rom_tl_i.a_size[1:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
rom_tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
rom_tl_i.a_opcode[2:0] |
Yes |
Yes |
T6,T11,T12 |
Yes |
T6,T10,T11 |
INPUT |
rom_tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rom_tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
rom_tl_o.d_error |
Yes |
Yes |
T11,T14,T15 |
Yes |
T11,T14,T15 |
OUTPUT |
rom_tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
rom_tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
rom_tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
rom_tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_source[7:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
rom_tl_o.d_size[1:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
rom_tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_opcode[0] |
Yes |
Yes |
*T11,*T14,*T15 |
Yes |
T11,T14,T15 |
OUTPUT |
rom_tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
regs_tl_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T9,T10,T11 |
Yes |
T9,T11,T32 |
INPUT |
regs_tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_i.a_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_i.a_opcode[2:0] |
Yes |
Yes |
T5,T7,T9 |
Yes |
T5,T7,T9 |
INPUT |
regs_tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
regs_tl_o.d_error |
Yes |
Yes |
T11,T14,T15 |
Yes |
T11,T14,T15 |
OUTPUT |
regs_tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
regs_tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
regs_tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
regs_tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
regs_tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
regs_tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
regs_tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T2,T5,T7 |
Yes |
T2,T5,T7 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T2,T5,T7 |
Yes |
T2,T5,T7 |
OUTPUT |
pwrmgr_data_o.good[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
pwrmgr_data_o.done[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
keymgr_data_o.valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
keymgr_data_o.data[255:0] |
Yes |
Yes |
T1,T2,T9 |
Yes |
T1,T2,T4 |
OUTPUT |
kmac_data_i.error |
No |
Yes |
T10,T17,T18 |
No |
|
INPUT |
kmac_data_i.digest_share1[383:0] |
Yes |
Yes |
T1,T2,T6 |
Yes |
T2,T3,T9 |
INPUT |
kmac_data_i.digest_share0[383:0] |
Yes |
Yes |
T2,T6,T11 |
Yes |
T2,T3,T9 |
INPUT |
kmac_data_i.done |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
kmac_data_i.ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
kmac_data_o.last |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_data_o.strb[7:0] |
No |
No |
|
No |
|
OUTPUT |
kmac_data_o.data[38:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
kmac_data_o.data[63:39] |
No |
No |
|
No |
|
OUTPUT |
kmac_data_o.valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
rom_ctrl
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
212 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 212 (rom_tl_i.a_valid) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
rom_ctrl
Assertion Details
AlertTxOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
266291347 |
0 |
0 |
T1 |
558704 |
558567 |
0 |
0 |
T2 |
234836 |
232602 |
0 |
0 |
T3 |
458142 |
458018 |
0 |
0 |
T4 |
360216 |
360116 |
0 |
0 |
T5 |
328804 |
328753 |
0 |
0 |
T6 |
34570 |
34464 |
0 |
0 |
T7 |
16769 |
16673 |
0 |
0 |
T8 |
197397 |
197309 |
0 |
0 |
T9 |
101157 |
101132 |
0 |
0 |
T10 |
571913 |
571778 |
0 |
0 |
BusRomIndicesMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266450622 |
266281044 |
0 |
0 |
T1 |
558704 |
558567 |
0 |
0 |
T2 |
234530 |
232354 |
0 |
0 |
T3 |
458142 |
458018 |
0 |
0 |
T4 |
360216 |
360116 |
0 |
0 |
T5 |
328804 |
328753 |
0 |
0 |
T6 |
34570 |
34464 |
0 |
0 |
T7 |
16769 |
16673 |
0 |
0 |
T8 |
197397 |
197309 |
0 |
0 |
T9 |
101157 |
101132 |
0 |
0 |
T10 |
571913 |
571778 |
0 |
0 |
FpvSecCmFifoRptrCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
0 |
0 |
0 |
FpvSecCmFifoWptrCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
90 |
0 |
0 |
T17 |
33077 |
0 |
0 |
0 |
T28 |
267594 |
10 |
0 |
0 |
T30 |
0 |
20 |
0 |
0 |
T31 |
0 |
20 |
0 |
0 |
T33 |
0 |
20 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T35 |
493500 |
0 |
0 |
0 |
T36 |
71184 |
0 |
0 |
0 |
T37 |
644149 |
0 |
0 |
0 |
T38 |
396704 |
0 |
0 |
0 |
T39 |
17579 |
0 |
0 |
0 |
T40 |
204724 |
0 |
0 |
0 |
T41 |
377027 |
0 |
0 |
0 |
T42 |
164918 |
0 |
0 |
0 |
KeymgrDataODataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
19969294 |
0 |
0 |
T1 |
558704 |
1417 |
0 |
0 |
T2 |
234836 |
8048 |
0 |
0 |
T3 |
458142 |
1768 |
0 |
0 |
T4 |
360216 |
1153 |
0 |
0 |
T5 |
328804 |
76 |
0 |
0 |
T6 |
34570 |
1670 |
0 |
0 |
T7 |
16769 |
276 |
0 |
0 |
T8 |
197397 |
910 |
0 |
0 |
T9 |
101157 |
1375 |
0 |
0 |
T10 |
571913 |
184 |
0 |
0 |
KeymgrDataODataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
266291347 |
0 |
0 |
T1 |
558704 |
558567 |
0 |
0 |
T2 |
234836 |
232602 |
0 |
0 |
T3 |
458142 |
458018 |
0 |
0 |
T4 |
360216 |
360116 |
0 |
0 |
T5 |
328804 |
328753 |
0 |
0 |
T6 |
34570 |
34464 |
0 |
0 |
T7 |
16769 |
16673 |
0 |
0 |
T8 |
197397 |
197309 |
0 |
0 |
T9 |
101157 |
101132 |
0 |
0 |
T10 |
571913 |
571778 |
0 |
0 |
KeymgrDataOValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
266291347 |
0 |
0 |
T1 |
558704 |
558567 |
0 |
0 |
T2 |
234836 |
232602 |
0 |
0 |
T3 |
458142 |
458018 |
0 |
0 |
T4 |
360216 |
360116 |
0 |
0 |
T5 |
328804 |
328753 |
0 |
0 |
T6 |
34570 |
34464 |
0 |
0 |
T7 |
16769 |
16673 |
0 |
0 |
T8 |
197397 |
197309 |
0 |
0 |
T9 |
101157 |
101132 |
0 |
0 |
T10 |
571913 |
571778 |
0 |
0 |
KeymgrValidChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
0 |
0 |
307 |
KmacDataODataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
246200851 |
0 |
0 |
T1 |
558704 |
557032 |
0 |
0 |
T2 |
234836 |
223655 |
0 |
0 |
T3 |
458142 |
456145 |
0 |
0 |
T4 |
360216 |
358889 |
0 |
0 |
T5 |
328804 |
328581 |
0 |
0 |
T6 |
34570 |
32752 |
0 |
0 |
T7 |
16769 |
16376 |
0 |
0 |
T8 |
197397 |
196369 |
0 |
0 |
T9 |
101157 |
100971 |
0 |
0 |
T10 |
571913 |
571459 |
0 |
0 |
KmacDataODataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
266291347 |
0 |
0 |
T1 |
558704 |
558567 |
0 |
0 |
T2 |
234836 |
232602 |
0 |
0 |
T3 |
458142 |
458018 |
0 |
0 |
T4 |
360216 |
360116 |
0 |
0 |
T5 |
328804 |
328753 |
0 |
0 |
T6 |
34570 |
34464 |
0 |
0 |
T7 |
16769 |
16673 |
0 |
0 |
T8 |
197397 |
197309 |
0 |
0 |
T9 |
101157 |
101132 |
0 |
0 |
T10 |
571913 |
571778 |
0 |
0 |
KmacDataOValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
266291347 |
0 |
0 |
T1 |
558704 |
558567 |
0 |
0 |
T2 |
234836 |
232602 |
0 |
0 |
T3 |
458142 |
458018 |
0 |
0 |
T4 |
360216 |
360116 |
0 |
0 |
T5 |
328804 |
328753 |
0 |
0 |
T6 |
34570 |
34464 |
0 |
0 |
T7 |
16769 |
16673 |
0 |
0 |
T8 |
197397 |
197309 |
0 |
0 |
T9 |
101157 |
101132 |
0 |
0 |
T10 |
571913 |
571778 |
0 |
0 |
PwrmgrDataChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
0 |
0 |
307 |
PwrmgrDataOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
266291347 |
0 |
0 |
T1 |
558704 |
558567 |
0 |
0 |
T2 |
234836 |
232602 |
0 |
0 |
T3 |
458142 |
458018 |
0 |
0 |
T4 |
360216 |
360116 |
0 |
0 |
T5 |
328804 |
328753 |
0 |
0 |
T6 |
34570 |
34464 |
0 |
0 |
T7 |
16769 |
16673 |
0 |
0 |
T8 |
197397 |
197309 |
0 |
0 |
T9 |
101157 |
101132 |
0 |
0 |
T10 |
571913 |
571778 |
0 |
0 |
RegsTlOAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
266291347 |
0 |
0 |
T1 |
558704 |
558567 |
0 |
0 |
T2 |
234836 |
232602 |
0 |
0 |
T3 |
458142 |
458018 |
0 |
0 |
T4 |
360216 |
360116 |
0 |
0 |
T5 |
328804 |
328753 |
0 |
0 |
T6 |
34570 |
34464 |
0 |
0 |
T7 |
16769 |
16673 |
0 |
0 |
T8 |
197397 |
197309 |
0 |
0 |
T9 |
101157 |
101132 |
0 |
0 |
T10 |
571913 |
571778 |
0 |
0 |
RegsTlODDataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
2651072 |
0 |
0 |
T1 |
558704 |
32 |
0 |
0 |
T2 |
234836 |
95 |
0 |
0 |
T3 |
458142 |
118 |
0 |
0 |
T4 |
360216 |
0 |
0 |
0 |
T5 |
328804 |
13 |
0 |
0 |
T6 |
34570 |
32 |
0 |
0 |
T7 |
16769 |
16 |
0 |
0 |
T8 |
197397 |
0 |
0 |
0 |
T9 |
101157 |
75 |
0 |
0 |
T10 |
571913 |
1 |
0 |
0 |
T11 |
0 |
105780 |
0 |
0 |
T32 |
0 |
7 |
0 |
0 |
RegsTlODDataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
266291347 |
0 |
0 |
T1 |
558704 |
558567 |
0 |
0 |
T2 |
234836 |
232602 |
0 |
0 |
T3 |
458142 |
458018 |
0 |
0 |
T4 |
360216 |
360116 |
0 |
0 |
T5 |
328804 |
328753 |
0 |
0 |
T6 |
34570 |
34464 |
0 |
0 |
T7 |
16769 |
16673 |
0 |
0 |
T8 |
197397 |
197309 |
0 |
0 |
T9 |
101157 |
101132 |
0 |
0 |
T10 |
571913 |
571778 |
0 |
0 |
RegsTlODValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
266291347 |
0 |
0 |
T1 |
558704 |
558567 |
0 |
0 |
T2 |
234836 |
232602 |
0 |
0 |
T3 |
458142 |
458018 |
0 |
0 |
T4 |
360216 |
360116 |
0 |
0 |
T5 |
328804 |
328753 |
0 |
0 |
T6 |
34570 |
34464 |
0 |
0 |
T7 |
16769 |
16673 |
0 |
0 |
T8 |
197397 |
197309 |
0 |
0 |
T9 |
101157 |
101132 |
0 |
0 |
T10 |
571913 |
571778 |
0 |
0 |
RomTlOAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
266291347 |
0 |
0 |
T1 |
558704 |
558567 |
0 |
0 |
T2 |
234836 |
232602 |
0 |
0 |
T3 |
458142 |
458018 |
0 |
0 |
T4 |
360216 |
360116 |
0 |
0 |
T5 |
328804 |
328753 |
0 |
0 |
T6 |
34570 |
34464 |
0 |
0 |
T7 |
16769 |
16673 |
0 |
0 |
T8 |
197397 |
197309 |
0 |
0 |
T9 |
101157 |
101132 |
0 |
0 |
T10 |
571913 |
571778 |
0 |
0 |
RomTlODDataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
2358661 |
0 |
0 |
T1 |
558704 |
281 |
0 |
0 |
T2 |
234836 |
18 |
0 |
0 |
T3 |
458142 |
444 |
0 |
0 |
T4 |
360216 |
179 |
0 |
0 |
T5 |
328804 |
0 |
0 |
0 |
T6 |
34570 |
172 |
0 |
0 |
T7 |
16769 |
0 |
0 |
0 |
T8 |
197397 |
69 |
0 |
0 |
T9 |
101157 |
442 |
0 |
0 |
T10 |
571913 |
0 |
0 |
0 |
T11 |
0 |
130750 |
0 |
0 |
T12 |
0 |
433 |
0 |
0 |
T13 |
0 |
155 |
0 |
0 |
RomTlODDataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
266291347 |
0 |
0 |
T1 |
558704 |
558567 |
0 |
0 |
T2 |
234836 |
232602 |
0 |
0 |
T3 |
458142 |
458018 |
0 |
0 |
T4 |
360216 |
360116 |
0 |
0 |
T5 |
328804 |
328753 |
0 |
0 |
T6 |
34570 |
34464 |
0 |
0 |
T7 |
16769 |
16673 |
0 |
0 |
T8 |
197397 |
197309 |
0 |
0 |
T9 |
101157 |
101132 |
0 |
0 |
T10 |
571913 |
571778 |
0 |
0 |
RomTlODValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
266291347 |
0 |
0 |
T1 |
558704 |
558567 |
0 |
0 |
T2 |
234836 |
232602 |
0 |
0 |
T3 |
458142 |
458018 |
0 |
0 |
T4 |
360216 |
360116 |
0 |
0 |
T5 |
328804 |
328753 |
0 |
0 |
T6 |
34570 |
34464 |
0 |
0 |
T7 |
16769 |
16673 |
0 |
0 |
T8 |
197397 |
197309 |
0 |
0 |
T9 |
101157 |
101132 |
0 |
0 |
T10 |
571913 |
571778 |
0 |
0 |
StabilityChkKmac_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
246198491 |
0 |
0 |
T1 |
558704 |
557030 |
0 |
0 |
T2 |
234836 |
223626 |
0 |
0 |
T3 |
458142 |
456143 |
0 |
0 |
T4 |
360216 |
358888 |
0 |
0 |
T5 |
328804 |
328580 |
0 |
0 |
T6 |
34570 |
32750 |
0 |
0 |
T7 |
16769 |
16375 |
0 |
0 |
T8 |
197397 |
196368 |
0 |
0 |
T9 |
101157 |
100971 |
0 |
0 |
T10 |
571913 |
571457 |
0 |
0 |
StabilityChkkeymgr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
19968253 |
0 |
0 |
T1 |
558704 |
1415 |
0 |
0 |
T2 |
234836 |
8039 |
0 |
0 |
T3 |
458142 |
1766 |
0 |
0 |
T4 |
360216 |
1152 |
0 |
0 |
T5 |
328804 |
75 |
0 |
0 |
T6 |
34570 |
1668 |
0 |
0 |
T7 |
16769 |
275 |
0 |
0 |
T8 |
197397 |
909 |
0 |
0 |
T9 |
101157 |
1372 |
0 |
0 |
T10 |
571913 |
183 |
0 |
0 |
TlAccessChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
246322053 |
0 |
0 |
T1 |
558704 |
557150 |
0 |
0 |
T2 |
234836 |
224554 |
0 |
0 |
T3 |
458142 |
456250 |
0 |
0 |
T4 |
360216 |
358963 |
0 |
0 |
T5 |
328804 |
328677 |
0 |
0 |
T6 |
34570 |
32794 |
0 |
0 |
T7 |
16769 |
16397 |
0 |
0 |
T8 |
197397 |
196399 |
0 |
0 |
T9 |
101157 |
100994 |
0 |
0 |
T10 |
571913 |
571594 |
0 |
0 |
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
90 |
0 |
0 |
T17 |
33077 |
0 |
0 |
0 |
T28 |
267594 |
10 |
0 |
0 |
T30 |
0 |
20 |
0 |
0 |
T31 |
0 |
20 |
0 |
0 |
T33 |
0 |
20 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T35 |
493500 |
0 |
0 |
0 |
T36 |
71184 |
0 |
0 |
0 |
T37 |
644149 |
0 |
0 |
0 |
T38 |
396704 |
0 |
0 |
0 |
T39 |
17579 |
0 |
0 |
0 |
T40 |
204724 |
0 |
0 |
0 |
T41 |
377027 |
0 |
0 |
0 |
T42 |
164918 |
0 |
0 |
0 |
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
0 |
0 |
0 |
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
490 |
0 |
0 |
T2 |
234836 |
5 |
0 |
0 |
T3 |
458142 |
0 |
0 |
0 |
T4 |
360216 |
0 |
0 |
0 |
T5 |
328804 |
0 |
0 |
0 |
T6 |
34570 |
0 |
0 |
0 |
T7 |
16769 |
0 |
0 |
0 |
T8 |
197397 |
0 |
0 |
0 |
T9 |
101157 |
0 |
0 |
0 |
T10 |
571913 |
0 |
0 |
0 |
T11 |
194167 |
0 |
0 |
0 |
T26 |
0 |
15 |
0 |
0 |
T27 |
0 |
10 |
0 |
0 |
T28 |
0 |
10 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T30 |
0 |
20 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
T44 |
0 |
15 |
0 |
0 |
T45 |
0 |
11 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266466595 |
0 |
0 |
0 |