Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 42891 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 769215 1 T1 26 T3 6 T6 31



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 221410 1 T1 244 T3 6 T6 437
values[0x0] 289400 1 T21 46454 T22 89806 T23 6143
values[0x1] 301296 1 T21 48470 T22 93289 T23 6242



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 21270 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 790836 1 T1 161 T3 6 T6 259



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3265 1 T8 1 T85 1 T125 7
valid_sources[0x01] 3165 1 T1 1 T6 3 T9 1
valid_sources[0x02] 3106 1 T6 2 T14 3 T66 1
valid_sources[0x03] 3134 1 T6 2 T126 3 T87 4
valid_sources[0x04] 3167 1 T1 1 T6 2 T9 1
valid_sources[0x05] 3122 1 T1 3 T6 1 T14 1
valid_sources[0x06] 3226 1 T1 2 T6 5 T9 1
valid_sources[0x07] 3048 1 T6 1 T111 7 T127 1
valid_sources[0x08] 3174 1 T6 1 T14 1 T111 19
valid_sources[0x09] 3336 1 T1 1 T6 1 T16 1
valid_sources[0x0a] 3028 1 T1 1 T6 3 T66 2
valid_sources[0x0b] 3326 1 T1 1 T6 1 T66 1
valid_sources[0x0c] 3176 1 T127 1 T126 1 T18 2
valid_sources[0x0d] 3092 1 T8 1 T66 1 T127 1
valid_sources[0x0e] 3163 1 T1 2 T66 2 T127 1
valid_sources[0x0f] 3320 1 T1 3 T6 3 T9 1
valid_sources[0x10] 3235 1 T6 4 T9 1 T14 3
valid_sources[0x11] 3162 1 T6 2 T8 3 T127 1
valid_sources[0x12] 3236 1 T1 1 T6 1 T9 1
valid_sources[0x13] 3261 1 T8 3 T66 1 T127 1
valid_sources[0x14] 3157 1 T6 2 T16 1 T126 1
valid_sources[0x15] 3202 1 T1 1 T6 1 T12 2
valid_sources[0x16] 3294 1 T1 1 T6 1 T9 1
valid_sources[0x17] 3117 1 T6 1 T9 1 T14 1
valid_sources[0x18] 3226 1 T6 1 T14 7 T127 2
valid_sources[0x19] 3258 1 T6 4 T9 1 T14 5
valid_sources[0x1a] 3211 1 T1 1 T6 1 T11 4
valid_sources[0x1b] 3227 1 T1 3 T6 1 T11 4
valid_sources[0x1c] 3093 1 T1 1 T6 1 T16 1
valid_sources[0x1d] 3250 1 T1 3 T11 12 T127 3
valid_sources[0x1e] 3144 1 T1 2 T6 2 T8 2
valid_sources[0x1f] 3167 1 T6 2 T127 1 T85 2
valid_sources[0x20] 3325 1 T1 1 T6 1 T8 1
valid_sources[0x21] 3123 1 T1 3 T6 3 T14 2
valid_sources[0x22] 3134 1 T1 1 T6 4 T7 29
valid_sources[0x23] 3036 1 T1 3 T8 1 T14 1
valid_sources[0x24] 3188 1 T6 2 T11 2 T66 3
valid_sources[0x25] 3141 1 T6 2 T16 1 T127 1
valid_sources[0x26] 3217 1 T6 1 T16 1 T127 2
valid_sources[0x27] 2964 1 T1 1 T6 2 T14 2
valid_sources[0x28] 3026 1 T1 1 T6 1 T14 1
valid_sources[0x29] 3075 1 T14 2 T85 1 T128 1
valid_sources[0x2a] 3111 1 T6 3 T8 2 T127 1
valid_sources[0x2b] 3226 1 T6 1 T9 1 T66 1
valid_sources[0x2c] 3220 1 T12 4 T127 1 T126 1
valid_sources[0x2d] 2975 1 T1 2 T7 35 T8 1
valid_sources[0x2e] 3191 1 T1 2 T6 1 T16 1
valid_sources[0x2f] 3171 1 T6 2 T8 2 T111 17
valid_sources[0x30] 3218 1 T85 3 T126 4 T19 2
valid_sources[0x31] 3124 1 T1 2 T6 3 T66 1
valid_sources[0x32] 3129 1 T1 1 T6 3 T9 1
valid_sources[0x33] 3306 1 T1 2 T6 3 T8 2
valid_sources[0x34] 3488 1 T6 1 T14 2 T127 1
valid_sources[0x35] 3018 1 T1 1 T14 4 T66 1
valid_sources[0x36] 3200 1 T6 3 T16 1 T127 2
valid_sources[0x37] 3308 1 T6 3 T127 3 T126 1
valid_sources[0x38] 3213 1 T1 1 T6 1 T16 1
valid_sources[0x39] 3125 1 T1 1 T6 2 T9 1
valid_sources[0x3a] 3229 1 T1 2 T6 1 T8 2
valid_sources[0x3b] 3338 1 T6 5 T16 1 T127 2
valid_sources[0x3c] 3093 1 T1 1 T6 1 T9 1
valid_sources[0x3d] 3237 1 T6 1 T127 2 T126 1
valid_sources[0x3e] 3110 1 T1 3 T85 1 T19 1
valid_sources[0x3f] 3186 1 T6 5 T7 40 T14 1
valid_sources[0x40] 3398 1 T1 1 T6 3 T127 1
valid_sources[0x41] 3137 1 T6 1 T14 2 T66 1
valid_sources[0x42] 3073 1 T1 1 T6 2 T66 2
valid_sources[0x43] 3357 1 T1 1 T6 1 T16 1
valid_sources[0x44] 3108 1 T6 3 T16 1 T66 1
valid_sources[0x45] 3215 1 T1 3 T6 2 T8 3
valid_sources[0x46] 3273 1 T1 1 T6 1 T13 3
valid_sources[0x47] 3163 1 T6 4 T8 2 T14 6
valid_sources[0x48] 3164 1 T1 1 T9 1 T127 3
valid_sources[0x49] 3212 1 T6 1 T7 53 T16 1
valid_sources[0x4a] 3278 1 T1 2 T6 2 T87 3
valid_sources[0x4b] 3253 1 T6 1 T8 2 T127 2
valid_sources[0x4c] 3063 1 T14 1 T16 1 T66 1
valid_sources[0x4d] 3065 1 T6 4 T127 1 T126 1
valid_sources[0x4e] 3145 1 T1 1 T8 1 T111 19
valid_sources[0x4f] 3238 1 T8 1 T16 2 T127 2
valid_sources[0x50] 3193 1 T1 1 T6 2 T127 1
valid_sources[0x51] 3216 1 T1 1 T6 2 T9 1
valid_sources[0x52] 3146 1 T9 1 T126 2 T87 2
valid_sources[0x53] 3158 1 T1 1 T6 1 T16 1
valid_sources[0x54] 3094 1 T6 1 T9 2 T14 2
valid_sources[0x55] 3199 1 T6 1 T14 2 T111 16
valid_sources[0x56] 3296 1 T6 2 T9 2 T127 5
valid_sources[0x57] 3215 1 T1 1 T6 3 T8 1
valid_sources[0x58] 3117 1 T1 1 T6 1 T8 3
valid_sources[0x59] 3020 1 T6 3 T127 2 T126 1
valid_sources[0x5a] 3342 1 T1 1 T6 3 T33 2
valid_sources[0x5b] 3312 1 T1 3 T8 1 T127 1
valid_sources[0x5c] 3170 1 T127 2 T85 1 T126 1
valid_sources[0x5d] 3278 1 T1 3 T6 2 T16 1
valid_sources[0x5e] 3252 1 T1 3 T66 1 T87 3
valid_sources[0x5f] 3113 1 T6 2 T9 2 T11 1
valid_sources[0x60] 3222 1 T1 1 T6 1 T111 23
valid_sources[0x61] 3249 1 T1 1 T6 2 T127 2
valid_sources[0x62] 3151 1 T16 1 T66 1 T85 1
valid_sources[0x63] 3042 1 T1 1 T8 1 T66 1
valid_sources[0x64] 3183 1 T6 1 T9 1 T14 9
valid_sources[0x65] 3166 1 T66 1 T127 1 T85 1
valid_sources[0x66] 3230 1 T6 3 T14 2 T126 3
valid_sources[0x67] 3094 1 T1 1 T6 4 T66 1
valid_sources[0x68] 3330 1 T1 1 T6 2 T16 1
valid_sources[0x69] 3145 1 T6 4 T127 1 T126 1
valid_sources[0x6a] 3224 1 T1 1 T6 2 T127 1
valid_sources[0x6b] 3366 1 T9 2 T14 1 T126 2
valid_sources[0x6c] 3157 1 T6 2 T127 1 T125 1
valid_sources[0x6d] 3226 1 T6 1 T9 1 T16 1
valid_sources[0x6e] 3215 1 T1 1 T14 1 T15 1
valid_sources[0x6f] 3151 1 T6 4 T14 1 T66 1
valid_sources[0x70] 3141 1 T1 2 T6 1 T14 2
valid_sources[0x71] 3166 1 T6 3 T127 2 T85 1
valid_sources[0x72] 3200 1 T6 2 T9 1 T16 1
valid_sources[0x73] 3207 1 T6 5 T9 1 T127 3
valid_sources[0x74] 3111 1 T66 1 T127 3 T126 1
valid_sources[0x75] 3213 1 T1 2 T6 1 T14 4
valid_sources[0x76] 3110 1 T1 1 T6 3 T9 1
valid_sources[0x77] 3119 1 T1 1 T6 3 T14 1
valid_sources[0x78] 3041 1 T127 1 T85 1 T126 1
valid_sources[0x79] 3174 1 T1 5 T6 3 T9 1
valid_sources[0x7a] 3218 1 T1 1 T6 2 T9 1
valid_sources[0x7b] 3140 1 T1 4 T6 4 T14 1
valid_sources[0x7c] 3257 1 T8 1 T16 2 T66 1
valid_sources[0x7d] 3223 1 T1 2 T6 4 T8 2
valid_sources[0x7e] 3007 1 T1 1 T6 1 T9 1
valid_sources[0x7f] 3144 1 T1 1 T6 2 T87 1
valid_sources[0x80] 3075 1 T1 1 T6 3 T14 5



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 194577 1 T1 26 T3 6 T6 31
values[0x0] all_enables biggest_size 286795 1 T21 46072 T22 89084 T23 6092
values[0x1] all_enables biggest_size 287843 1 T21 46335 T22 89300 T23 5967


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 62811 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 601966 1 T3 16 T4 1 T7 50



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 168892 1 T2 1 T3 33 T4 1
values[0x0] 229965 1 T28 5 T17 7 T70 2
values[0x1] 265920 1 T5 1 T24 6 T28 8



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 29610 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 635167 1 T3 20 T4 1 T5 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2624 1 T126 3 T88 3 T129 1
valid_sources[0x01] 2293 1 T3 1 T85 1 T130 1
valid_sources[0x02] 2656 1 T129 1 T131 2 T39 4
valid_sources[0x03] 2121 1 T88 2 T132 2 T129 1
valid_sources[0x04] 2259 1 T3 1 T13 1 T66 1
valid_sources[0x05] 2929 1 T66 1 T126 1 T88 1
valid_sources[0x06] 2691 1 T133 1 T91 1 T21 278
valid_sources[0x07] 2260 1 T85 1 T126 1 T88 1
valid_sources[0x08] 2704 1 T112 1 T130 1 T134 1
valid_sources[0x09] 2320 1 T28 3 T91 1 T21 430
valid_sources[0x0a] 2636 1 T130 1 T87 5 T21 377
valid_sources[0x0b] 2631 1 T85 2 T130 1 T133 1
valid_sources[0x0c] 2254 1 T130 2 T70 1 T135 1
valid_sources[0x0d] 2919 1 T12 1 T88 1 T129 1
valid_sources[0x0e] 2673 1 T13 1 T126 2 T87 2
valid_sources[0x0f] 2603 1 T7 2 T20 1 T18 1
valid_sources[0x10] 2830 1 T66 4 T126 1 T130 1
valid_sources[0x11] 2469 1 T3 2 T126 1 T88 3
valid_sources[0x12] 2431 1 T66 2 T130 1 T30 2
valid_sources[0x13] 2220 1 T12 1 T48 4 T88 2
valid_sources[0x14] 2589 1 T16 3 T72 1 T50 1
valid_sources[0x15] 2439 1 T29 1 T89 1 T131 1
valid_sources[0x16] 1992 1 T130 1 T87 1 T91 2
valid_sources[0x17] 2479 1 T3 1 T130 2 T133 1
valid_sources[0x18] 3429 1 T112 1 T130 1 T87 4
valid_sources[0x19] 2705 1 T91 2 T41 4 T21 323
valid_sources[0x1a] 3001 1 T88 1 T21 354 T22 819
valid_sources[0x1b] 2450 1 T136 5 T88 1 T129 1
valid_sources[0x1c] 3138 1 T18 1 T129 1 T133 1
valid_sources[0x1d] 2741 1 T4 1 T18 1 T131 1
valid_sources[0x1e] 2918 1 T28 1 T129 4 T137 3
valid_sources[0x1f] 2388 1 T112 2 T89 1 T135 2
valid_sources[0x20] 2645 1 T28 2 T126 2 T48 6
valid_sources[0x21] 2491 1 T126 2 T130 4 T87 2
valid_sources[0x22] 2643 1 T126 1 T89 1 T129 1
valid_sources[0x23] 2269 1 T3 1 T137 3 T21 309
valid_sources[0x24] 2718 1 T85 1 T130 1 T91 1
valid_sources[0x25] 2565 1 T12 1 T128 12 T49 1
valid_sources[0x26] 3254 1 T85 1 T126 1 T18 1
valid_sources[0x27] 2707 1 T66 1 T130 1 T29 1
valid_sources[0x28] 2304 1 T29 1 T88 1 T129 1
valid_sources[0x29] 2291 1 T13 1 T66 3 T126 2
valid_sources[0x2a] 2724 1 T126 1 T130 2 T138 2
valid_sources[0x2b] 2311 1 T91 2 T21 481 T139 1
valid_sources[0x2c] 2165 1 T126 1 T130 2 T132 2
valid_sources[0x2d] 2639 1 T130 1 T87 1 T21 350
valid_sources[0x2e] 2357 1 T13 1 T12 1 T112 1
valid_sources[0x2f] 2850 1 T26 1 T129 2 T21 422
valid_sources[0x30] 2800 1 T13 1 T17 11 T140 1
valid_sources[0x31] 2421 1 T66 4 T87 1 T90 64
valid_sources[0x32] 2587 1 T72 2 T89 1 T129 4
valid_sources[0x33] 2500 1 T12 1 T34 1 T39 2
valid_sources[0x34] 2757 1 T89 1 T91 1 T21 440
valid_sources[0x35] 3343 1 T28 1 T66 7 T18 1
valid_sources[0x36] 2795 1 T88 1 T91 2 T141 1
valid_sources[0x37] 2738 1 T130 1 T88 1 T129 2
valid_sources[0x38] 2682 1 T129 2 T34 1 T39 3
valid_sources[0x39] 2647 1 T87 2 T89 1 T129 6
valid_sources[0x3a] 2443 1 T12 1 T126 1 T89 1
valid_sources[0x3b] 2694 1 T3 1 T130 1 T32 38
valid_sources[0x3c] 2491 1 T5 1 T126 1 T130 1
valid_sources[0x3d] 2016 1 T126 1 T128 9 T137 6
valid_sources[0x3e] 3222 1 T126 1 T18 1 T138 1
valid_sources[0x3f] 2887 1 T3 1 T91 1 T138 1
valid_sources[0x40] 2885 1 T3 1 T133 2 T21 353
valid_sources[0x41] 2304 1 T18 1 T142 1 T143 3
valid_sources[0x42] 2506 1 T87 2 T137 8 T135 1
valid_sources[0x43] 2755 1 T126 1 T21 352 T58 4
valid_sources[0x44] 2702 1 T130 1 T88 1 T129 3
valid_sources[0x45] 2171 1 T48 1 T72 3 T88 2
valid_sources[0x46] 2614 1 T91 2 T144 1 T21 503
valid_sources[0x47] 2925 1 T12 1 T129 1 T91 2
valid_sources[0x48] 3018 1 T145 32 T21 338 T22 829
valid_sources[0x49] 2619 1 T7 9 T13 1 T12 1
valid_sources[0x4a] 2767 1 T130 3 T87 6 T129 5
valid_sources[0x4b] 2646 1 T13 1 T12 1 T146 1
valid_sources[0x4c] 2778 1 T70 2 T133 1 T21 363
valid_sources[0x4d] 2563 1 T29 2 T128 8 T88 2
valid_sources[0x4e] 2186 1 T9 64 T66 2 T126 1
valid_sources[0x4f] 2205 1 T10 1 T66 1 T12 1
valid_sources[0x50] 1921 1 T3 1 T7 3 T66 4
valid_sources[0x51] 2843 1 T126 1 T87 2 T89 1
valid_sources[0x52] 2699 1 T133 3 T135 1 T147 2
valid_sources[0x53] 2492 1 T12 1 T126 1 T89 1
valid_sources[0x54] 3500 1 T13 1 T24 2 T12 1
valid_sources[0x55] 2604 1 T85 1 T130 2 T129 1
valid_sources[0x56] 2410 1 T13 3 T18 1 T75 2
valid_sources[0x57] 2431 1 T126 3 T86 3 T87 2
valid_sources[0x58] 2469 1 T66 4 T91 1 T21 406
valid_sources[0x59] 2712 1 T16 2 T112 1 T129 2
valid_sources[0x5a] 2714 1 T18 1 T88 4 T89 1
valid_sources[0x5b] 2671 1 T48 4 T29 1 T21 298
valid_sources[0x5c] 2502 1 T66 3 T130 1 T135 1
valid_sources[0x5d] 2606 1 T28 1 T21 388 T22 731
valid_sources[0x5e] 2348 1 T136 1 T89 1 T91 4
valid_sources[0x5f] 2493 1 T91 2 T135 1 T39 5
valid_sources[0x60] 2522 1 T3 1 T137 5 T138 1
valid_sources[0x61] 2216 1 T12 1 T87 4 T88 4
valid_sources[0x62] 2876 1 T133 1 T147 3 T39 1
valid_sources[0x63] 2480 1 T12 2 T18 1 T130 1
valid_sources[0x64] 2777 1 T129 1 T49 1 T148 1
valid_sources[0x65] 3209 1 T7 1 T87 1 T91 1
valid_sources[0x66] 2641 1 T2 1 T131 2 T149 1
valid_sources[0x67] 2447 1 T126 1 T89 1 T137 8
valid_sources[0x68] 2490 1 T12 1 T126 1 T29 2
valid_sources[0x69] 2257 1 T135 1 T21 431 T22 763
valid_sources[0x6a] 2506 1 T12 1 T88 2 T137 8
valid_sources[0x6b] 2341 1 T28 1 T126 1 T112 1
valid_sources[0x6c] 2535 1 T126 1 T87 2 T91 3
valid_sources[0x6d] 2771 1 T48 3 T130 2 T86 11
valid_sources[0x6e] 2546 1 T3 1 T66 1 T29 2
valid_sources[0x6f] 2621 1 T13 1 T129 2 T49 3
valid_sources[0x70] 2740 1 T3 1 T130 1 T87 2
valid_sources[0x71] 2726 1 T3 1 T13 1 T126 1
valid_sources[0x72] 2841 1 T21 362 T62 1 T22 809
valid_sources[0x73] 2141 1 T3 1 T87 1 T141 4
valid_sources[0x74] 2766 1 T129 1 T91 1 T40 3
valid_sources[0x75] 2419 1 T13 1 T126 1 T87 4
valid_sources[0x76] 2536 1 T18 1 T130 1 T72 1
valid_sources[0x77] 2530 1 T7 16 T13 1 T66 1
valid_sources[0x78] 2605 1 T7 1 T87 1 T88 1
valid_sources[0x79] 2378 1 T126 3 T89 2 T133 1
valid_sources[0x7a] 2689 1 T87 2 T129 3 T138 4
valid_sources[0x7b] 2392 1 T12 1 T87 2 T29 1
valid_sources[0x7c] 2513 1 T13 2 T16 1 T29 1
valid_sources[0x7d] 3104 1 T12 1 T135 1 T42 1
valid_sources[0x7e] 2890 1 T16 3 T126 1 T112 2
valid_sources[0x7f] 2811 1 T66 3 T112 1 T18 1
valid_sources[0x80] 2386 1 T86 3 T150 1 T50 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 152592 1 T3 16 T4 1 T7 50
values[0x0] all_enables biggest_size 224769 1 T28 3 T17 1 T70 1
values[0x1] all_enables biggest_size 224605 1 T24 1 T17 1 T70 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%