Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 96.88 91.85 97.72 100.00 98.28 97.45 98.37


Total test records in report: 455
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T301 /workspace/coverage/default/24.rom_ctrl_alert_test.879404559 Jun 06 01:14:48 PM PDT 24 Jun 06 01:15:19 PM PDT 24 3294452154 ps
T302 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3247951223 Jun 06 01:15:46 PM PDT 24 Jun 06 01:16:14 PM PDT 24 11317666607 ps
T303 /workspace/coverage/default/34.rom_ctrl_alert_test.382245991 Jun 06 01:15:17 PM PDT 24 Jun 06 01:15:28 PM PDT 24 497144292 ps
T304 /workspace/coverage/default/23.rom_ctrl_alert_test.3532259642 Jun 06 01:14:49 PM PDT 24 Jun 06 01:15:00 PM PDT 24 1121407523 ps
T305 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.750089035 Jun 06 01:15:16 PM PDT 24 Jun 06 01:15:37 PM PDT 24 675063040 ps
T306 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2000359540 Jun 06 01:14:13 PM PDT 24 Jun 06 01:28:03 PM PDT 24 308749506734 ps
T307 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1510535567 Jun 06 01:15:39 PM PDT 24 Jun 06 01:15:50 PM PDT 24 685345372 ps
T308 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3939398772 Jun 06 01:15:48 PM PDT 24 Jun 06 01:26:22 PM PDT 24 133547053401 ps
T28 /workspace/coverage/default/1.rom_ctrl_sec_cm.4096357168 Jun 06 01:14:04 PM PDT 24 Jun 06 01:17:59 PM PDT 24 7949110234 ps
T52 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2331473244 Jun 06 01:14:22 PM PDT 24 Jun 06 03:56:37 PM PDT 24 68779189806 ps
T309 /workspace/coverage/default/29.rom_ctrl_stress_all.2253430828 Jun 06 01:14:59 PM PDT 24 Jun 06 01:15:45 PM PDT 24 4301889471 ps
T310 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.275355788 Jun 06 01:14:04 PM PDT 24 Jun 06 01:15:06 PM PDT 24 30702706777 ps
T311 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3190702901 Jun 06 01:14:21 PM PDT 24 Jun 06 01:15:30 PM PDT 24 16389354474 ps
T312 /workspace/coverage/default/22.rom_ctrl_alert_test.726797320 Jun 06 01:14:38 PM PDT 24 Jun 06 01:14:52 PM PDT 24 686750986 ps
T313 /workspace/coverage/default/12.rom_ctrl_smoke.47696533 Jun 06 01:14:21 PM PDT 24 Jun 06 01:15:17 PM PDT 24 4706104224 ps
T314 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1405651332 Jun 06 01:15:44 PM PDT 24 Jun 06 01:16:04 PM PDT 24 6205979178 ps
T315 /workspace/coverage/default/37.rom_ctrl_smoke.2874019833 Jun 06 01:15:26 PM PDT 24 Jun 06 01:15:54 PM PDT 24 2036301168 ps
T316 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.950771153 Jun 06 01:14:03 PM PDT 24 Jun 06 01:25:01 PM PDT 24 134435359293 ps
T317 /workspace/coverage/default/2.rom_ctrl_smoke.332887903 Jun 06 01:14:05 PM PDT 24 Jun 06 01:14:59 PM PDT 24 24988642968 ps
T318 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2301563398 Jun 06 01:14:24 PM PDT 24 Jun 06 01:18:10 PM PDT 24 4483063197 ps
T319 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2380230296 Jun 06 01:14:33 PM PDT 24 Jun 06 01:15:08 PM PDT 24 10141164702 ps
T320 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.856938559 Jun 06 01:15:36 PM PDT 24 Jun 06 01:22:45 PM PDT 24 42856131711 ps
T321 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.449999909 Jun 06 01:15:35 PM PDT 24 Jun 06 01:16:41 PM PDT 24 7467842065 ps
T322 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3299415821 Jun 06 01:14:29 PM PDT 24 Jun 06 01:15:38 PM PDT 24 8709674762 ps
T323 /workspace/coverage/default/10.rom_ctrl_alert_test.2638116761 Jun 06 01:14:21 PM PDT 24 Jun 06 01:14:30 PM PDT 24 167560991 ps
T29 /workspace/coverage/default/2.rom_ctrl_sec_cm.2288556191 Jun 06 01:14:05 PM PDT 24 Jun 06 01:18:02 PM PDT 24 2021790396 ps
T324 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.779614455 Jun 06 01:14:49 PM PDT 24 Jun 06 01:19:15 PM PDT 24 68253613719 ps
T325 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1801210387 Jun 06 01:14:58 PM PDT 24 Jun 06 01:37:54 PM PDT 24 945089473969 ps
T326 /workspace/coverage/default/22.rom_ctrl_smoke.4161747503 Jun 06 01:14:38 PM PDT 24 Jun 06 01:14:59 PM PDT 24 360302544 ps
T327 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3534951319 Jun 06 01:14:30 PM PDT 24 Jun 06 01:14:43 PM PDT 24 184320544 ps
T328 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2374620561 Jun 06 01:14:48 PM PDT 24 Jun 06 01:15:25 PM PDT 24 17506525941 ps
T329 /workspace/coverage/default/44.rom_ctrl_stress_all.2506836261 Jun 06 01:15:46 PM PDT 24 Jun 06 01:18:21 PM PDT 24 60664531801 ps
T330 /workspace/coverage/default/17.rom_ctrl_alert_test.1488825283 Jun 06 01:14:34 PM PDT 24 Jun 06 01:15:00 PM PDT 24 2806446811 ps
T331 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1496790823 Jun 06 01:15:46 PM PDT 24 Jun 06 01:16:07 PM PDT 24 1835457494 ps
T332 /workspace/coverage/default/46.rom_ctrl_alert_test.2688071850 Jun 06 01:15:48 PM PDT 24 Jun 06 01:16:21 PM PDT 24 4341262379 ps
T333 /workspace/coverage/default/38.rom_ctrl_stress_all.3951713240 Jun 06 01:15:26 PM PDT 24 Jun 06 01:17:47 PM PDT 24 41464562651 ps
T334 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1807717462 Jun 06 01:15:47 PM PDT 24 Jun 06 01:16:07 PM PDT 24 1408070544 ps
T335 /workspace/coverage/default/28.rom_ctrl_stress_all.3750733753 Jun 06 01:14:58 PM PDT 24 Jun 06 01:15:30 PM PDT 24 2549975198 ps
T336 /workspace/coverage/default/42.rom_ctrl_stress_all.1480567621 Jun 06 01:15:37 PM PDT 24 Jun 06 01:16:42 PM PDT 24 14501013986 ps
T337 /workspace/coverage/default/33.rom_ctrl_stress_all.4292026785 Jun 06 01:15:06 PM PDT 24 Jun 06 01:17:19 PM PDT 24 43932910613 ps
T338 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2767595580 Jun 06 01:15:26 PM PDT 24 Jun 06 01:24:20 PM PDT 24 40706362215 ps
T339 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3205402152 Jun 06 01:15:29 PM PDT 24 Jun 06 01:15:52 PM PDT 24 4138943634 ps
T53 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1599671078 Jun 06 01:14:23 PM PDT 24 Jun 06 02:02:37 PM PDT 24 553604813455 ps
T340 /workspace/coverage/default/40.rom_ctrl_stress_all.439495407 Jun 06 01:15:36 PM PDT 24 Jun 06 01:20:34 PM PDT 24 141778452734 ps
T341 /workspace/coverage/default/30.rom_ctrl_stress_all.117981996 Jun 06 01:14:58 PM PDT 24 Jun 06 01:18:02 PM PDT 24 75896058239 ps
T342 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.370466353 Jun 06 01:14:34 PM PDT 24 Jun 06 01:15:05 PM PDT 24 3505351351 ps
T343 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3810483777 Jun 06 01:15:25 PM PDT 24 Jun 06 01:19:55 PM PDT 24 31493220558 ps
T344 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3114769494 Jun 06 01:14:12 PM PDT 24 Jun 06 01:14:31 PM PDT 24 1055693387 ps
T345 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3176508114 Jun 06 01:15:06 PM PDT 24 Jun 06 01:15:17 PM PDT 24 483471406 ps
T346 /workspace/coverage/default/41.rom_ctrl_alert_test.4100361085 Jun 06 01:15:37 PM PDT 24 Jun 06 01:16:12 PM PDT 24 17780504225 ps
T347 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2923852557 Jun 06 01:14:23 PM PDT 24 Jun 06 01:14:34 PM PDT 24 183539355 ps
T348 /workspace/coverage/default/8.rom_ctrl_smoke.2669099980 Jun 06 01:14:09 PM PDT 24 Jun 06 01:15:30 PM PDT 24 8525041248 ps
T349 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3192312748 Jun 06 01:14:26 PM PDT 24 Jun 06 01:15:01 PM PDT 24 4176883642 ps
T350 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2750884411 Jun 06 01:15:44 PM PDT 24 Jun 06 01:16:46 PM PDT 24 7012337883 ps
T351 /workspace/coverage/default/32.rom_ctrl_alert_test.1672053909 Jun 06 01:15:09 PM PDT 24 Jun 06 01:15:44 PM PDT 24 16421956505 ps
T352 /workspace/coverage/default/24.rom_ctrl_stress_all.1897526834 Jun 06 01:14:50 PM PDT 24 Jun 06 01:15:27 PM PDT 24 16395221325 ps
T353 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.837603765 Jun 06 01:15:28 PM PDT 24 Jun 06 01:16:23 PM PDT 24 23319972201 ps
T354 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.724087087 Jun 06 01:15:16 PM PDT 24 Jun 06 01:16:08 PM PDT 24 10456060391 ps
T355 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3404724151 Jun 06 01:14:58 PM PDT 24 Jun 06 01:15:32 PM PDT 24 4103340661 ps
T356 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1746706041 Jun 06 01:14:48 PM PDT 24 Jun 06 01:22:49 PM PDT 24 204947811263 ps
T67 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3287124074 Jun 06 02:36:14 PM PDT 24 Jun 06 02:36:26 PM PDT 24 650551104 ps
T68 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3500849910 Jun 06 02:35:16 PM PDT 24 Jun 06 02:36:12 PM PDT 24 2016867802 ps
T69 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3110214033 Jun 06 02:36:46 PM PDT 24 Jun 06 02:37:14 PM PDT 24 6639105986 ps
T117 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1875311618 Jun 06 02:35:31 PM PDT 24 Jun 06 02:36:02 PM PDT 24 3870837282 ps
T118 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1183873456 Jun 06 02:36:33 PM PDT 24 Jun 06 02:37:04 PM PDT 24 2864456382 ps
T119 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.232838413 Jun 06 02:35:14 PM PDT 24 Jun 06 02:35:42 PM PDT 24 10916978170 ps
T81 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2911869404 Jun 06 02:35:31 PM PDT 24 Jun 06 02:36:05 PM PDT 24 19543880242 ps
T120 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.222877937 Jun 06 02:36:34 PM PDT 24 Jun 06 02:37:00 PM PDT 24 18064272907 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1168633283 Jun 06 02:35:32 PM PDT 24 Jun 06 02:35:54 PM PDT 24 9173580832 ps
T54 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3642214069 Jun 06 02:36:33 PM PDT 24 Jun 06 02:39:22 PM PDT 24 5697869998 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.369965550 Jun 06 02:35:44 PM PDT 24 Jun 06 02:36:16 PM PDT 24 14447592597 ps
T357 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1178690221 Jun 06 02:35:17 PM PDT 24 Jun 06 02:35:47 PM PDT 24 12391657966 ps
T121 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3292068005 Jun 06 02:36:25 PM PDT 24 Jun 06 02:37:22 PM PDT 24 4305848551 ps
T55 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2591861607 Jun 06 02:36:43 PM PDT 24 Jun 06 02:38:09 PM PDT 24 3472124014 ps
T358 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2896755867 Jun 06 02:35:34 PM PDT 24 Jun 06 02:35:58 PM PDT 24 23198427427 ps
T359 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2764188497 Jun 06 02:35:40 PM PDT 24 Jun 06 02:35:49 PM PDT 24 167719589 ps
T56 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1880087595 Jun 06 02:36:20 PM PDT 24 Jun 06 02:37:59 PM PDT 24 43247281780 ps
T80 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3666105402 Jun 06 02:36:30 PM PDT 24 Jun 06 02:38:10 PM PDT 24 14981145049 ps
T77 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1915749880 Jun 06 02:36:25 PM PDT 24 Jun 06 02:36:57 PM PDT 24 15411110335 ps
T78 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4207789262 Jun 06 02:36:43 PM PDT 24 Jun 06 02:37:07 PM PDT 24 10400771622 ps
T360 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2187195665 Jun 06 02:35:20 PM PDT 24 Jun 06 02:35:47 PM PDT 24 3022923517 ps
T125 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1810263284 Jun 06 02:36:28 PM PDT 24 Jun 06 02:37:57 PM PDT 24 8496248817 ps
T79 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4055788277 Jun 06 02:36:08 PM PDT 24 Jun 06 02:36:37 PM PDT 24 12312410183 ps
T84 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1405092443 Jun 06 02:36:38 PM PDT 24 Jun 06 02:37:16 PM PDT 24 848579528 ps
T361 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2866668570 Jun 06 02:35:49 PM PDT 24 Jun 06 02:36:13 PM PDT 24 9235120975 ps
T362 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1446128838 Jun 06 02:36:34 PM PDT 24 Jun 06 02:36:57 PM PDT 24 2264096928 ps
T363 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2555358958 Jun 06 02:36:17 PM PDT 24 Jun 06 02:36:41 PM PDT 24 5149293191 ps
T364 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2679234233 Jun 06 02:36:26 PM PDT 24 Jun 06 02:36:54 PM PDT 24 12857727398 ps
T85 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3678984621 Jun 06 02:36:15 PM PDT 24 Jun 06 02:36:24 PM PDT 24 660358889 ps
T86 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3671813165 Jun 06 02:36:44 PM PDT 24 Jun 06 02:38:13 PM PDT 24 8582469553 ps
T365 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.257573217 Jun 06 02:36:06 PM PDT 24 Jun 06 02:36:40 PM PDT 24 4127896466 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3290045597 Jun 06 02:35:32 PM PDT 24 Jun 06 02:35:59 PM PDT 24 3466422378 ps
T367 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1477592138 Jun 06 02:36:08 PM PDT 24 Jun 06 02:36:17 PM PDT 24 174550063 ps
T87 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3308991702 Jun 06 02:36:45 PM PDT 24 Jun 06 02:37:08 PM PDT 24 8602763478 ps
T88 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.936757070 Jun 06 02:35:42 PM PDT 24 Jun 06 02:35:52 PM PDT 24 338546507 ps
T368 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4019631646 Jun 06 02:36:34 PM PDT 24 Jun 06 02:37:02 PM PDT 24 11748544455 ps
T369 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1968460616 Jun 06 02:36:36 PM PDT 24 Jun 06 02:36:58 PM PDT 24 4304995953 ps
T370 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2508987247 Jun 06 02:35:32 PM PDT 24 Jun 06 02:35:52 PM PDT 24 3884945731 ps
T371 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.95576645 Jun 06 02:36:20 PM PDT 24 Jun 06 02:36:49 PM PDT 24 3478726143 ps
T372 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1859631290 Jun 06 02:36:16 PM PDT 24 Jun 06 02:36:46 PM PDT 24 3973684798 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2207387488 Jun 06 02:35:22 PM PDT 24 Jun 06 02:35:52 PM PDT 24 7199032627 ps
T374 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.494713822 Jun 06 02:35:22 PM PDT 24 Jun 06 02:35:41 PM PDT 24 5976387338 ps
T375 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.943908546 Jun 06 02:36:36 PM PDT 24 Jun 06 02:37:03 PM PDT 24 11791247732 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2552233163 Jun 06 02:35:40 PM PDT 24 Jun 06 02:36:05 PM PDT 24 2798189500 ps
T95 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2585233299 Jun 06 02:35:49 PM PDT 24 Jun 06 02:36:28 PM PDT 24 7353113114 ps
T377 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2814066633 Jun 06 02:35:58 PM PDT 24 Jun 06 02:36:34 PM PDT 24 28013327826 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3026392513 Jun 06 02:35:49 PM PDT 24 Jun 06 02:36:03 PM PDT 24 699590508 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2652632546 Jun 06 02:35:49 PM PDT 24 Jun 06 02:36:17 PM PDT 24 2360897826 ps
T380 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.304383182 Jun 06 02:36:26 PM PDT 24 Jun 06 02:36:39 PM PDT 24 362899900 ps
T127 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3704275211 Jun 06 02:35:57 PM PDT 24 Jun 06 02:38:47 PM PDT 24 6260016947 ps
T130 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3684645230 Jun 06 02:35:24 PM PDT 24 Jun 06 02:37:03 PM PDT 24 11718846446 ps
T381 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2749067718 Jun 06 02:36:06 PM PDT 24 Jun 06 02:38:05 PM PDT 24 14471585630 ps
T382 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.452178120 Jun 06 02:35:57 PM PDT 24 Jun 06 02:36:18 PM PDT 24 9309084024 ps
T383 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3237735689 Jun 06 02:36:25 PM PDT 24 Jun 06 02:36:49 PM PDT 24 1818084971 ps
T384 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2239616864 Jun 06 02:35:57 PM PDT 24 Jun 06 02:36:28 PM PDT 24 11607349308 ps
T385 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2151157217 Jun 06 02:36:25 PM PDT 24 Jun 06 02:36:59 PM PDT 24 7666307689 ps
T386 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.40260818 Jun 06 02:35:48 PM PDT 24 Jun 06 02:35:58 PM PDT 24 169397075 ps
T129 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3814673178 Jun 06 02:36:06 PM PDT 24 Jun 06 02:38:42 PM PDT 24 1292986139 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1924756747 Jun 06 02:36:32 PM PDT 24 Jun 06 02:37:01 PM PDT 24 18409964973 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.183174904 Jun 06 02:35:33 PM PDT 24 Jun 06 02:35:46 PM PDT 24 688744888 ps
T389 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1404544926 Jun 06 02:36:44 PM PDT 24 Jun 06 02:37:13 PM PDT 24 10064111028 ps
T390 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.856869459 Jun 06 02:36:43 PM PDT 24 Jun 06 02:36:53 PM PDT 24 186612011 ps
T391 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2461032883 Jun 06 02:36:16 PM PDT 24 Jun 06 02:36:42 PM PDT 24 20784729432 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.851556737 Jun 06 02:36:14 PM PDT 24 Jun 06 02:36:30 PM PDT 24 1415156949 ps
T393 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3072952180 Jun 06 02:36:15 PM PDT 24 Jun 06 02:36:53 PM PDT 24 17039408592 ps
T96 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1547542586 Jun 06 02:35:47 PM PDT 24 Jun 06 02:36:18 PM PDT 24 14336770578 ps
T394 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2125244782 Jun 06 02:36:08 PM PDT 24 Jun 06 02:37:51 PM PDT 24 4324123013 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2061056103 Jun 06 02:35:23 PM PDT 24 Jun 06 02:35:49 PM PDT 24 42760307307 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3848964966 Jun 06 02:35:15 PM PDT 24 Jun 06 02:35:46 PM PDT 24 7048608209 ps
T126 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.287844850 Jun 06 02:36:44 PM PDT 24 Jun 06 02:39:22 PM PDT 24 1702769755 ps
T397 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1971854373 Jun 06 02:36:32 PM PDT 24 Jun 06 02:36:42 PM PDT 24 435928790 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3632520709 Jun 06 02:35:24 PM PDT 24 Jun 06 02:35:51 PM PDT 24 3028143978 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.531544304 Jun 06 02:35:24 PM PDT 24 Jun 06 02:35:53 PM PDT 24 5554573406 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.75423959 Jun 06 02:35:33 PM PDT 24 Jun 06 02:35:51 PM PDT 24 2896281577 ps
T401 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1480117303 Jun 06 02:36:44 PM PDT 24 Jun 06 02:37:42 PM PDT 24 1084034206 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3918163983 Jun 06 02:35:34 PM PDT 24 Jun 06 02:36:01 PM PDT 24 5015550733 ps
T403 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2291839659 Jun 06 02:36:34 PM PDT 24 Jun 06 02:39:12 PM PDT 24 66999274362 ps
T404 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.381751574 Jun 06 02:36:33 PM PDT 24 Jun 06 02:37:04 PM PDT 24 70136287164 ps
T97 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3823486920 Jun 06 02:35:29 PM PDT 24 Jun 06 02:37:57 PM PDT 24 68545215569 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2985814647 Jun 06 02:35:41 PM PDT 24 Jun 06 02:36:14 PM PDT 24 15730482944 ps
T406 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.452931783 Jun 06 02:36:06 PM PDT 24 Jun 06 02:36:37 PM PDT 24 51214067062 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3743325489 Jun 06 02:35:24 PM PDT 24 Jun 06 02:35:48 PM PDT 24 9123021131 ps
T408 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1785800315 Jun 06 02:35:13 PM PDT 24 Jun 06 02:35:45 PM PDT 24 68767938481 ps
T409 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1221703228 Jun 06 02:36:34 PM PDT 24 Jun 06 02:38:12 PM PDT 24 28109181964 ps
T410 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2304762240 Jun 06 02:35:49 PM PDT 24 Jun 06 02:36:19 PM PDT 24 6968161095 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3275431687 Jun 06 02:35:39 PM PDT 24 Jun 06 02:36:03 PM PDT 24 2493835171 ps
T412 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.876294492 Jun 06 02:36:33 PM PDT 24 Jun 06 02:37:07 PM PDT 24 24183979555 ps
T413 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.23248455 Jun 06 02:36:33 PM PDT 24 Jun 06 02:37:03 PM PDT 24 11865818373 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.603019597 Jun 06 02:35:40 PM PDT 24 Jun 06 02:38:46 PM PDT 24 92494596770 ps
T414 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.151276389 Jun 06 02:36:05 PM PDT 24 Jun 06 02:36:45 PM PDT 24 5719252446 ps
T415 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3578132381 Jun 06 02:36:33 PM PDT 24 Jun 06 02:36:56 PM PDT 24 8608116359 ps
T99 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.636131316 Jun 06 02:36:35 PM PDT 24 Jun 06 02:37:57 PM PDT 24 3676301554 ps
T100 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3380584627 Jun 06 02:35:41 PM PDT 24 Jun 06 02:38:40 PM PDT 24 44208267443 ps
T134 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4072956339 Jun 06 02:35:23 PM PDT 24 Jun 06 02:37:06 PM PDT 24 8731004063 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1616692756 Jun 06 02:35:51 PM PDT 24 Jun 06 02:36:09 PM PDT 24 1362484459 ps
T417 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2506352348 Jun 06 02:36:34 PM PDT 24 Jun 06 02:36:45 PM PDT 24 988598940 ps
T418 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1361644341 Jun 06 02:36:24 PM PDT 24 Jun 06 02:36:52 PM PDT 24 2839815603 ps
T419 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2069460194 Jun 06 02:36:08 PM PDT 24 Jun 06 02:36:29 PM PDT 24 7012836366 ps
T420 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2481833342 Jun 06 02:36:14 PM PDT 24 Jun 06 02:36:24 PM PDT 24 172751663 ps
T421 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1426823620 Jun 06 02:36:43 PM PDT 24 Jun 06 02:37:06 PM PDT 24 2456457825 ps
T105 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3563042415 Jun 06 02:36:27 PM PDT 24 Jun 06 02:37:25 PM PDT 24 4285275599 ps
T422 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.778349555 Jun 06 02:35:44 PM PDT 24 Jun 06 02:36:05 PM PDT 24 6920208512 ps
T423 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.233730280 Jun 06 02:36:35 PM PDT 24 Jun 06 02:37:07 PM PDT 24 7821530635 ps
T128 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.475864873 Jun 06 02:36:33 PM PDT 24 Jun 06 02:39:19 PM PDT 24 5134875779 ps
T101 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2821488717 Jun 06 02:36:16 PM PDT 24 Jun 06 02:39:38 PM PDT 24 24885368464 ps
T131 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3606993911 Jun 06 02:36:32 PM PDT 24 Jun 06 02:38:13 PM PDT 24 17866082867 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.120318338 Jun 06 02:35:14 PM PDT 24 Jun 06 02:35:27 PM PDT 24 689513730 ps
T425 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.748394303 Jun 06 02:36:25 PM PDT 24 Jun 06 02:36:47 PM PDT 24 4276505228 ps
T426 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3945989246 Jun 06 02:36:25 PM PDT 24 Jun 06 02:36:58 PM PDT 24 15381322618 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.626145436 Jun 06 02:35:52 PM PDT 24 Jun 06 02:36:29 PM PDT 24 3738529105 ps
T428 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3655498927 Jun 06 02:35:58 PM PDT 24 Jun 06 02:36:19 PM PDT 24 1829665613 ps
T429 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3920414553 Jun 06 02:36:33 PM PDT 24 Jun 06 02:36:49 PM PDT 24 497222043 ps
T430 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1456757140 Jun 06 02:35:22 PM PDT 24 Jun 06 02:36:00 PM PDT 24 4192098337 ps
T102 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2059011376 Jun 06 02:36:15 PM PDT 24 Jun 06 02:38:25 PM PDT 24 12330718982 ps
T431 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.377557341 Jun 06 02:36:45 PM PDT 24 Jun 06 02:37:14 PM PDT 24 2790490465 ps
T432 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4239918809 Jun 06 02:36:44 PM PDT 24 Jun 06 02:37:08 PM PDT 24 18300276288 ps
T433 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.95271115 Jun 06 02:36:34 PM PDT 24 Jun 06 02:36:45 PM PDT 24 609213586 ps
T434 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2579517153 Jun 06 02:35:43 PM PDT 24 Jun 06 02:36:07 PM PDT 24 7848769536 ps
T435 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1574484103 Jun 06 02:35:58 PM PDT 24 Jun 06 02:36:34 PM PDT 24 4455375515 ps
T436 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3454816243 Jun 06 02:36:38 PM PDT 24 Jun 06 02:37:58 PM PDT 24 964387719 ps
T437 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1273709527 Jun 06 02:36:24 PM PDT 24 Jun 06 02:37:42 PM PDT 24 3058985728 ps
T133 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3608036626 Jun 06 02:36:16 PM PDT 24 Jun 06 02:38:59 PM PDT 24 7694138559 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3308538603 Jun 06 02:35:29 PM PDT 24 Jun 06 02:35:39 PM PDT 24 170716018 ps
T439 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3705585787 Jun 06 02:36:32 PM PDT 24 Jun 06 02:37:03 PM PDT 24 3171262576 ps
T440 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3358434528 Jun 06 02:36:34 PM PDT 24 Jun 06 02:37:02 PM PDT 24 6541249519 ps
T441 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.378034654 Jun 06 02:35:14 PM PDT 24 Jun 06 02:37:57 PM PDT 24 18470602160 ps
T442 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2740437954 Jun 06 02:36:06 PM PDT 24 Jun 06 02:36:29 PM PDT 24 4579253480 ps
T106 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1349687836 Jun 06 02:35:57 PM PDT 24 Jun 06 02:37:01 PM PDT 24 17287238334 ps
T443 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.971479779 Jun 06 02:35:33 PM PDT 24 Jun 06 02:37:14 PM PDT 24 72776228592 ps
T444 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2494497503 Jun 06 02:36:33 PM PDT 24 Jun 06 02:36:42 PM PDT 24 176291723 ps
T445 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.238209710 Jun 06 02:35:57 PM PDT 24 Jun 06 02:36:16 PM PDT 24 2984556487 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3826973270 Jun 06 02:35:14 PM PDT 24 Jun 06 02:35:40 PM PDT 24 10553433491 ps
T447 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2145597077 Jun 06 02:35:23 PM PDT 24 Jun 06 02:35:32 PM PDT 24 167320886 ps
T448 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2026198179 Jun 06 02:36:21 PM PDT 24 Jun 06 02:36:40 PM PDT 24 776900743 ps
T103 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2776880211 Jun 06 02:36:32 PM PDT 24 Jun 06 02:38:24 PM PDT 24 13409909425 ps
T449 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2959954569 Jun 06 02:36:26 PM PDT 24 Jun 06 02:36:35 PM PDT 24 752006007 ps
T104 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3018685330 Jun 06 02:35:56 PM PDT 24 Jun 06 02:36:05 PM PDT 24 179793275 ps
T135 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2917285688 Jun 06 02:35:43 PM PDT 24 Jun 06 02:38:29 PM PDT 24 5506532155 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.428842383 Jun 06 02:35:29 PM PDT 24 Jun 06 02:35:47 PM PDT 24 5261654892 ps
T451 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.924923412 Jun 06 02:36:07 PM PDT 24 Jun 06 02:36:16 PM PDT 24 660468222 ps
T452 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2173471080 Jun 06 02:35:57 PM PDT 24 Jun 06 02:37:37 PM PDT 24 95626616375 ps
T453 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1120710928 Jun 06 02:35:59 PM PDT 24 Jun 06 02:37:21 PM PDT 24 957574621 ps
T132 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3080662359 Jun 06 02:35:50 PM PDT 24 Jun 06 02:38:42 PM PDT 24 14703493428 ps
T454 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4096686535 Jun 06 02:36:08 PM PDT 24 Jun 06 02:36:20 PM PDT 24 433618915 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2218524274 Jun 06 02:35:15 PM PDT 24 Jun 06 02:35:38 PM PDT 24 2317506696 ps

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1981195655
Short name T6
Test name
Test status
Simulation time 44103231463 ps
CPU time 460.25 seconds
Started Jun 06 01:15:37 PM PDT 24
Finished Jun 06 01:23:18 PM PDT 24
Peak memory 227848 kb
Host smart-fa67f3ce-bc52-4735-b75f-b8fb4ffe80dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981195655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1981195655
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.4222355429
Short name T17
Test name
Test status
Simulation time 13997457469 ps
CPU time 982.37 seconds
Started Jun 06 01:14:47 PM PDT 24
Finished Jun 06 01:31:12 PM PDT 24
Peak memory 227648 kb
Host smart-bfc9c030-a029-4d25-8485-a47dded95b9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222355429 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.4222355429
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.435166149
Short name T2
Test name
Test status
Simulation time 5413071957 ps
CPU time 25.37 seconds
Started Jun 06 01:14:04 PM PDT 24
Finished Jun 06 01:14:30 PM PDT 24
Peak memory 219040 kb
Host smart-de61b183-875d-4660-96d8-39e712e3f1b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435166149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.435166149
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1035072136
Short name T11
Test name
Test status
Simulation time 36727586307 ps
CPU time 484.88 seconds
Started Jun 06 01:14:20 PM PDT 24
Finished Jun 06 01:22:25 PM PDT 24
Peak memory 237680 kb
Host smart-d54d92cb-a304-436f-acba-f1ce701b22b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035072136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1035072136
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1046284538
Short name T49
Test name
Test status
Simulation time 9305834946 ps
CPU time 24.05 seconds
Started Jun 06 01:14:41 PM PDT 24
Finished Jun 06 01:15:06 PM PDT 24
Peak memory 219108 kb
Host smart-e4bada51-3781-40be-9b01-8c70086a325d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046284538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1046284538
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3642214069
Short name T54
Test name
Test status
Simulation time 5697869998 ps
CPU time 167.19 seconds
Started Jun 06 02:36:33 PM PDT 24
Finished Jun 06 02:39:22 PM PDT 24
Peak memory 219388 kb
Host smart-029917fb-8e62-4289-92a3-2a4a2c3bf1d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642214069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3642214069
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2322051250
Short name T73
Test name
Test status
Simulation time 3740448224 ps
CPU time 30.06 seconds
Started Jun 06 01:14:38 PM PDT 24
Finished Jun 06 01:15:10 PM PDT 24
Peak memory 216808 kb
Host smart-503916bd-ca6b-4e0c-b81f-5dba0625bea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322051250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2322051250
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.505626311
Short name T146
Test name
Test status
Simulation time 14095994790 ps
CPU time 130.39 seconds
Started Jun 06 01:15:48 PM PDT 24
Finished Jun 06 01:18:00 PM PDT 24
Peak memory 220528 kb
Host smart-669afb13-3c58-448d-acd7-ec091d137310
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505626311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.505626311
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.774131328
Short name T23
Test name
Test status
Simulation time 13504706844 ps
CPU time 137.29 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:16:32 PM PDT 24
Peak memory 235208 kb
Host smart-096e5723-a188-4ee8-891c-b0560970dc9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774131328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.774131328
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3704275211
Short name T127
Test name
Test status
Simulation time 6260016947 ps
CPU time 169.64 seconds
Started Jun 06 02:35:57 PM PDT 24
Finished Jun 06 02:38:47 PM PDT 24
Peak memory 219324 kb
Host smart-5ad7f8a1-1657-410b-a132-94400767bf70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704275211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3704275211
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.936757070
Short name T88
Test name
Test status
Simulation time 338546507 ps
CPU time 8.06 seconds
Started Jun 06 02:35:42 PM PDT 24
Finished Jun 06 02:35:52 PM PDT 24
Peak memory 211016 kb
Host smart-9f6b3046-992b-4ada-b785-4ee72f40eb47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936757070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.936757070
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.179169451
Short name T150
Test name
Test status
Simulation time 5957538877 ps
CPU time 43.85 seconds
Started Jun 06 01:15:06 PM PDT 24
Finished Jun 06 01:15:51 PM PDT 24
Peak memory 217040 kb
Host smart-30084b54-be09-4438-b691-9965feb681a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179169451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.179169451
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3500849910
Short name T68
Test name
Test status
Simulation time 2016867802 ps
CPU time 55.07 seconds
Started Jun 06 02:35:16 PM PDT 24
Finished Jun 06 02:36:12 PM PDT 24
Peak memory 214560 kb
Host smart-ab6f905d-3d45-43c3-a55d-e2c9c187e07a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500849910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3500849910
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2273037271
Short name T163
Test name
Test status
Simulation time 22498928600 ps
CPU time 50.71 seconds
Started Jun 06 01:14:21 PM PDT 24
Finished Jun 06 01:15:13 PM PDT 24
Peak memory 218884 kb
Host smart-5dc8e385-0386-4d4a-8462-686d429e130d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273037271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2273037271
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2312993497
Short name T47
Test name
Test status
Simulation time 7625413336 ps
CPU time 60.15 seconds
Started Jun 06 01:14:36 PM PDT 24
Finished Jun 06 01:15:38 PM PDT 24
Peak memory 219036 kb
Host smart-89d95dde-8d20-46bd-bd70-7a9a2f30fefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312993497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2312993497
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3684645230
Short name T130
Test name
Test status
Simulation time 11718846446 ps
CPU time 97.23 seconds
Started Jun 06 02:35:24 PM PDT 24
Finished Jun 06 02:37:03 PM PDT 24
Peak memory 214376 kb
Host smart-be925d04-49d9-4531-bc73-ba9562bfe69d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684645230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3684645230
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1360450668
Short name T15
Test name
Test status
Simulation time 215987869036 ps
CPU time 551.82 seconds
Started Jun 06 01:14:11 PM PDT 24
Finished Jun 06 01:23:24 PM PDT 24
Peak memory 239016 kb
Host smart-41fc4718-8c62-4a64-95d1-d4620ea97355
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360450668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1360450668
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3153974008
Short name T66
Test name
Test status
Simulation time 505200088 ps
CPU time 23.15 seconds
Started Jun 06 01:14:38 PM PDT 24
Finished Jun 06 01:15:03 PM PDT 24
Peak memory 215572 kb
Host smart-f378cd1d-c089-4d7d-ab10-eddaa60e961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153974008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3153974008
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3292068005
Short name T121
Test name
Test status
Simulation time 4305848551 ps
CPU time 55.84 seconds
Started Jun 06 02:36:25 PM PDT 24
Finished Jun 06 02:37:22 PM PDT 24
Peak memory 216292 kb
Host smart-03506ed8-9314-416e-a016-0c6b6526f926
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292068005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3292068005
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3666105402
Short name T80
Test name
Test status
Simulation time 14981145049 ps
CPU time 99.16 seconds
Started Jun 06 02:36:30 PM PDT 24
Finished Jun 06 02:38:10 PM PDT 24
Peak memory 214204 kb
Host smart-f31955ea-b0de-4ea3-8047-5617012138aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666105402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3666105402
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.475864873
Short name T128
Test name
Test status
Simulation time 5134875779 ps
CPU time 164.91 seconds
Started Jun 06 02:36:33 PM PDT 24
Finished Jun 06 02:39:19 PM PDT 24
Peak memory 215632 kb
Host smart-916a2645-26c6-4aaf-aa29-70b3fa7a7ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475864873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.475864873
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.287844850
Short name T126
Test name
Test status
Simulation time 1702769755 ps
CPU time 156.59 seconds
Started Jun 06 02:36:44 PM PDT 24
Finished Jun 06 02:39:22 PM PDT 24
Peak memory 214248 kb
Host smart-69738bf9-3ca7-42bc-aef4-2ac84650b1d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287844850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.287844850
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.55024574
Short name T142
Test name
Test status
Simulation time 5609200899 ps
CPU time 108.55 seconds
Started Jun 06 01:14:48 PM PDT 24
Finished Jun 06 01:16:38 PM PDT 24
Peak memory 239616 kb
Host smart-369f867c-e9fc-4d34-86a7-c5eea6ea643b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55024574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_co
rrupt_sig_fatal_chk.55024574
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3914522086
Short name T107
Test name
Test status
Simulation time 101216808078 ps
CPU time 183.65 seconds
Started Jun 06 01:15:48 PM PDT 24
Finished Jun 06 01:18:53 PM PDT 24
Peak memory 222116 kb
Host smart-a2497656-d603-4661-bd55-72738105e1ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914522086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3914522086
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3848964966
Short name T396
Test name
Test status
Simulation time 7048608209 ps
CPU time 28.96 seconds
Started Jun 06 02:35:15 PM PDT 24
Finished Jun 06 02:35:46 PM PDT 24
Peak memory 212380 kb
Host smart-a5aca1ff-7571-4e29-a46c-0c2e615d9496
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848964966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3848964966
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1785800315
Short name T408
Test name
Test status
Simulation time 68767938481 ps
CPU time 30.5 seconds
Started Jun 06 02:35:13 PM PDT 24
Finished Jun 06 02:35:45 PM PDT 24
Peak memory 212108 kb
Host smart-ce6a3d7e-3608-4d06-9e3e-13c3a2d2aa44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785800315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1785800315
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1178690221
Short name T357
Test name
Test status
Simulation time 12391657966 ps
CPU time 29.51 seconds
Started Jun 06 02:35:17 PM PDT 24
Finished Jun 06 02:35:47 PM PDT 24
Peak memory 212204 kb
Host smart-b207c742-a822-4f17-aeac-1f8c2bf96baa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178690221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1178690221
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3826973270
Short name T446
Test name
Test status
Simulation time 10553433491 ps
CPU time 24.67 seconds
Started Jun 06 02:35:14 PM PDT 24
Finished Jun 06 02:35:40 PM PDT 24
Peak memory 218412 kb
Host smart-f37be237-3464-4dd6-9da7-7d990e2b6615
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826973270 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3826973270
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2218524274
Short name T455
Test name
Test status
Simulation time 2317506696 ps
CPU time 21.35 seconds
Started Jun 06 02:35:15 PM PDT 24
Finished Jun 06 02:35:38 PM PDT 24
Peak memory 212012 kb
Host smart-a0169e21-fb72-48a6-87b6-e8c0b591bbe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218524274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2218524274
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2145597077
Short name T447
Test name
Test status
Simulation time 167320886 ps
CPU time 8.14 seconds
Started Jun 06 02:35:23 PM PDT 24
Finished Jun 06 02:35:32 PM PDT 24
Peak memory 210864 kb
Host smart-f8217626-82a0-49df-9812-89d3a7b9a4a0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145597077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2145597077
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2187195665
Short name T360
Test name
Test status
Simulation time 3022923517 ps
CPU time 25.29 seconds
Started Jun 06 02:35:20 PM PDT 24
Finished Jun 06 02:35:47 PM PDT 24
Peak memory 210916 kb
Host smart-75894cb6-c9f3-49ac-bd1c-f78bdb144fd1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187195665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2187195665
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.378034654
Short name T441
Test name
Test status
Simulation time 18470602160 ps
CPU time 162 seconds
Started Jun 06 02:35:14 PM PDT 24
Finished Jun 06 02:37:57 PM PDT 24
Peak memory 215348 kb
Host smart-9bd2df3b-fd2d-4d6c-833a-c6ffa08d56ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378034654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.378034654
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.232838413
Short name T119
Test name
Test status
Simulation time 10916978170 ps
CPU time 26.28 seconds
Started Jun 06 02:35:14 PM PDT 24
Finished Jun 06 02:35:42 PM PDT 24
Peak memory 212792 kb
Host smart-e089793a-9acd-4274-bc8a-4b3c83386474
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232838413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.232838413
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.120318338
Short name T424
Test name
Test status
Simulation time 689513730 ps
CPU time 11.2 seconds
Started Jun 06 02:35:14 PM PDT 24
Finished Jun 06 02:35:27 PM PDT 24
Peak memory 217312 kb
Host smart-2c52f4f0-aa89-4e7f-ba4d-720769e3e0d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120318338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.120318338
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4072956339
Short name T134
Test name
Test status
Simulation time 8731004063 ps
CPU time 102.35 seconds
Started Jun 06 02:35:23 PM PDT 24
Finished Jun 06 02:37:06 PM PDT 24
Peak memory 214284 kb
Host smart-8f01dec1-f394-457c-a8fc-ad13ec27215b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072956339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.4072956339
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3632520709
Short name T398
Test name
Test status
Simulation time 3028143978 ps
CPU time 26.47 seconds
Started Jun 06 02:35:24 PM PDT 24
Finished Jun 06 02:35:51 PM PDT 24
Peak memory 211972 kb
Host smart-1e5911aa-c745-4f42-975f-7aacef4a662f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632520709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3632520709
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.494713822
Short name T374
Test name
Test status
Simulation time 5976387338 ps
CPU time 18.14 seconds
Started Jun 06 02:35:22 PM PDT 24
Finished Jun 06 02:35:41 PM PDT 24
Peak memory 212272 kb
Host smart-84ba446c-18d1-41d3-8cd1-48b95b4eecd6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494713822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.494713822
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.531544304
Short name T399
Test name
Test status
Simulation time 5554573406 ps
CPU time 28.43 seconds
Started Jun 06 02:35:24 PM PDT 24
Finished Jun 06 02:35:53 PM PDT 24
Peak memory 212176 kb
Host smart-d13a6033-635f-48d8-8eef-a61ebc657918
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531544304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.531544304
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2061056103
Short name T395
Test name
Test status
Simulation time 42760307307 ps
CPU time 25.39 seconds
Started Jun 06 02:35:23 PM PDT 24
Finished Jun 06 02:35:49 PM PDT 24
Peak memory 217848 kb
Host smart-3a6b56f7-86d0-46f3-af02-d1b28774e031
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061056103 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2061056103
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3743325489
Short name T407
Test name
Test status
Simulation time 9123021131 ps
CPU time 22.95 seconds
Started Jun 06 02:35:24 PM PDT 24
Finished Jun 06 02:35:48 PM PDT 24
Peak memory 212220 kb
Host smart-9a56b5a0-ee94-45df-ae20-20b102f50d09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743325489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3743325489
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.428842383
Short name T450
Test name
Test status
Simulation time 5261654892 ps
CPU time 16.69 seconds
Started Jun 06 02:35:29 PM PDT 24
Finished Jun 06 02:35:47 PM PDT 24
Peak memory 211200 kb
Host smart-f6a4ece6-023d-45ab-b18e-0f460807f562
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428842383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.428842383
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3308538603
Short name T438
Test name
Test status
Simulation time 170716018 ps
CPU time 8.2 seconds
Started Jun 06 02:35:29 PM PDT 24
Finished Jun 06 02:35:39 PM PDT 24
Peak memory 210616 kb
Host smart-cffba93b-c983-45f9-b04f-94e8b1115d1b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308538603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3308538603
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2207387488
Short name T373
Test name
Test status
Simulation time 7199032627 ps
CPU time 29.2 seconds
Started Jun 06 02:35:22 PM PDT 24
Finished Jun 06 02:35:52 PM PDT 24
Peak memory 212948 kb
Host smart-5680f08f-3d67-4964-9ca5-73a61d6245ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207387488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2207387488
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1456757140
Short name T430
Test name
Test status
Simulation time 4192098337 ps
CPU time 36.55 seconds
Started Jun 06 02:35:22 PM PDT 24
Finished Jun 06 02:36:00 PM PDT 24
Peak memory 218652 kb
Host smart-179cbed7-810f-4d16-a56a-8ae869b34ba4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456757140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1456757140
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.851556737
Short name T392
Test name
Test status
Simulation time 1415156949 ps
CPU time 15.02 seconds
Started Jun 06 02:36:14 PM PDT 24
Finished Jun 06 02:36:30 PM PDT 24
Peak memory 214336 kb
Host smart-cc84d3e6-f46a-4381-80df-7bc402db740d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851556737 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.851556737
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2461032883
Short name T391
Test name
Test status
Simulation time 20784729432 ps
CPU time 24.3 seconds
Started Jun 06 02:36:16 PM PDT 24
Finished Jun 06 02:36:42 PM PDT 24
Peak memory 212788 kb
Host smart-ff482f9c-9b40-4cae-b1e8-d385af9bfa9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461032883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2461032883
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2059011376
Short name T102
Test name
Test status
Simulation time 12330718982 ps
CPU time 128.54 seconds
Started Jun 06 02:36:15 PM PDT 24
Finished Jun 06 02:38:25 PM PDT 24
Peak memory 215620 kb
Host smart-abb43191-aa94-4129-b9c9-43738c54de06
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059011376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2059011376
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1859631290
Short name T372
Test name
Test status
Simulation time 3973684798 ps
CPU time 29.03 seconds
Started Jun 06 02:36:16 PM PDT 24
Finished Jun 06 02:36:46 PM PDT 24
Peak memory 212384 kb
Host smart-35536843-d572-4046-a3c1-054e27393538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859631290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1859631290
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2026198179
Short name T448
Test name
Test status
Simulation time 776900743 ps
CPU time 17.97 seconds
Started Jun 06 02:36:21 PM PDT 24
Finished Jun 06 02:36:40 PM PDT 24
Peak memory 217564 kb
Host smart-54725976-9676-4b8a-9387-238e2842e58d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026198179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2026198179
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3608036626
Short name T133
Test name
Test status
Simulation time 7694138559 ps
CPU time 161.53 seconds
Started Jun 06 02:36:16 PM PDT 24
Finished Jun 06 02:38:59 PM PDT 24
Peak memory 214588 kb
Host smart-17a9384e-37ba-4af7-8015-a4b2487157c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608036626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3608036626
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2679234233
Short name T364
Test name
Test status
Simulation time 12857727398 ps
CPU time 26.96 seconds
Started Jun 06 02:36:26 PM PDT 24
Finished Jun 06 02:36:54 PM PDT 24
Peak memory 219264 kb
Host smart-546d2172-1eb4-421a-a42a-cc2eff3e05d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679234233 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2679234233
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.748394303
Short name T425
Test name
Test status
Simulation time 4276505228 ps
CPU time 21.35 seconds
Started Jun 06 02:36:25 PM PDT 24
Finished Jun 06 02:36:47 PM PDT 24
Peak memory 212268 kb
Host smart-b7013a83-0e3c-4176-892c-753e275846c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748394303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.748394303
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1273709527
Short name T437
Test name
Test status
Simulation time 3058985728 ps
CPU time 76.51 seconds
Started Jun 06 02:36:24 PM PDT 24
Finished Jun 06 02:37:42 PM PDT 24
Peak memory 215508 kb
Host smart-676d67c2-45e1-460e-9a6c-3245797af458
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273709527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1273709527
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.304383182
Short name T380
Test name
Test status
Simulation time 362899900 ps
CPU time 11.76 seconds
Started Jun 06 02:36:26 PM PDT 24
Finished Jun 06 02:36:39 PM PDT 24
Peak memory 212696 kb
Host smart-e7f2cb81-8c59-4f4d-8e10-a6677a60481e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304383182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.304383182
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2151157217
Short name T385
Test name
Test status
Simulation time 7666307689 ps
CPU time 33.14 seconds
Started Jun 06 02:36:25 PM PDT 24
Finished Jun 06 02:36:59 PM PDT 24
Peak memory 217920 kb
Host smart-6876b8b5-7a8c-4b40-b45f-5ae6dbbbb208
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151157217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2151157217
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1810263284
Short name T125
Test name
Test status
Simulation time 8496248817 ps
CPU time 88.73 seconds
Started Jun 06 02:36:28 PM PDT 24
Finished Jun 06 02:37:57 PM PDT 24
Peak memory 214296 kb
Host smart-a8ac5a49-7faa-4a95-affa-21979be089b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810263284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1810263284
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1915749880
Short name T77
Test name
Test status
Simulation time 15411110335 ps
CPU time 31.47 seconds
Started Jun 06 02:36:25 PM PDT 24
Finished Jun 06 02:36:57 PM PDT 24
Peak memory 217420 kb
Host smart-854465e4-e06e-4929-8ea8-f166d69e1de8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915749880 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1915749880
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2959954569
Short name T449
Test name
Test status
Simulation time 752006007 ps
CPU time 7.98 seconds
Started Jun 06 02:36:26 PM PDT 24
Finished Jun 06 02:36:35 PM PDT 24
Peak memory 211024 kb
Host smart-eb99de27-e1cd-4415-a589-6fc394b17346
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959954569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2959954569
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3945989246
Short name T426
Test name
Test status
Simulation time 15381322618 ps
CPU time 31.42 seconds
Started Jun 06 02:36:25 PM PDT 24
Finished Jun 06 02:36:58 PM PDT 24
Peak memory 211708 kb
Host smart-4b202ec9-9761-4590-b21e-e366cc12d09a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945989246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3945989246
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1361644341
Short name T418
Test name
Test status
Simulation time 2839815603 ps
CPU time 26.62 seconds
Started Jun 06 02:36:24 PM PDT 24
Finished Jun 06 02:36:52 PM PDT 24
Peak memory 218564 kb
Host smart-1994f025-901c-4890-9312-f95a28aab3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361644341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1361644341
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1924756747
Short name T387
Test name
Test status
Simulation time 18409964973 ps
CPU time 27.59 seconds
Started Jun 06 02:36:32 PM PDT 24
Finished Jun 06 02:37:01 PM PDT 24
Peak memory 218268 kb
Host smart-e1128463-306a-4464-8dd6-7cd903fe2c06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924756747 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1924756747
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1971854373
Short name T397
Test name
Test status
Simulation time 435928790 ps
CPU time 8.29 seconds
Started Jun 06 02:36:32 PM PDT 24
Finished Jun 06 02:36:42 PM PDT 24
Peak memory 210948 kb
Host smart-95e656d3-e5dc-4750-a81f-e413783dd8a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971854373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1971854373
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3563042415
Short name T105
Test name
Test status
Simulation time 4285275599 ps
CPU time 56.56 seconds
Started Jun 06 02:36:27 PM PDT 24
Finished Jun 06 02:37:25 PM PDT 24
Peak memory 215096 kb
Host smart-e5c3dbd9-da05-4e7b-8dfe-2c51afd65086
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563042415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3563042415
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1183873456
Short name T118
Test name
Test status
Simulation time 2864456382 ps
CPU time 29.79 seconds
Started Jun 06 02:36:33 PM PDT 24
Finished Jun 06 02:37:04 PM PDT 24
Peak memory 212516 kb
Host smart-29437d27-689d-440e-91c3-943b02eb9722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183873456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1183873456
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3237735689
Short name T383
Test name
Test status
Simulation time 1818084971 ps
CPU time 22.57 seconds
Started Jun 06 02:36:25 PM PDT 24
Finished Jun 06 02:36:49 PM PDT 24
Peak memory 218540 kb
Host smart-905bc29d-f1fa-40b5-becd-22f600f76d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237735689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3237735689
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3454816243
Short name T436
Test name
Test status
Simulation time 964387719 ps
CPU time 78.93 seconds
Started Jun 06 02:36:38 PM PDT 24
Finished Jun 06 02:37:58 PM PDT 24
Peak memory 213608 kb
Host smart-f589d651-07f5-4cd7-8a9b-175fb80db74e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454816243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3454816243
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.95271115
Short name T433
Test name
Test status
Simulation time 609213586 ps
CPU time 8.95 seconds
Started Jun 06 02:36:34 PM PDT 24
Finished Jun 06 02:36:45 PM PDT 24
Peak memory 216384 kb
Host smart-d14156e2-8930-4b24-aca7-fb08c3c3e275
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95271115 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.95271115
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.233730280
Short name T423
Test name
Test status
Simulation time 7821530635 ps
CPU time 30.43 seconds
Started Jun 06 02:36:35 PM PDT 24
Finished Jun 06 02:37:07 PM PDT 24
Peak memory 212664 kb
Host smart-20d82501-3104-4ffb-9eb1-748dd2fe9aec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233730280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.233730280
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2291839659
Short name T403
Test name
Test status
Simulation time 66999274362 ps
CPU time 156.54 seconds
Started Jun 06 02:36:34 PM PDT 24
Finished Jun 06 02:39:12 PM PDT 24
Peak memory 215456 kb
Host smart-c80e98d6-04ca-4630-866b-0d24c364a7b8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291839659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2291839659
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4019631646
Short name T368
Test name
Test status
Simulation time 11748544455 ps
CPU time 26.16 seconds
Started Jun 06 02:36:34 PM PDT 24
Finished Jun 06 02:37:02 PM PDT 24
Peak memory 212952 kb
Host smart-55ec5d5d-5220-447d-b924-e58ba5c352b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019631646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4019631646
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3705585787
Short name T439
Test name
Test status
Simulation time 3171262576 ps
CPU time 29.93 seconds
Started Jun 06 02:36:32 PM PDT 24
Finished Jun 06 02:37:03 PM PDT 24
Peak memory 218348 kb
Host smart-1eb0b424-4226-4d2d-9b31-155821513bdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705585787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3705585787
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1221703228
Short name T409
Test name
Test status
Simulation time 28109181964 ps
CPU time 96.32 seconds
Started Jun 06 02:36:34 PM PDT 24
Finished Jun 06 02:38:12 PM PDT 24
Peak memory 214220 kb
Host smart-d73ad098-0599-4c7f-9078-19d1962672d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221703228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1221703228
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1446128838
Short name T362
Test name
Test status
Simulation time 2264096928 ps
CPU time 21.28 seconds
Started Jun 06 02:36:34 PM PDT 24
Finished Jun 06 02:36:57 PM PDT 24
Peak memory 217612 kb
Host smart-24766d66-d044-4e29-88c6-494cf8cf5531
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446128838 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1446128838
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.381751574
Short name T404
Test name
Test status
Simulation time 70136287164 ps
CPU time 29.03 seconds
Started Jun 06 02:36:33 PM PDT 24
Finished Jun 06 02:37:04 PM PDT 24
Peak memory 212748 kb
Host smart-a8f58f62-e1fd-4b77-ac13-1f2c08c5061d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381751574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.381751574
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.636131316
Short name T99
Test name
Test status
Simulation time 3676301554 ps
CPU time 80.91 seconds
Started Jun 06 02:36:35 PM PDT 24
Finished Jun 06 02:37:57 PM PDT 24
Peak memory 211064 kb
Host smart-2a37e9c6-d288-4588-b895-e50017ca1d72
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636131316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.636131316
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.222877937
Short name T120
Test name
Test status
Simulation time 18064272907 ps
CPU time 24.21 seconds
Started Jun 06 02:36:34 PM PDT 24
Finished Jun 06 02:37:00 PM PDT 24
Peak memory 213160 kb
Host smart-3310824d-e1f8-483e-a8b5-bc86802f3531
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222877937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.222877937
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.23248455
Short name T413
Test name
Test status
Simulation time 11865818373 ps
CPU time 27.78 seconds
Started Jun 06 02:36:33 PM PDT 24
Finished Jun 06 02:37:03 PM PDT 24
Peak memory 218492 kb
Host smart-e69ce5ed-574d-4f70-9a53-ff2acdb91502
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23248455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.23248455
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.876294492
Short name T412
Test name
Test status
Simulation time 24183979555 ps
CPU time 32.74 seconds
Started Jun 06 02:36:33 PM PDT 24
Finished Jun 06 02:37:07 PM PDT 24
Peak memory 218424 kb
Host smart-46aeb059-b3a5-441f-b6ca-78496c9cba28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876294492 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.876294492
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2494497503
Short name T444
Test name
Test status
Simulation time 176291723 ps
CPU time 8.28 seconds
Started Jun 06 02:36:33 PM PDT 24
Finished Jun 06 02:36:42 PM PDT 24
Peak memory 211076 kb
Host smart-1cb91e11-74de-4745-a387-953781016426
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494497503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2494497503
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1405092443
Short name T84
Test name
Test status
Simulation time 848579528 ps
CPU time 37.92 seconds
Started Jun 06 02:36:38 PM PDT 24
Finished Jun 06 02:37:16 PM PDT 24
Peak memory 214076 kb
Host smart-65f95272-9264-4162-8c8b-39c6ede89cff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405092443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1405092443
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.943908546
Short name T375
Test name
Test status
Simulation time 11791247732 ps
CPU time 25.74 seconds
Started Jun 06 02:36:36 PM PDT 24
Finished Jun 06 02:37:03 PM PDT 24
Peak memory 212860 kb
Host smart-36f45464-553e-40b1-bf48-bf62964dbde4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943908546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.943908546
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3578132381
Short name T415
Test name
Test status
Simulation time 8608116359 ps
CPU time 21.91 seconds
Started Jun 06 02:36:33 PM PDT 24
Finished Jun 06 02:36:56 PM PDT 24
Peak memory 218904 kb
Host smart-ed8b7b8c-19ea-4a8b-943e-0cf13f9aa96e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578132381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3578132381
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3606993911
Short name T131
Test name
Test status
Simulation time 17866082867 ps
CPU time 99.1 seconds
Started Jun 06 02:36:32 PM PDT 24
Finished Jun 06 02:38:13 PM PDT 24
Peak memory 213260 kb
Host smart-1959f5ea-1d4b-4b3f-9226-3e1a51798cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606993911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3606993911
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1968460616
Short name T369
Test name
Test status
Simulation time 4304995953 ps
CPU time 20.87 seconds
Started Jun 06 02:36:36 PM PDT 24
Finished Jun 06 02:36:58 PM PDT 24
Peak memory 215356 kb
Host smart-5a33363a-0b56-4e49-b6b5-26f06584201e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968460616 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1968460616
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3358434528
Short name T440
Test name
Test status
Simulation time 6541249519 ps
CPU time 26.87 seconds
Started Jun 06 02:36:34 PM PDT 24
Finished Jun 06 02:37:02 PM PDT 24
Peak memory 212348 kb
Host smart-7ed0db67-3a4e-4e5b-af6f-b4124243cfaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358434528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3358434528
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2776880211
Short name T103
Test name
Test status
Simulation time 13409909425 ps
CPU time 111.13 seconds
Started Jun 06 02:36:32 PM PDT 24
Finished Jun 06 02:38:24 PM PDT 24
Peak memory 211988 kb
Host smart-befe0c6b-7e6b-4546-b753-93dd98597908
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776880211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2776880211
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2506352348
Short name T417
Test name
Test status
Simulation time 988598940 ps
CPU time 9.74 seconds
Started Jun 06 02:36:34 PM PDT 24
Finished Jun 06 02:36:45 PM PDT 24
Peak memory 211548 kb
Host smart-9240d001-38cf-448c-8a13-fa21b9768a6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506352348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2506352348
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3920414553
Short name T429
Test name
Test status
Simulation time 497222043 ps
CPU time 14.6 seconds
Started Jun 06 02:36:33 PM PDT 24
Finished Jun 06 02:36:49 PM PDT 24
Peak memory 219092 kb
Host smart-37b2673c-edcd-444d-a11b-cd2406900de3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920414553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3920414553
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4207789262
Short name T78
Test name
Test status
Simulation time 10400771622 ps
CPU time 23.14 seconds
Started Jun 06 02:36:43 PM PDT 24
Finished Jun 06 02:37:07 PM PDT 24
Peak memory 219208 kb
Host smart-3e04249b-14c6-4a18-bcad-05f735155d0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207789262 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4207789262
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3308991702
Short name T87
Test name
Test status
Simulation time 8602763478 ps
CPU time 21.42 seconds
Started Jun 06 02:36:45 PM PDT 24
Finished Jun 06 02:37:08 PM PDT 24
Peak memory 212420 kb
Host smart-541a5e93-c902-47e3-a3b4-4b085bba01dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308991702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3308991702
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3671813165
Short name T86
Test name
Test status
Simulation time 8582469553 ps
CPU time 87.37 seconds
Started Jun 06 02:36:44 PM PDT 24
Finished Jun 06 02:38:13 PM PDT 24
Peak memory 214860 kb
Host smart-fed65ecc-90fe-4f50-89a0-b42c6ac300d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671813165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3671813165
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4239918809
Short name T432
Test name
Test status
Simulation time 18300276288 ps
CPU time 22.11 seconds
Started Jun 06 02:36:44 PM PDT 24
Finished Jun 06 02:37:08 PM PDT 24
Peak memory 213084 kb
Host smart-d97a1d44-3ecc-4c57-b20d-5593f486bd77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239918809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.4239918809
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1404544926
Short name T389
Test name
Test status
Simulation time 10064111028 ps
CPU time 27.51 seconds
Started Jun 06 02:36:44 PM PDT 24
Finished Jun 06 02:37:13 PM PDT 24
Peak memory 219256 kb
Host smart-98a0bdf5-e5f2-4f3d-9d64-6b9954d08e23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404544926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1404544926
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.856869459
Short name T390
Test name
Test status
Simulation time 186612011 ps
CPU time 8.74 seconds
Started Jun 06 02:36:43 PM PDT 24
Finished Jun 06 02:36:53 PM PDT 24
Peak memory 219264 kb
Host smart-647196ec-6266-457d-b980-50c77e9f4828
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856869459 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.856869459
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1426823620
Short name T421
Test name
Test status
Simulation time 2456457825 ps
CPU time 22.19 seconds
Started Jun 06 02:36:43 PM PDT 24
Finished Jun 06 02:37:06 PM PDT 24
Peak memory 212160 kb
Host smart-f3ddc64e-6f9c-49c8-b93c-20a9836ea778
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426823620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1426823620
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1480117303
Short name T401
Test name
Test status
Simulation time 1084034206 ps
CPU time 56.66 seconds
Started Jun 06 02:36:44 PM PDT 24
Finished Jun 06 02:37:42 PM PDT 24
Peak memory 214560 kb
Host smart-a7920b2b-ca19-4bee-9842-348023ba6e28
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480117303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1480117303
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3110214033
Short name T69
Test name
Test status
Simulation time 6639105986 ps
CPU time 26.32 seconds
Started Jun 06 02:36:46 PM PDT 24
Finished Jun 06 02:37:14 PM PDT 24
Peak memory 212964 kb
Host smart-47cc6e27-90e5-46b6-b246-629b669254d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110214033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3110214033
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.377557341
Short name T431
Test name
Test status
Simulation time 2790490465 ps
CPU time 27.49 seconds
Started Jun 06 02:36:45 PM PDT 24
Finished Jun 06 02:37:14 PM PDT 24
Peak memory 216792 kb
Host smart-ff5e465f-368e-48a9-a144-1949ecd754aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377557341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.377557341
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2591861607
Short name T55
Test name
Test status
Simulation time 3472124014 ps
CPU time 84.5 seconds
Started Jun 06 02:36:43 PM PDT 24
Finished Jun 06 02:38:09 PM PDT 24
Peak memory 213084 kb
Host smart-6bfc116a-3ee9-4b0f-ab5f-ea0652b5c1ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591861607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2591861607
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2911869404
Short name T81
Test name
Test status
Simulation time 19543880242 ps
CPU time 32.81 seconds
Started Jun 06 02:35:31 PM PDT 24
Finished Jun 06 02:36:05 PM PDT 24
Peak memory 212424 kb
Host smart-b134c391-0e75-4351-8ab3-2b9cf8da74e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911869404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2911869404
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.75423959
Short name T400
Test name
Test status
Simulation time 2896281577 ps
CPU time 17.41 seconds
Started Jun 06 02:35:33 PM PDT 24
Finished Jun 06 02:35:51 PM PDT 24
Peak memory 211132 kb
Host smart-dc6ae367-f70c-49fa-91b6-cf7dd7d43ba4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75423959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_ba
sh.75423959
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3918163983
Short name T402
Test name
Test status
Simulation time 5015550733 ps
CPU time 25.94 seconds
Started Jun 06 02:35:34 PM PDT 24
Finished Jun 06 02:36:01 PM PDT 24
Peak memory 212124 kb
Host smart-aec33767-0005-48e6-82a9-1d39259552c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918163983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3918163983
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2508987247
Short name T370
Test name
Test status
Simulation time 3884945731 ps
CPU time 19.81 seconds
Started Jun 06 02:35:32 PM PDT 24
Finished Jun 06 02:35:52 PM PDT 24
Peak memory 216136 kb
Host smart-cb63e7c2-e98e-4566-aae3-cfe782bdcd1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508987247 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2508987247
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1168633283
Short name T82
Test name
Test status
Simulation time 9173580832 ps
CPU time 22.03 seconds
Started Jun 06 02:35:32 PM PDT 24
Finished Jun 06 02:35:54 PM PDT 24
Peak memory 212664 kb
Host smart-1c8e793c-6903-4788-8923-558951d75978
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168633283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1168633283
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2896755867
Short name T358
Test name
Test status
Simulation time 23198427427 ps
CPU time 23.61 seconds
Started Jun 06 02:35:34 PM PDT 24
Finished Jun 06 02:35:58 PM PDT 24
Peak memory 211196 kb
Host smart-b27f921e-b244-45d1-ac77-c4c631bbb218
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896755867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2896755867
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3290045597
Short name T366
Test name
Test status
Simulation time 3466422378 ps
CPU time 26.72 seconds
Started Jun 06 02:35:32 PM PDT 24
Finished Jun 06 02:35:59 PM PDT 24
Peak memory 210916 kb
Host smart-80fbdd93-064f-4154-a5be-e655934550b5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290045597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3290045597
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3823486920
Short name T97
Test name
Test status
Simulation time 68545215569 ps
CPU time 146.74 seconds
Started Jun 06 02:35:29 PM PDT 24
Finished Jun 06 02:37:57 PM PDT 24
Peak memory 219192 kb
Host smart-cea4e7da-a069-43f9-9c5e-1d8d617d7ee3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823486920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3823486920
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1875311618
Short name T117
Test name
Test status
Simulation time 3870837282 ps
CPU time 30.19 seconds
Started Jun 06 02:35:31 PM PDT 24
Finished Jun 06 02:36:02 PM PDT 24
Peak memory 212584 kb
Host smart-d08a0c17-0a43-4cd0-a981-f9d2793795db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875311618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1875311618
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.183174904
Short name T388
Test name
Test status
Simulation time 688744888 ps
CPU time 12.82 seconds
Started Jun 06 02:35:33 PM PDT 24
Finished Jun 06 02:35:46 PM PDT 24
Peak memory 217788 kb
Host smart-5192ab2e-e445-46d5-96d0-b485f3d7afbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183174904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.183174904
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.971479779
Short name T443
Test name
Test status
Simulation time 72776228592 ps
CPU time 100.4 seconds
Started Jun 06 02:35:33 PM PDT 24
Finished Jun 06 02:37:14 PM PDT 24
Peak memory 219300 kb
Host smart-5a2a924c-5c5c-4b3c-8568-69324b810622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971479779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.971479779
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2764188497
Short name T359
Test name
Test status
Simulation time 167719589 ps
CPU time 8.43 seconds
Started Jun 06 02:35:40 PM PDT 24
Finished Jun 06 02:35:49 PM PDT 24
Peak memory 211024 kb
Host smart-3c7248e2-5d52-41bf-bb38-2e036d5ff601
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764188497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2764188497
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.626145436
Short name T427
Test name
Test status
Simulation time 3738529105 ps
CPU time 35.45 seconds
Started Jun 06 02:35:52 PM PDT 24
Finished Jun 06 02:36:29 PM PDT 24
Peak memory 212284 kb
Host smart-1f5f15d8-1f01-46dc-b429-2dab4d94c4a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626145436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.626145436
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2552233163
Short name T376
Test name
Test status
Simulation time 2798189500 ps
CPU time 23.94 seconds
Started Jun 06 02:35:40 PM PDT 24
Finished Jun 06 02:36:05 PM PDT 24
Peak memory 219172 kb
Host smart-ecc985b8-836c-42a3-8f4b-bfcb2181809a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552233163 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2552233163
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.778349555
Short name T422
Test name
Test status
Simulation time 6920208512 ps
CPU time 19.55 seconds
Started Jun 06 02:35:44 PM PDT 24
Finished Jun 06 02:36:05 PM PDT 24
Peak memory 212540 kb
Host smart-2e5f0a59-05a0-4316-b0ba-355604456129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778349555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.778349555
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2985814647
Short name T405
Test name
Test status
Simulation time 15730482944 ps
CPU time 31.6 seconds
Started Jun 06 02:35:41 PM PDT 24
Finished Jun 06 02:36:14 PM PDT 24
Peak memory 211044 kb
Host smart-9df513fd-e188-4b22-ba6a-533ec4e6fd42
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985814647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2985814647
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3275431687
Short name T411
Test name
Test status
Simulation time 2493835171 ps
CPU time 22.47 seconds
Started Jun 06 02:35:39 PM PDT 24
Finished Jun 06 02:36:03 PM PDT 24
Peak memory 210924 kb
Host smart-8e44188a-e2d1-4e2e-bd8b-5f720437e369
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275431687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3275431687
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.603019597
Short name T98
Test name
Test status
Simulation time 92494596770 ps
CPU time 185.26 seconds
Started Jun 06 02:35:40 PM PDT 24
Finished Jun 06 02:38:46 PM PDT 24
Peak memory 219296 kb
Host smart-4190910f-b0ea-44a7-a042-d12e0aa7c5ac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603019597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.603019597
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.369965550
Short name T83
Test name
Test status
Simulation time 14447592597 ps
CPU time 29.81 seconds
Started Jun 06 02:35:44 PM PDT 24
Finished Jun 06 02:36:16 PM PDT 24
Peak memory 212976 kb
Host smart-a21d89f4-96b0-4ff7-98cf-ab5a7f617f52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369965550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.369965550
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2579517153
Short name T434
Test name
Test status
Simulation time 7848769536 ps
CPU time 22.89 seconds
Started Jun 06 02:35:43 PM PDT 24
Finished Jun 06 02:36:07 PM PDT 24
Peak memory 218780 kb
Host smart-e9187f5f-6f3e-477d-9a4f-6d583c746200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579517153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2579517153
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2917285688
Short name T135
Test name
Test status
Simulation time 5506532155 ps
CPU time 164.75 seconds
Started Jun 06 02:35:43 PM PDT 24
Finished Jun 06 02:38:29 PM PDT 24
Peak memory 214676 kb
Host smart-1eb6a80f-7738-49e0-bfe0-7deaaeb8d419
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917285688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2917285688
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.40260818
Short name T386
Test name
Test status
Simulation time 169397075 ps
CPU time 7.95 seconds
Started Jun 06 02:35:48 PM PDT 24
Finished Jun 06 02:35:58 PM PDT 24
Peak memory 211020 kb
Host smart-cfffd47c-37bd-4d48-9ff3-fbacc705eee9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40260818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasi
ng.40260818
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2866668570
Short name T361
Test name
Test status
Simulation time 9235120975 ps
CPU time 21.9 seconds
Started Jun 06 02:35:49 PM PDT 24
Finished Jun 06 02:36:13 PM PDT 24
Peak memory 212292 kb
Host smart-7ece4e61-e418-4218-948c-25f5a5f84e21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866668570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2866668570
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2585233299
Short name T95
Test name
Test status
Simulation time 7353113114 ps
CPU time 37.16 seconds
Started Jun 06 02:35:49 PM PDT 24
Finished Jun 06 02:36:28 PM PDT 24
Peak memory 212328 kb
Host smart-1f8a61a6-fe88-41c3-9259-0d14846f08ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585233299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2585233299
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3655498927
Short name T428
Test name
Test status
Simulation time 1829665613 ps
CPU time 19.73 seconds
Started Jun 06 02:35:58 PM PDT 24
Finished Jun 06 02:36:19 PM PDT 24
Peak memory 217740 kb
Host smart-9199f4c4-55eb-4e31-a117-97164cb0e25c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655498927 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3655498927
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1547542586
Short name T96
Test name
Test status
Simulation time 14336770578 ps
CPU time 30.01 seconds
Started Jun 06 02:35:47 PM PDT 24
Finished Jun 06 02:36:18 PM PDT 24
Peak memory 212544 kb
Host smart-76c4aec3-8a27-431b-8a98-00ee8e44c1dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547542586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1547542586
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2304762240
Short name T410
Test name
Test status
Simulation time 6968161095 ps
CPU time 27.93 seconds
Started Jun 06 02:35:49 PM PDT 24
Finished Jun 06 02:36:19 PM PDT 24
Peak memory 211216 kb
Host smart-007e55a2-8073-4740-bc15-cca0fc7b6f4d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304762240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2304762240
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1616692756
Short name T416
Test name
Test status
Simulation time 1362484459 ps
CPU time 16.8 seconds
Started Jun 06 02:35:51 PM PDT 24
Finished Jun 06 02:36:09 PM PDT 24
Peak memory 210852 kb
Host smart-c9528eeb-efde-4b50-a0a8-91ced84915b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616692756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1616692756
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3380584627
Short name T100
Test name
Test status
Simulation time 44208267443 ps
CPU time 178.2 seconds
Started Jun 06 02:35:41 PM PDT 24
Finished Jun 06 02:38:40 PM PDT 24
Peak memory 215176 kb
Host smart-c83d1489-b715-4767-a156-0554778c3dcf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380584627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3380584627
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3026392513
Short name T378
Test name
Test status
Simulation time 699590508 ps
CPU time 12.18 seconds
Started Jun 06 02:35:49 PM PDT 24
Finished Jun 06 02:36:03 PM PDT 24
Peak memory 212496 kb
Host smart-ad32c393-55d3-43d9-aa02-ab4f9b42445b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026392513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3026392513
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2652632546
Short name T379
Test name
Test status
Simulation time 2360897826 ps
CPU time 26.23 seconds
Started Jun 06 02:35:49 PM PDT 24
Finished Jun 06 02:36:17 PM PDT 24
Peak memory 219180 kb
Host smart-c5a75c3e-2277-4431-903c-1e198a1e8e95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652632546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2652632546
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3080662359
Short name T132
Test name
Test status
Simulation time 14703493428 ps
CPU time 170.65 seconds
Started Jun 06 02:35:50 PM PDT 24
Finished Jun 06 02:38:42 PM PDT 24
Peak memory 219300 kb
Host smart-0188d0bf-86fe-4719-a1e8-344323457ab0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080662359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3080662359
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.238209710
Short name T445
Test name
Test status
Simulation time 2984556487 ps
CPU time 18.5 seconds
Started Jun 06 02:35:57 PM PDT 24
Finished Jun 06 02:36:16 PM PDT 24
Peak memory 217240 kb
Host smart-5daced79-f7ae-4016-8824-8126f17e0e77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238209710 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.238209710
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.452178120
Short name T382
Test name
Test status
Simulation time 9309084024 ps
CPU time 20.21 seconds
Started Jun 06 02:35:57 PM PDT 24
Finished Jun 06 02:36:18 PM PDT 24
Peak memory 212808 kb
Host smart-23c7d3e2-81a3-466e-8796-91958c03b79b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452178120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.452178120
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1349687836
Short name T106
Test name
Test status
Simulation time 17287238334 ps
CPU time 63.7 seconds
Started Jun 06 02:35:57 PM PDT 24
Finished Jun 06 02:37:01 PM PDT 24
Peak memory 215248 kb
Host smart-9a80fa46-6113-4302-857e-127550ab034b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349687836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1349687836
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2814066633
Short name T377
Test name
Test status
Simulation time 28013327826 ps
CPU time 35.17 seconds
Started Jun 06 02:35:58 PM PDT 24
Finished Jun 06 02:36:34 PM PDT 24
Peak memory 212796 kb
Host smart-c60f7082-1ea8-45e6-99e6-24bda72ba707
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814066633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2814066633
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2239616864
Short name T384
Test name
Test status
Simulation time 11607349308 ps
CPU time 30.06 seconds
Started Jun 06 02:35:57 PM PDT 24
Finished Jun 06 02:36:28 PM PDT 24
Peak memory 217864 kb
Host smart-70e121d3-7b13-48bb-8e14-abcd372065ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239616864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2239616864
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1120710928
Short name T453
Test name
Test status
Simulation time 957574621 ps
CPU time 80.41 seconds
Started Jun 06 02:35:59 PM PDT 24
Finished Jun 06 02:37:21 PM PDT 24
Peak memory 213976 kb
Host smart-0dedf73c-d53f-4343-886a-7156f3c037bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120710928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1120710928
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.257573217
Short name T365
Test name
Test status
Simulation time 4127896466 ps
CPU time 32.49 seconds
Started Jun 06 02:36:06 PM PDT 24
Finished Jun 06 02:36:40 PM PDT 24
Peak memory 218100 kb
Host smart-e518444e-3dfb-47a0-a5eb-73b1fda3698d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257573217 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.257573217
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3018685330
Short name T104
Test name
Test status
Simulation time 179793275 ps
CPU time 8.03 seconds
Started Jun 06 02:35:56 PM PDT 24
Finished Jun 06 02:36:05 PM PDT 24
Peak memory 211040 kb
Host smart-5600a8d8-c40e-4339-b25a-fc7069247e96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018685330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3018685330
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2173471080
Short name T452
Test name
Test status
Simulation time 95626616375 ps
CPU time 99.8 seconds
Started Jun 06 02:35:57 PM PDT 24
Finished Jun 06 02:37:37 PM PDT 24
Peak memory 214336 kb
Host smart-397b02d4-beda-4b1e-bbe2-b245430f732b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173471080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2173471080
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1477592138
Short name T367
Test name
Test status
Simulation time 174550063 ps
CPU time 8.08 seconds
Started Jun 06 02:36:08 PM PDT 24
Finished Jun 06 02:36:17 PM PDT 24
Peak memory 211668 kb
Host smart-8b3bb68e-8c68-41bf-80ec-348303d4a153
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477592138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1477592138
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1574484103
Short name T435
Test name
Test status
Simulation time 4455375515 ps
CPU time 35.48 seconds
Started Jun 06 02:35:58 PM PDT 24
Finished Jun 06 02:36:34 PM PDT 24
Peak memory 219272 kb
Host smart-875d685d-0011-4df5-82fd-61d4b9748c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574484103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1574484103
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.452931783
Short name T406
Test name
Test status
Simulation time 51214067062 ps
CPU time 29.38 seconds
Started Jun 06 02:36:06 PM PDT 24
Finished Jun 06 02:36:37 PM PDT 24
Peak memory 216364 kb
Host smart-8929674d-4381-4784-8fe9-d97db1583526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452931783 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.452931783
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4096686535
Short name T454
Test name
Test status
Simulation time 433618915 ps
CPU time 10.94 seconds
Started Jun 06 02:36:08 PM PDT 24
Finished Jun 06 02:36:20 PM PDT 24
Peak memory 210976 kb
Host smart-6d21c72d-d726-4560-862c-662806c0ed94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096686535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4096686535
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.151276389
Short name T414
Test name
Test status
Simulation time 5719252446 ps
CPU time 38.64 seconds
Started Jun 06 02:36:05 PM PDT 24
Finished Jun 06 02:36:45 PM PDT 24
Peak memory 214248 kb
Host smart-96db6c91-3161-479f-a741-bd7cfc77fa3c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151276389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.151276389
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2069460194
Short name T419
Test name
Test status
Simulation time 7012836366 ps
CPU time 20.35 seconds
Started Jun 06 02:36:08 PM PDT 24
Finished Jun 06 02:36:29 PM PDT 24
Peak memory 211552 kb
Host smart-337d8fc7-37a8-45c8-ad7c-4add03f5c872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069460194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2069460194
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2740437954
Short name T442
Test name
Test status
Simulation time 4579253480 ps
CPU time 21.69 seconds
Started Jun 06 02:36:06 PM PDT 24
Finished Jun 06 02:36:29 PM PDT 24
Peak memory 219056 kb
Host smart-6d6c5179-9544-4ebb-bb73-fd33c9f20086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740437954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2740437954
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2125244782
Short name T394
Test name
Test status
Simulation time 4324123013 ps
CPU time 101.87 seconds
Started Jun 06 02:36:08 PM PDT 24
Finished Jun 06 02:37:51 PM PDT 24
Peak memory 214316 kb
Host smart-5965649d-eb4e-4e91-9dd8-09bbd15dcd3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125244782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2125244782
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.95576645
Short name T371
Test name
Test status
Simulation time 3478726143 ps
CPU time 27.91 seconds
Started Jun 06 02:36:20 PM PDT 24
Finished Jun 06 02:36:49 PM PDT 24
Peak memory 216004 kb
Host smart-f052a2b7-aab6-42e5-86da-d8ee8142f009
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95576645 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.95576645
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.924923412
Short name T451
Test name
Test status
Simulation time 660468222 ps
CPU time 8.14 seconds
Started Jun 06 02:36:07 PM PDT 24
Finished Jun 06 02:36:16 PM PDT 24
Peak memory 211348 kb
Host smart-0e400b88-12cf-41fc-82c6-01a8a610f554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924923412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.924923412
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2749067718
Short name T381
Test name
Test status
Simulation time 14471585630 ps
CPU time 117.57 seconds
Started Jun 06 02:36:06 PM PDT 24
Finished Jun 06 02:38:05 PM PDT 24
Peak memory 214564 kb
Host smart-a9e6b803-527f-4bfc-821a-8bb706952a93
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749067718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2749067718
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2481833342
Short name T420
Test name
Test status
Simulation time 172751663 ps
CPU time 8.21 seconds
Started Jun 06 02:36:14 PM PDT 24
Finished Jun 06 02:36:24 PM PDT 24
Peak memory 211292 kb
Host smart-29e7604d-e272-42d8-9a0f-fa15446fd8aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481833342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2481833342
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4055788277
Short name T79
Test name
Test status
Simulation time 12312410183 ps
CPU time 28.23 seconds
Started Jun 06 02:36:08 PM PDT 24
Finished Jun 06 02:36:37 PM PDT 24
Peak memory 219300 kb
Host smart-cbe0235f-9fc9-4ffc-a7c9-79c8e7206364
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055788277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.4055788277
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3814673178
Short name T129
Test name
Test status
Simulation time 1292986139 ps
CPU time 154.86 seconds
Started Jun 06 02:36:06 PM PDT 24
Finished Jun 06 02:38:42 PM PDT 24
Peak memory 219212 kb
Host smart-6dbf3c63-4241-4959-b96d-18811f1854c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814673178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3814673178
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2555358958
Short name T363
Test name
Test status
Simulation time 5149293191 ps
CPU time 22.28 seconds
Started Jun 06 02:36:17 PM PDT 24
Finished Jun 06 02:36:41 PM PDT 24
Peak memory 217548 kb
Host smart-e4894a1c-76e1-4a82-ac91-1efbfcb4f4bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555358958 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2555358958
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3287124074
Short name T67
Test name
Test status
Simulation time 650551104 ps
CPU time 10.4 seconds
Started Jun 06 02:36:14 PM PDT 24
Finished Jun 06 02:36:26 PM PDT 24
Peak memory 211092 kb
Host smart-4491df00-cc9a-4564-90d8-ea605dd40873
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287124074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3287124074
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2821488717
Short name T101
Test name
Test status
Simulation time 24885368464 ps
CPU time 199.96 seconds
Started Jun 06 02:36:16 PM PDT 24
Finished Jun 06 02:39:38 PM PDT 24
Peak memory 215764 kb
Host smart-37987d5c-f5c0-479b-b031-b77a62553595
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821488717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2821488717
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3678984621
Short name T85
Test name
Test status
Simulation time 660358889 ps
CPU time 8.16 seconds
Started Jun 06 02:36:15 PM PDT 24
Finished Jun 06 02:36:24 PM PDT 24
Peak memory 211468 kb
Host smart-4ac80815-71dd-41ca-8879-8b899a899bf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678984621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3678984621
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3072952180
Short name T393
Test name
Test status
Simulation time 17039408592 ps
CPU time 37.18 seconds
Started Jun 06 02:36:15 PM PDT 24
Finished Jun 06 02:36:53 PM PDT 24
Peak memory 219208 kb
Host smart-606c560a-d3d2-4594-920f-73ce87475af2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072952180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3072952180
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1880087595
Short name T56
Test name
Test status
Simulation time 43247281780 ps
CPU time 97.88 seconds
Started Jun 06 02:36:20 PM PDT 24
Finished Jun 06 02:37:59 PM PDT 24
Peak memory 214312 kb
Host smart-eae8bd9d-df6b-4198-a666-9f134266cd02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880087595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1880087595
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3204705005
Short name T167
Test name
Test status
Simulation time 10128804088 ps
CPU time 24.97 seconds
Started Jun 06 01:14:03 PM PDT 24
Finished Jun 06 01:14:29 PM PDT 24
Peak memory 217012 kb
Host smart-89efa15c-f402-4a48-8e99-0b4308c3e518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204705005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3204705005
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1868317457
Short name T274
Test name
Test status
Simulation time 39469434188 ps
CPU time 566.16 seconds
Started Jun 06 01:14:02 PM PDT 24
Finished Jun 06 01:23:29 PM PDT 24
Peak memory 219532 kb
Host smart-5f2abc56-3944-4145-929b-43324ef9cf19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868317457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1868317457
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.275355788
Short name T310
Test name
Test status
Simulation time 30702706777 ps
CPU time 60.56 seconds
Started Jun 06 01:14:04 PM PDT 24
Finished Jun 06 01:15:06 PM PDT 24
Peak memory 219040 kb
Host smart-bacb7a8a-c3de-42bf-86cf-8f9b849ea4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275355788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.275355788
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3656872991
Short name T260
Test name
Test status
Simulation time 184419973 ps
CPU time 10.33 seconds
Started Jun 06 01:14:05 PM PDT 24
Finished Jun 06 01:14:16 PM PDT 24
Peak memory 218956 kb
Host smart-48e76ca0-3847-4939-9094-dc22a5a6c490
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3656872991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3656872991
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1335910827
Short name T25
Test name
Test status
Simulation time 11705083812 ps
CPU time 247.16 seconds
Started Jun 06 01:14:02 PM PDT 24
Finished Jun 06 01:18:11 PM PDT 24
Peak memory 234856 kb
Host smart-dc407ae1-d770-43b8-bdb3-766bfee4bcfb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335910827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1335910827
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.513699512
Short name T35
Test name
Test status
Simulation time 8035153058 ps
CPU time 63.54 seconds
Started Jun 06 01:14:04 PM PDT 24
Finished Jun 06 01:15:09 PM PDT 24
Peak memory 216276 kb
Host smart-9a826f3e-9398-4323-b975-8f801550ab59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513699512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.513699512
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4193612987
Short name T288
Test name
Test status
Simulation time 868476818 ps
CPU time 30.06 seconds
Started Jun 06 01:14:14 PM PDT 24
Finished Jun 06 01:14:45 PM PDT 24
Peak memory 218856 kb
Host smart-9ea2b602-0ff6-4658-8a54-85f231aa32ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193612987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4193612987
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1515270548
Short name T179
Test name
Test status
Simulation time 331870315 ps
CPU time 7.92 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:14:22 PM PDT 24
Peak memory 216668 kb
Host smart-02381412-2d0b-4b65-9d8a-0d6c265ed03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515270548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1515270548
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.950771153
Short name T316
Test name
Test status
Simulation time 134435359293 ps
CPU time 656.45 seconds
Started Jun 06 01:14:03 PM PDT 24
Finished Jun 06 01:25:01 PM PDT 24
Peak memory 234008 kb
Host smart-e77b85db-a20e-482c-bb1c-aaa9e46bd450
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950771153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.950771153
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2760061711
Short name T200
Test name
Test status
Simulation time 16469200511 ps
CPU time 46.2 seconds
Started Jun 06 01:14:04 PM PDT 24
Finished Jun 06 01:14:51 PM PDT 24
Peak memory 227500 kb
Host smart-9b66732a-ffc3-4521-89ee-4ba4a604f859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760061711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2760061711
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1193836299
Short name T209
Test name
Test status
Simulation time 3948662786 ps
CPU time 17.09 seconds
Started Jun 06 01:14:06 PM PDT 24
Finished Jun 06 01:14:24 PM PDT 24
Peak memory 217352 kb
Host smart-d71bb5b7-591d-4b1a-8e76-4a4398a9427b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1193836299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1193836299
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.4096357168
Short name T28
Test name
Test status
Simulation time 7949110234 ps
CPU time 233.12 seconds
Started Jun 06 01:14:04 PM PDT 24
Finished Jun 06 01:17:59 PM PDT 24
Peak memory 235824 kb
Host smart-b75e81f9-11a1-4281-af12-ab6c085f060b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096357168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4096357168
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2572015658
Short name T283
Test name
Test status
Simulation time 693543994 ps
CPU time 19.5 seconds
Started Jun 06 01:14:04 PM PDT 24
Finished Jun 06 01:14:25 PM PDT 24
Peak memory 215332 kb
Host smart-877e9677-444a-4f53-8a09-d16a1c7d14e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572015658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2572015658
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3598352008
Short name T198
Test name
Test status
Simulation time 1180464560 ps
CPU time 20.47 seconds
Started Jun 06 01:14:14 PM PDT 24
Finished Jun 06 01:14:36 PM PDT 24
Peak memory 210840 kb
Host smart-b9ca53b7-6ad9-4407-9254-63be64dda56a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598352008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3598352008
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2638116761
Short name T323
Test name
Test status
Simulation time 167560991 ps
CPU time 8.49 seconds
Started Jun 06 01:14:21 PM PDT 24
Finished Jun 06 01:14:30 PM PDT 24
Peak memory 216756 kb
Host smart-d6d94c67-dbcb-4943-93c7-d97961f4e71d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638116761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2638116761
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3268463608
Short name T37
Test name
Test status
Simulation time 11999001828 ps
CPU time 203.28 seconds
Started Jun 06 01:14:22 PM PDT 24
Finished Jun 06 01:17:46 PM PDT 24
Peak memory 239180 kb
Host smart-bdd5b023-ca4b-4b4b-8ce2-cddc1a83669f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268463608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3268463608
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1472834856
Short name T183
Test name
Test status
Simulation time 5366051699 ps
CPU time 36.54 seconds
Started Jun 06 01:14:21 PM PDT 24
Finished Jun 06 01:14:58 PM PDT 24
Peak memory 219048 kb
Host smart-ef014a39-bc4e-4567-b6a6-502d299ce23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472834856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1472834856
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1513010298
Short name T285
Test name
Test status
Simulation time 2192325109 ps
CPU time 17.4 seconds
Started Jun 06 01:14:21 PM PDT 24
Finished Jun 06 01:14:40 PM PDT 24
Peak memory 217420 kb
Host smart-82389f13-4e00-467f-a698-3c9238e675f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513010298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1513010298
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1068879534
Short name T151
Test name
Test status
Simulation time 10785195836 ps
CPU time 54.13 seconds
Started Jun 06 01:14:21 PM PDT 24
Finished Jun 06 01:15:16 PM PDT 24
Peak memory 216996 kb
Host smart-15a30b7f-35a8-4bae-90c7-b70aa1edb385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068879534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1068879534
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2958164400
Short name T235
Test name
Test status
Simulation time 4413626743 ps
CPU time 69.68 seconds
Started Jun 06 01:14:24 PM PDT 24
Finished Jun 06 01:15:35 PM PDT 24
Peak memory 220552 kb
Host smart-cf21d79b-1635-4379-b22e-981e55180dd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958164400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2958164400
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.99151124
Short name T5
Test name
Test status
Simulation time 3143134820 ps
CPU time 18.37 seconds
Started Jun 06 01:14:22 PM PDT 24
Finished Jun 06 01:14:41 PM PDT 24
Peak memory 216804 kb
Host smart-53564e1e-b7b8-4483-8af5-b42549e36d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99151124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.99151124
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2301563398
Short name T318
Test name
Test status
Simulation time 4483063197 ps
CPU time 224.9 seconds
Started Jun 06 01:14:24 PM PDT 24
Finished Jun 06 01:18:10 PM PDT 24
Peak memory 224356 kb
Host smart-37e10da8-a9b2-4d78-b365-166499f41636
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301563398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2301563398
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2632292556
Short name T293
Test name
Test status
Simulation time 6937638897 ps
CPU time 60.98 seconds
Started Jun 06 01:14:20 PM PDT 24
Finished Jun 06 01:15:22 PM PDT 24
Peak memory 219052 kb
Host smart-ec3f160c-51a8-4d2f-b91a-4c1a23d57be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632292556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2632292556
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1805744589
Short name T193
Test name
Test status
Simulation time 11758073283 ps
CPU time 28.82 seconds
Started Jun 06 01:14:24 PM PDT 24
Finished Jun 06 01:14:54 PM PDT 24
Peak memory 217324 kb
Host smart-4871a435-a124-40e0-8647-b16ff2035a96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805744589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1805744589
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.205699118
Short name T247
Test name
Test status
Simulation time 344213202 ps
CPU time 20.27 seconds
Started Jun 06 01:14:19 PM PDT 24
Finished Jun 06 01:14:40 PM PDT 24
Peak memory 215900 kb
Host smart-0d364c00-a1d1-42ea-8f98-0bcb42f79c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205699118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.205699118
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2113310044
Short name T297
Test name
Test status
Simulation time 18416991710 ps
CPU time 163 seconds
Started Jun 06 01:14:24 PM PDT 24
Finished Jun 06 01:17:08 PM PDT 24
Peak memory 218996 kb
Host smart-1c08065f-62e3-4d63-8cb6-7643d5249936
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113310044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2113310044
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2331473244
Short name T52
Test name
Test status
Simulation time 68779189806 ps
CPU time 9733.29 seconds
Started Jun 06 01:14:22 PM PDT 24
Finished Jun 06 03:56:37 PM PDT 24
Peak memory 231864 kb
Host smart-23a8fcc9-f44c-42fc-97d6-a1552ae7810b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331473244 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2331473244
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1285590290
Short name T250
Test name
Test status
Simulation time 18789342941 ps
CPU time 29.3 seconds
Started Jun 06 01:14:24 PM PDT 24
Finished Jun 06 01:14:54 PM PDT 24
Peak memory 217012 kb
Host smart-10c42204-e27d-43ba-b070-0976a2d5cd6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285590290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1285590290
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2923852557
Short name T347
Test name
Test status
Simulation time 183539355 ps
CPU time 10.45 seconds
Started Jun 06 01:14:23 PM PDT 24
Finished Jun 06 01:14:34 PM PDT 24
Peak memory 219004 kb
Host smart-290191db-63ca-493c-a7ec-faab189963b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2923852557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2923852557
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.47696533
Short name T313
Test name
Test status
Simulation time 4706104224 ps
CPU time 54.79 seconds
Started Jun 06 01:14:21 PM PDT 24
Finished Jun 06 01:15:17 PM PDT 24
Peak memory 216384 kb
Host smart-3f6ff535-655b-4ffa-be09-3bc6743ace83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47696533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.47696533
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1292546153
Short name T278
Test name
Test status
Simulation time 30765849036 ps
CPU time 123.77 seconds
Started Jun 06 01:14:22 PM PDT 24
Finished Jun 06 01:16:26 PM PDT 24
Peak memory 219068 kb
Host smart-3fe0a27e-294a-4fd6-ab87-2af2ea6806bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292546153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1292546153
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1599671078
Short name T53
Test name
Test status
Simulation time 553604813455 ps
CPU time 2893.65 seconds
Started Jun 06 01:14:23 PM PDT 24
Finished Jun 06 02:02:37 PM PDT 24
Peak memory 244012 kb
Host smart-41df4172-69e6-4846-b298-b452fb076e66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599671078 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.1599671078
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1028073927
Short name T189
Test name
Test status
Simulation time 2287240743 ps
CPU time 22.68 seconds
Started Jun 06 01:14:30 PM PDT 24
Finished Jun 06 01:14:54 PM PDT 24
Peak memory 216980 kb
Host smart-be0c2d04-cbb9-4765-9740-f378335595d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028073927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1028073927
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2036381805
Short name T42
Test name
Test status
Simulation time 92183311718 ps
CPU time 553.08 seconds
Started Jun 06 01:14:24 PM PDT 24
Finished Jun 06 01:23:38 PM PDT 24
Peak memory 236632 kb
Host smart-2f234a93-1022-4442-904c-e2e68c1d12a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036381805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2036381805
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2456630113
Short name T16
Test name
Test status
Simulation time 12395726374 ps
CPU time 39.57 seconds
Started Jun 06 01:14:21 PM PDT 24
Finished Jun 06 01:15:01 PM PDT 24
Peak memory 219024 kb
Host smart-fae27f7d-ce64-452d-992b-e3c4ed8efe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456630113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2456630113
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3192312748
Short name T349
Test name
Test status
Simulation time 4176883642 ps
CPU time 34.67 seconds
Started Jun 06 01:14:26 PM PDT 24
Finished Jun 06 01:15:01 PM PDT 24
Peak memory 210992 kb
Host smart-3a586459-2934-4f2d-9e1f-ebf54482fdab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3192312748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3192312748
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2304964286
Short name T143
Test name
Test status
Simulation time 349585785 ps
CPU time 20.25 seconds
Started Jun 06 01:14:22 PM PDT 24
Finished Jun 06 01:14:43 PM PDT 24
Peak memory 215412 kb
Host smart-5589611f-9152-4570-ab07-0fe1d0759a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304964286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2304964286
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1349783453
Short name T22
Test name
Test status
Simulation time 1073310845 ps
CPU time 33.71 seconds
Started Jun 06 01:14:23 PM PDT 24
Finished Jun 06 01:14:57 PM PDT 24
Peak memory 218876 kb
Host smart-a57d750d-af38-44db-950b-39b8b2c1fd26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349783453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1349783453
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2412590366
Short name T210
Test name
Test status
Simulation time 11969589086 ps
CPU time 25.31 seconds
Started Jun 06 01:14:31 PM PDT 24
Finished Jun 06 01:14:58 PM PDT 24
Peak memory 216980 kb
Host smart-93aeeed2-7cad-46ca-a932-1fe2ad8c7328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412590366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2412590366
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.575667812
Short name T160
Test name
Test status
Simulation time 15752565393 ps
CPU time 189.3 seconds
Started Jun 06 01:14:34 PM PDT 24
Finished Jun 06 01:17:45 PM PDT 24
Peak memory 234980 kb
Host smart-84554b71-205a-44b4-9461-ebe1dc633c77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575667812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.575667812
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2380230296
Short name T319
Test name
Test status
Simulation time 10141164702 ps
CPU time 33.77 seconds
Started Jun 06 01:14:33 PM PDT 24
Finished Jun 06 01:15:08 PM PDT 24
Peak memory 219072 kb
Host smart-ad104ddb-0e38-4101-889b-cddc2d7a683c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380230296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2380230296
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.370466353
Short name T342
Test name
Test status
Simulation time 3505351351 ps
CPU time 29.62 seconds
Started Jun 06 01:14:34 PM PDT 24
Finished Jun 06 01:15:05 PM PDT 24
Peak memory 218996 kb
Host smart-36e53527-4693-4e4d-9d59-f41fb0b1143d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370466353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.370466353
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1576343949
Short name T90
Test name
Test status
Simulation time 34795886411 ps
CPU time 46.58 seconds
Started Jun 06 01:14:29 PM PDT 24
Finished Jun 06 01:15:16 PM PDT 24
Peak memory 216656 kb
Host smart-24f35f80-6478-4837-9d01-f0128b9552d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576343949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1576343949
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1423369974
Short name T242
Test name
Test status
Simulation time 21913221289 ps
CPU time 237.52 seconds
Started Jun 06 01:14:30 PM PDT 24
Finished Jun 06 01:18:29 PM PDT 24
Peak memory 227228 kb
Host smart-4aae5e52-642d-45bb-9558-16cc94b21faf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423369974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1423369974
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1666290924
Short name T197
Test name
Test status
Simulation time 2485175001 ps
CPU time 23.7 seconds
Started Jun 06 01:14:29 PM PDT 24
Finished Jun 06 01:14:54 PM PDT 24
Peak memory 216668 kb
Host smart-a18a1444-395d-4c33-8957-dd70a3694c97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666290924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1666290924
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3244718544
Short name T186
Test name
Test status
Simulation time 69705052777 ps
CPU time 695.41 seconds
Started Jun 06 01:14:34 PM PDT 24
Finished Jun 06 01:26:11 PM PDT 24
Peak memory 237720 kb
Host smart-8284bc64-4d6c-49d0-af5d-14686c2fdcfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244718544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3244718544
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4201818504
Short name T168
Test name
Test status
Simulation time 3625507894 ps
CPU time 35.19 seconds
Started Jun 06 01:14:29 PM PDT 24
Finished Jun 06 01:15:05 PM PDT 24
Peak memory 218948 kb
Host smart-884c509f-0776-4c79-9e2f-614eeb50ead4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201818504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4201818504
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3534951319
Short name T327
Test name
Test status
Simulation time 184320544 ps
CPU time 10.71 seconds
Started Jun 06 01:14:30 PM PDT 24
Finished Jun 06 01:14:43 PM PDT 24
Peak memory 218892 kb
Host smart-10b46e51-da80-4c32-9847-296bdfeb202f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534951319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3534951319
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.145829426
Short name T221
Test name
Test status
Simulation time 348259534 ps
CPU time 20.9 seconds
Started Jun 06 01:14:32 PM PDT 24
Finished Jun 06 01:14:54 PM PDT 24
Peak memory 215408 kb
Host smart-8c4919af-1371-4bd6-9ac4-927d24bde263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145829426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.145829426
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3710280738
Short name T145
Test name
Test status
Simulation time 35566934326 ps
CPU time 101.1 seconds
Started Jun 06 01:14:31 PM PDT 24
Finished Jun 06 01:16:14 PM PDT 24
Peak memory 220344 kb
Host smart-d65cc18b-9451-4b38-953c-a868f299a5e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710280738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3710280738
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3116659847
Short name T115
Test name
Test status
Simulation time 174570001 ps
CPU time 8.42 seconds
Started Jun 06 01:14:30 PM PDT 24
Finished Jun 06 01:14:40 PM PDT 24
Peak memory 216716 kb
Host smart-972786b1-855e-415d-9d3a-c8b653897c4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116659847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3116659847
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.688187823
Short name T267
Test name
Test status
Simulation time 7840497287 ps
CPU time 290.36 seconds
Started Jun 06 01:14:29 PM PDT 24
Finished Jun 06 01:19:20 PM PDT 24
Peak memory 219212 kb
Host smart-d60e50a0-74a2-4fc5-81dd-f0a3ace0561f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688187823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.688187823
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3299415821
Short name T322
Test name
Test status
Simulation time 8709674762 ps
CPU time 67.37 seconds
Started Jun 06 01:14:29 PM PDT 24
Finished Jun 06 01:15:38 PM PDT 24
Peak memory 218968 kb
Host smart-3b7a5691-5a60-48a4-9e07-70f18009f20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299415821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3299415821
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.340432659
Short name T180
Test name
Test status
Simulation time 1340858027 ps
CPU time 15.21 seconds
Started Jun 06 01:14:30 PM PDT 24
Finished Jun 06 01:14:47 PM PDT 24
Peak memory 218580 kb
Host smart-b6a58a4d-fe68-41b1-8e6c-62811c3ae539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=340432659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.340432659
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3813417406
Short name T204
Test name
Test status
Simulation time 7872221877 ps
CPU time 67.82 seconds
Started Jun 06 01:14:30 PM PDT 24
Finished Jun 06 01:15:40 PM PDT 24
Peak memory 216824 kb
Host smart-31c0a94a-8300-47ab-a33e-9570d050bc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813417406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3813417406
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4219849020
Short name T266
Test name
Test status
Simulation time 525792774 ps
CPU time 35.96 seconds
Started Jun 06 01:14:30 PM PDT 24
Finished Jun 06 01:15:08 PM PDT 24
Peak memory 218908 kb
Host smart-89c5c1dd-1c40-4c62-99ff-187c339d619d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219849020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4219849020
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3940702775
Short name T18
Test name
Test status
Simulation time 9470200886 ps
CPU time 371.42 seconds
Started Jun 06 01:14:34 PM PDT 24
Finished Jun 06 01:20:47 PM PDT 24
Peak memory 225988 kb
Host smart-bb7070ae-8443-4415-b356-47c05e5162e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940702775 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.3940702775
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1488825283
Short name T330
Test name
Test status
Simulation time 2806446811 ps
CPU time 24.63 seconds
Started Jun 06 01:14:34 PM PDT 24
Finished Jun 06 01:15:00 PM PDT 24
Peak memory 216772 kb
Host smart-85c5d057-2d60-43bd-904e-183ffe605557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488825283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1488825283
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3564048739
Short name T112
Test name
Test status
Simulation time 10124237053 ps
CPU time 201.62 seconds
Started Jun 06 01:14:34 PM PDT 24
Finished Jun 06 01:17:57 PM PDT 24
Peak memory 239640 kb
Host smart-0a7e0b46-fa44-48c0-a518-13928211a2df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564048739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3564048739
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1420026567
Short name T246
Test name
Test status
Simulation time 12129492243 ps
CPU time 40.81 seconds
Started Jun 06 01:14:29 PM PDT 24
Finished Jun 06 01:15:12 PM PDT 24
Peak memory 218992 kb
Host smart-bc59cd08-865b-4666-98a4-bc9d809e2e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420026567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1420026567
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.887690186
Short name T194
Test name
Test status
Simulation time 9941977719 ps
CPU time 25.26 seconds
Started Jun 06 01:14:31 PM PDT 24
Finished Jun 06 01:14:58 PM PDT 24
Peak memory 219052 kb
Host smart-c19aab99-430c-4d89-bcf8-c5c0c15f815d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887690186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.887690186
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.877265882
Short name T233
Test name
Test status
Simulation time 6202660563 ps
CPU time 30.78 seconds
Started Jun 06 01:14:28 PM PDT 24
Finished Jun 06 01:15:00 PM PDT 24
Peak memory 216504 kb
Host smart-df36a702-2673-4bed-989a-c664ff088e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877265882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.877265882
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2328118919
Short name T169
Test name
Test status
Simulation time 7517867883 ps
CPU time 25.61 seconds
Started Jun 06 01:14:30 PM PDT 24
Finished Jun 06 01:14:57 PM PDT 24
Peak memory 218944 kb
Host smart-afb2e9b3-f103-48f6-80df-1000562fb2f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328118919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2328118919
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3059304244
Short name T72
Test name
Test status
Simulation time 4406773929 ps
CPU time 12.76 seconds
Started Jun 06 01:14:33 PM PDT 24
Finished Jun 06 01:14:48 PM PDT 24
Peak memory 217004 kb
Host smart-2702288e-b6c5-4994-959b-189b6abae7f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059304244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3059304244
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1641658216
Short name T113
Test name
Test status
Simulation time 57189777686 ps
CPU time 518.89 seconds
Started Jun 06 01:14:31 PM PDT 24
Finished Jun 06 01:23:11 PM PDT 24
Peak memory 218616 kb
Host smart-3d2a3a6f-e1f9-447d-bd0a-7f513a758886
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641658216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1641658216
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.906191146
Short name T185
Test name
Test status
Simulation time 14887854642 ps
CPU time 41.21 seconds
Started Jun 06 01:14:31 PM PDT 24
Finished Jun 06 01:15:14 PM PDT 24
Peak memory 218896 kb
Host smart-28faaeb0-0348-468c-8f9e-79a944afa43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906191146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.906191146
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1125634820
Short name T220
Test name
Test status
Simulation time 3807929841 ps
CPU time 31.84 seconds
Started Jun 06 01:14:29 PM PDT 24
Finished Jun 06 01:15:02 PM PDT 24
Peak memory 219068 kb
Host smart-a1f30f60-aefa-4426-9a83-794a42bc7ddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125634820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1125634820
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2688492727
Short name T20
Test name
Test status
Simulation time 3656347996 ps
CPU time 31.9 seconds
Started Jun 06 01:14:32 PM PDT 24
Finished Jun 06 01:15:06 PM PDT 24
Peak memory 215928 kb
Host smart-596b888c-6582-4da8-b5f2-fa3b8e54c2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688492727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2688492727
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.216915176
Short name T270
Test name
Test status
Simulation time 9636982687 ps
CPU time 111.65 seconds
Started Jun 06 01:14:32 PM PDT 24
Finished Jun 06 01:16:26 PM PDT 24
Peak memory 219564 kb
Host smart-12880aea-da97-4ee2-8d66-f1dd46e1f493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216915176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.216915176
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.640943845
Short name T214
Test name
Test status
Simulation time 1312621438 ps
CPU time 16.2 seconds
Started Jun 06 01:14:40 PM PDT 24
Finished Jun 06 01:14:57 PM PDT 24
Peak memory 216724 kb
Host smart-faeb347e-c194-482f-b433-9f6bfbc6c137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640943845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.640943845
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.95908759
Short name T58
Test name
Test status
Simulation time 3418839338 ps
CPU time 242.87 seconds
Started Jun 06 01:14:39 PM PDT 24
Finished Jun 06 01:18:43 PM PDT 24
Peak memory 234540 kb
Host smart-bcbcc4ff-e5ce-4efe-95de-8625c90cddc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95908759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_co
rrupt_sig_fatal_chk.95908759
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2249811188
Short name T268
Test name
Test status
Simulation time 1269363420 ps
CPU time 19.23 seconds
Started Jun 06 01:14:37 PM PDT 24
Finished Jun 06 01:14:58 PM PDT 24
Peak memory 218916 kb
Host smart-1ff118a3-f4a0-4ee4-b58f-190b7692a0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249811188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2249811188
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3663644659
Short name T63
Test name
Test status
Simulation time 5214363934 ps
CPU time 52.48 seconds
Started Jun 06 01:14:30 PM PDT 24
Finished Jun 06 01:15:24 PM PDT 24
Peak memory 217000 kb
Host smart-89c4e9aa-d28e-4c61-9e72-b45f7c71877e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663644659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3663644659
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1407379630
Short name T89
Test name
Test status
Simulation time 17783151013 ps
CPU time 156.38 seconds
Started Jun 06 01:14:37 PM PDT 24
Finished Jun 06 01:17:14 PM PDT 24
Peak memory 220468 kb
Host smart-ace786a7-886f-4027-a6ab-18f5a35962fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407379630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1407379630
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2915880619
Short name T232
Test name
Test status
Simulation time 22480437416 ps
CPU time 28.63 seconds
Started Jun 06 01:14:03 PM PDT 24
Finished Jun 06 01:14:33 PM PDT 24
Peak memory 217060 kb
Host smart-0c3dd222-7fab-476c-ba1f-470b87f646c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915880619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2915880619
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.788558388
Short name T136
Test name
Test status
Simulation time 3016011881 ps
CPU time 129.27 seconds
Started Jun 06 01:14:04 PM PDT 24
Finished Jun 06 01:16:14 PM PDT 24
Peak memory 238180 kb
Host smart-65db8414-c134-43e5-96da-5d3c9ac7544c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788558388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.788558388
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3381516284
Short name T277
Test name
Test status
Simulation time 5872098671 ps
CPU time 56.34 seconds
Started Jun 06 01:14:02 PM PDT 24
Finished Jun 06 01:15:00 PM PDT 24
Peak memory 219084 kb
Host smart-3111935f-a014-4355-be9e-26b9fabcd888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381516284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3381516284
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2079916783
Short name T172
Test name
Test status
Simulation time 2521354601 ps
CPU time 17.42 seconds
Started Jun 06 01:14:14 PM PDT 24
Finished Jun 06 01:14:33 PM PDT 24
Peak memory 218984 kb
Host smart-f77ecf4c-de9a-42c6-96d9-215245c4e909
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2079916783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2079916783
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2288556191
Short name T29
Test name
Test status
Simulation time 2021790396 ps
CPU time 235.25 seconds
Started Jun 06 01:14:05 PM PDT 24
Finished Jun 06 01:18:02 PM PDT 24
Peak memory 235224 kb
Host smart-11b8b5da-50a5-4c0a-98d2-a632dead75c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288556191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2288556191
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.332887903
Short name T317
Test name
Test status
Simulation time 24988642968 ps
CPU time 52.33 seconds
Started Jun 06 01:14:05 PM PDT 24
Finished Jun 06 01:14:59 PM PDT 24
Peak memory 215800 kb
Host smart-0b0ffa25-9dc7-4441-b8f7-37431a9eb7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332887903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.332887903
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2846541396
Short name T282
Test name
Test status
Simulation time 1112174271 ps
CPU time 47.5 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:15:02 PM PDT 24
Peak memory 218880 kb
Host smart-ed366a10-1777-4ab1-9749-c69155b53a2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846541396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2846541396
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1134999089
Short name T173
Test name
Test status
Simulation time 98205307732 ps
CPU time 511.26 seconds
Started Jun 06 01:14:40 PM PDT 24
Finished Jun 06 01:23:12 PM PDT 24
Peak memory 218220 kb
Host smart-97b14abc-e3aa-4fb8-b286-8baaa01dc4aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134999089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1134999089
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2515823827
Short name T275
Test name
Test status
Simulation time 508810783 ps
CPU time 11.8 seconds
Started Jun 06 01:14:38 PM PDT 24
Finished Jun 06 01:14:51 PM PDT 24
Peak memory 218972 kb
Host smart-52459277-b532-4992-9c39-824d91e577ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515823827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2515823827
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3890812935
Short name T192
Test name
Test status
Simulation time 14905987132 ps
CPU time 30.66 seconds
Started Jun 06 01:14:38 PM PDT 24
Finished Jun 06 01:15:09 PM PDT 24
Peak memory 217044 kb
Host smart-6b27d687-7c3c-4d92-9534-82191ff7dae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890812935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3890812935
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2446989161
Short name T41
Test name
Test status
Simulation time 135174230786 ps
CPU time 550.78 seconds
Started Jun 06 01:14:41 PM PDT 24
Finished Jun 06 01:23:52 PM PDT 24
Peak memory 229292 kb
Host smart-d41a2fed-d968-4b93-b37a-998af93baef5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446989161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2446989161
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1961892925
Short name T188
Test name
Test status
Simulation time 10371310611 ps
CPU time 51.39 seconds
Started Jun 06 01:14:40 PM PDT 24
Finished Jun 06 01:15:33 PM PDT 24
Peak memory 218740 kb
Host smart-59d099be-d23d-499c-b39e-fa867f0644c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961892925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1961892925
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.316185870
Short name T252
Test name
Test status
Simulation time 4129375440 ps
CPU time 22.72 seconds
Started Jun 06 01:14:36 PM PDT 24
Finished Jun 06 01:15:00 PM PDT 24
Peak memory 219024 kb
Host smart-1af0d44d-3822-462d-b1fd-ae91bbc5cce4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=316185870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.316185870
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2827642716
Short name T181
Test name
Test status
Simulation time 3361605988 ps
CPU time 19.85 seconds
Started Jun 06 01:14:39 PM PDT 24
Finished Jun 06 01:15:00 PM PDT 24
Peak memory 216500 kb
Host smart-59cdaedb-9d1b-42a5-a1ed-bc61aba14fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827642716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2827642716
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3245538042
Short name T256
Test name
Test status
Simulation time 13378726312 ps
CPU time 109.87 seconds
Started Jun 06 01:14:37 PM PDT 24
Finished Jun 06 01:16:28 PM PDT 24
Peak memory 221148 kb
Host smart-b12445c2-8e40-44ee-8e3f-4bfa3a382386
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245538042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3245538042
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.726797320
Short name T312
Test name
Test status
Simulation time 686750986 ps
CPU time 12.8 seconds
Started Jun 06 01:14:38 PM PDT 24
Finished Jun 06 01:14:52 PM PDT 24
Peak memory 216708 kb
Host smart-decc9e8a-50f1-4ea2-aaa1-5f4b9d79184c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726797320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.726797320
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1314170298
Short name T273
Test name
Test status
Simulation time 34120088009 ps
CPU time 380.82 seconds
Started Jun 06 01:14:38 PM PDT 24
Finished Jun 06 01:21:00 PM PDT 24
Peak memory 234620 kb
Host smart-8a73bd5b-c885-461e-948d-1257387225d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314170298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1314170298
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.888005666
Short name T227
Test name
Test status
Simulation time 10496686581 ps
CPU time 66.39 seconds
Started Jun 06 01:14:40 PM PDT 24
Finished Jun 06 01:15:47 PM PDT 24
Peak memory 219076 kb
Host smart-f5fd53cc-2197-4ee4-a444-c43febfc1956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888005666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.888005666
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.670514574
Short name T241
Test name
Test status
Simulation time 16793236441 ps
CPU time 34.54 seconds
Started Jun 06 01:14:39 PM PDT 24
Finished Jun 06 01:15:15 PM PDT 24
Peak memory 217296 kb
Host smart-308df0d3-6048-426b-acdf-2e5b6b6ddddb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670514574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.670514574
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.4161747503
Short name T326
Test name
Test status
Simulation time 360302544 ps
CPU time 19.78 seconds
Started Jun 06 01:14:38 PM PDT 24
Finished Jun 06 01:14:59 PM PDT 24
Peak memory 215900 kb
Host smart-166aea35-1bc9-48fa-9b0a-36c7269a78d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161747503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.4161747503
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2032742474
Short name T292
Test name
Test status
Simulation time 3498152273 ps
CPU time 46.79 seconds
Started Jun 06 01:14:39 PM PDT 24
Finished Jun 06 01:15:27 PM PDT 24
Peak memory 218452 kb
Host smart-bcb27107-a397-4f5a-bbca-29f2175c5282
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032742474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2032742474
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3532259642
Short name T304
Test name
Test status
Simulation time 1121407523 ps
CPU time 9.55 seconds
Started Jun 06 01:14:49 PM PDT 24
Finished Jun 06 01:15:00 PM PDT 24
Peak memory 216492 kb
Host smart-2240a0d7-dfc3-4f71-b92b-2a690fbce8a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532259642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3532259642
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.779614455
Short name T324
Test name
Test status
Simulation time 68253613719 ps
CPU time 264.64 seconds
Started Jun 06 01:14:49 PM PDT 24
Finished Jun 06 01:19:15 PM PDT 24
Peak memory 235940 kb
Host smart-4bd5f6ae-fc86-4bee-a3ee-aeafcac73cf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779614455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.779614455
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2799530969
Short name T226
Test name
Test status
Simulation time 6164938889 ps
CPU time 54.44 seconds
Started Jun 06 01:14:48 PM PDT 24
Finished Jun 06 01:15:43 PM PDT 24
Peak memory 219052 kb
Host smart-0ae61043-0110-4875-bd8c-b2f2e863d139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799530969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2799530969
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1809564962
Short name T237
Test name
Test status
Simulation time 2569456927 ps
CPU time 26.83 seconds
Started Jun 06 01:14:47 PM PDT 24
Finished Jun 06 01:15:16 PM PDT 24
Peak memory 219040 kb
Host smart-0bd42f85-02b7-45c1-a1de-9830d5ea9816
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809564962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1809564962
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3506238323
Short name T243
Test name
Test status
Simulation time 3088173858 ps
CPU time 41.31 seconds
Started Jun 06 01:14:41 PM PDT 24
Finished Jun 06 01:15:23 PM PDT 24
Peak memory 215508 kb
Host smart-2a53bc7b-de9a-468f-be71-d39a6ca2c139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506238323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3506238323
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.586228562
Short name T152
Test name
Test status
Simulation time 1740230486 ps
CPU time 33.59 seconds
Started Jun 06 01:14:47 PM PDT 24
Finished Jun 06 01:15:22 PM PDT 24
Peak memory 218148 kb
Host smart-0822aa33-fa1b-4c15-98f5-8dbfd8a48420
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586228562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.586228562
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.879404559
Short name T301
Test name
Test status
Simulation time 3294452154 ps
CPU time 28.87 seconds
Started Jun 06 01:14:48 PM PDT 24
Finished Jun 06 01:15:19 PM PDT 24
Peak memory 216772 kb
Host smart-f92173b8-1a60-42b0-8894-0e3f4c177b9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879404559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.879404559
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.702629946
Short name T263
Test name
Test status
Simulation time 3295236341 ps
CPU time 19.58 seconds
Started Jun 06 01:14:48 PM PDT 24
Finished Jun 06 01:15:09 PM PDT 24
Peak memory 218968 kb
Host smart-cf2b07d1-1747-4c18-ae99-9581623b6ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702629946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.702629946
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2061764482
Short name T32
Test name
Test status
Simulation time 2574807557 ps
CPU time 25.58 seconds
Started Jun 06 01:14:48 PM PDT 24
Finished Jun 06 01:15:15 PM PDT 24
Peak memory 219008 kb
Host smart-036da144-660b-45a3-aeb7-e187342c9804
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2061764482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2061764482
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.186297068
Short name T93
Test name
Test status
Simulation time 2081997720 ps
CPU time 28.13 seconds
Started Jun 06 01:14:50 PM PDT 24
Finished Jun 06 01:15:19 PM PDT 24
Peak memory 215508 kb
Host smart-adceb7ef-6196-4eb8-9d49-4cef48ee3a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186297068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.186297068
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1897526834
Short name T352
Test name
Test status
Simulation time 16395221325 ps
CPU time 35.75 seconds
Started Jun 06 01:14:50 PM PDT 24
Finished Jun 06 01:15:27 PM PDT 24
Peak memory 214132 kb
Host smart-d2730622-777c-4bf7-b791-8a5a2482b07a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897526834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1897526834
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3258054528
Short name T26
Test name
Test status
Simulation time 3774269241 ps
CPU time 17.84 seconds
Started Jun 06 01:14:47 PM PDT 24
Finished Jun 06 01:15:06 PM PDT 24
Peak memory 216648 kb
Host smart-894e7534-97f7-4343-972b-0123ec29bee3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258054528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3258054528
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1538854727
Short name T39
Test name
Test status
Simulation time 54878853392 ps
CPU time 601.53 seconds
Started Jun 06 01:14:48 PM PDT 24
Finished Jun 06 01:24:52 PM PDT 24
Peak memory 225356 kb
Host smart-67b337e5-e525-4edf-855d-9bccc5b360bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538854727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1538854727
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.411840852
Short name T291
Test name
Test status
Simulation time 7006823406 ps
CPU time 41.79 seconds
Started Jun 06 01:14:47 PM PDT 24
Finished Jun 06 01:15:30 PM PDT 24
Peak memory 219072 kb
Host smart-82d26ffe-04f1-45b3-93d4-fb9798e8c12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411840852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.411840852
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2374620561
Short name T328
Test name
Test status
Simulation time 17506525941 ps
CPU time 35.14 seconds
Started Jun 06 01:14:48 PM PDT 24
Finished Jun 06 01:15:25 PM PDT 24
Peak memory 217480 kb
Host smart-78dd7642-5b6e-4c29-8975-60d0850338a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2374620561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2374620561
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1640490919
Short name T92
Test name
Test status
Simulation time 361648633 ps
CPU time 20.41 seconds
Started Jun 06 01:14:49 PM PDT 24
Finished Jun 06 01:15:11 PM PDT 24
Peak memory 217068 kb
Host smart-ade35bfe-9f70-4d81-ba76-a3d82a981b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640490919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1640490919
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3000878809
Short name T205
Test name
Test status
Simulation time 37935080828 ps
CPU time 141.8 seconds
Started Jun 06 01:14:49 PM PDT 24
Finished Jun 06 01:17:12 PM PDT 24
Peak memory 221184 kb
Host smart-72113b08-1b48-4af8-a171-da0661db0367
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000878809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3000878809
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2981989031
Short name T196
Test name
Test status
Simulation time 5471575149 ps
CPU time 27.18 seconds
Started Jun 06 01:14:47 PM PDT 24
Finished Jun 06 01:15:16 PM PDT 24
Peak memory 217060 kb
Host smart-5aa7d9cc-39b1-40aa-bcfc-fec8b3681c8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981989031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2981989031
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1746706041
Short name T356
Test name
Test status
Simulation time 204947811263 ps
CPU time 479.73 seconds
Started Jun 06 01:14:48 PM PDT 24
Finished Jun 06 01:22:49 PM PDT 24
Peak memory 226420 kb
Host smart-35f352b5-deb6-4843-bfd4-66128ba4e9ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746706041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1746706041
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3702160433
Short name T48
Test name
Test status
Simulation time 346296147 ps
CPU time 19.31 seconds
Started Jun 06 01:14:48 PM PDT 24
Finished Jun 06 01:15:09 PM PDT 24
Peak memory 218872 kb
Host smart-445a2d75-2ffc-4a4b-9006-fd5ba5402c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702160433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3702160433
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4268154102
Short name T251
Test name
Test status
Simulation time 1399688924 ps
CPU time 19.89 seconds
Started Jun 06 01:14:47 PM PDT 24
Finished Jun 06 01:15:08 PM PDT 24
Peak memory 211348 kb
Host smart-ed0eb961-3e9d-4790-bfc2-f5ebaef95634
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268154102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4268154102
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.14625466
Short name T190
Test name
Test status
Simulation time 736592837 ps
CPU time 19.71 seconds
Started Jun 06 01:14:47 PM PDT 24
Finished Jun 06 01:15:08 PM PDT 24
Peak memory 215376 kb
Host smart-9ffac4e1-3b01-4097-94fc-98a5758053b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14625466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.14625466
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.904397009
Short name T216
Test name
Test status
Simulation time 3581187860 ps
CPU time 51.15 seconds
Started Jun 06 01:14:48 PM PDT 24
Finished Jun 06 01:15:41 PM PDT 24
Peak memory 218976 kb
Host smart-85bb9a0c-05de-47bd-9e9f-d0372ca517cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904397009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.904397009
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3898758714
Short name T208
Test name
Test status
Simulation time 21343339871 ps
CPU time 21.91 seconds
Started Jun 06 01:14:57 PM PDT 24
Finished Jun 06 01:15:20 PM PDT 24
Peak memory 217184 kb
Host smart-886c9d61-5921-4c4a-8e41-08884114fcd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898758714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3898758714
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3187889897
Short name T40
Test name
Test status
Simulation time 187501098917 ps
CPU time 555.29 seconds
Started Jun 06 01:14:59 PM PDT 24
Finished Jun 06 01:24:15 PM PDT 24
Peak memory 233396 kb
Host smart-54a5432f-c1d4-40f4-b23d-54d519f57c01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187889897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3187889897
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.861134923
Short name T231
Test name
Test status
Simulation time 5717522158 ps
CPU time 37.37 seconds
Started Jun 06 01:14:57 PM PDT 24
Finished Jun 06 01:15:36 PM PDT 24
Peak memory 218976 kb
Host smart-5621bf2c-0629-4966-aea9-d5012df2a720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861134923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.861134923
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3404724151
Short name T355
Test name
Test status
Simulation time 4103340661 ps
CPU time 32.99 seconds
Started Jun 06 01:14:58 PM PDT 24
Finished Jun 06 01:15:32 PM PDT 24
Peak memory 219012 kb
Host smart-a25b7509-b079-48c7-b67f-8b2a3532d04d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3404724151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3404724151
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2646268217
Short name T271
Test name
Test status
Simulation time 6645639296 ps
CPU time 46.76 seconds
Started Jun 06 01:14:49 PM PDT 24
Finished Jun 06 01:15:37 PM PDT 24
Peak memory 216620 kb
Host smart-b2afd60b-3268-46a3-8733-a07b42444502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646268217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2646268217
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.379987296
Short name T8
Test name
Test status
Simulation time 6041556967 ps
CPU time 18.69 seconds
Started Jun 06 01:14:50 PM PDT 24
Finished Jun 06 01:15:09 PM PDT 24
Peak memory 214172 kb
Host smart-eef0a8a6-d778-4f25-92e1-fef50accbed1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379987296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.379987296
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.919457469
Short name T74
Test name
Test status
Simulation time 8185887366 ps
CPU time 33.3 seconds
Started Jun 06 01:15:01 PM PDT 24
Finished Jun 06 01:15:35 PM PDT 24
Peak memory 217000 kb
Host smart-308e3b9b-18bd-4395-894b-6282e0097dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919457469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.919457469
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3023110205
Short name T280
Test name
Test status
Simulation time 42378251587 ps
CPU time 534.69 seconds
Started Jun 06 01:14:58 PM PDT 24
Finished Jun 06 01:23:54 PM PDT 24
Peak memory 233568 kb
Host smart-b455a9e7-0230-4bc4-bf03-42af7ab17b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023110205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3023110205
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3379333618
Short name T206
Test name
Test status
Simulation time 1376383121 ps
CPU time 19.66 seconds
Started Jun 06 01:14:58 PM PDT 24
Finished Jun 06 01:15:19 PM PDT 24
Peak memory 219144 kb
Host smart-6f162e49-67ea-423a-a807-daa628e17b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379333618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3379333618
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3921687664
Short name T202
Test name
Test status
Simulation time 182473145 ps
CPU time 10.48 seconds
Started Jun 06 01:14:58 PM PDT 24
Finished Jun 06 01:15:09 PM PDT 24
Peak memory 218980 kb
Host smart-ac252486-8139-4bf4-915d-521dedc4a6c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3921687664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3921687664
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1800545444
Short name T219
Test name
Test status
Simulation time 16412305242 ps
CPU time 48.64 seconds
Started Jun 06 01:14:59 PM PDT 24
Finished Jun 06 01:15:48 PM PDT 24
Peak memory 215912 kb
Host smart-02f42dab-1d1a-4c70-bb61-f4b324415fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800545444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1800545444
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3750733753
Short name T335
Test name
Test status
Simulation time 2549975198 ps
CPU time 31.61 seconds
Started Jun 06 01:14:58 PM PDT 24
Finished Jun 06 01:15:30 PM PDT 24
Peak memory 218880 kb
Host smart-19bdbd50-5279-47fd-9569-647f529269b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750733753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3750733753
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1153195133
Short name T284
Test name
Test status
Simulation time 1226667969 ps
CPU time 11.9 seconds
Started Jun 06 01:14:59 PM PDT 24
Finished Jun 06 01:15:12 PM PDT 24
Peak memory 216708 kb
Host smart-f55d2e4e-e483-4f95-a802-b0e89485195a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153195133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1153195133
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.193586725
Short name T45
Test name
Test status
Simulation time 162695883645 ps
CPU time 488.6 seconds
Started Jun 06 01:14:57 PM PDT 24
Finished Jun 06 01:23:07 PM PDT 24
Peak memory 237728 kb
Host smart-31e54112-2edf-4a96-ac4c-64821663a5ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193586725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.193586725
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.807409278
Short name T27
Test name
Test status
Simulation time 5142448529 ps
CPU time 49.47 seconds
Started Jun 06 01:15:04 PM PDT 24
Finished Jun 06 01:15:55 PM PDT 24
Peak memory 218964 kb
Host smart-fbafecd4-ec41-498d-afa1-85c2da698491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807409278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.807409278
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4109564674
Short name T289
Test name
Test status
Simulation time 2227476839 ps
CPU time 23.11 seconds
Started Jun 06 01:15:00 PM PDT 24
Finished Jun 06 01:15:24 PM PDT 24
Peak memory 218968 kb
Host smart-65dc91a7-9d66-44df-9006-2da371553cab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4109564674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4109564674
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1171928553
Short name T295
Test name
Test status
Simulation time 3188159485 ps
CPU time 44.4 seconds
Started Jun 06 01:14:59 PM PDT 24
Finished Jun 06 01:15:44 PM PDT 24
Peak memory 215616 kb
Host smart-0a28706a-def1-482e-a683-85f29e308216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171928553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1171928553
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2253430828
Short name T309
Test name
Test status
Simulation time 4301889471 ps
CPU time 44.82 seconds
Started Jun 06 01:14:59 PM PDT 24
Finished Jun 06 01:15:45 PM PDT 24
Peak memory 216640 kb
Host smart-1d0304a6-bd16-4ef8-9569-fecfcaa00610
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253430828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2253430828
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.930233317
Short name T287
Test name
Test status
Simulation time 1201399358 ps
CPU time 16.2 seconds
Started Jun 06 01:14:12 PM PDT 24
Finished Jun 06 01:14:29 PM PDT 24
Peak memory 216592 kb
Host smart-8fb7c194-98f7-4c2b-a4fa-b4cb5c75bbd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930233317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.930233317
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.384321322
Short name T44
Test name
Test status
Simulation time 4102902333 ps
CPU time 284.96 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:18:59 PM PDT 24
Peak memory 234544 kb
Host smart-0d3d2a06-b685-49e6-9045-a522dcbf646d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384321322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.384321322
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1679803225
Short name T175
Test name
Test status
Simulation time 21039310999 ps
CPU time 50.54 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:15:05 PM PDT 24
Peak memory 218784 kb
Host smart-53a8c5fa-2cbd-43c3-a644-83a8ebdac689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679803225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1679803225
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.286651347
Short name T34
Test name
Test status
Simulation time 2457815517 ps
CPU time 10.56 seconds
Started Jun 06 01:14:04 PM PDT 24
Finished Jun 06 01:14:16 PM PDT 24
Peak memory 219276 kb
Host smart-9261c43a-f3cd-41ff-936e-9e044e5a4d98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286651347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.286651347
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2390361124
Short name T24
Test name
Test status
Simulation time 1570653694 ps
CPU time 221.56 seconds
Started Jun 06 01:14:15 PM PDT 24
Finished Jun 06 01:17:58 PM PDT 24
Peak memory 236016 kb
Host smart-b1e74ccb-51cd-40d5-b367-88f0c79602e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390361124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2390361124
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1690338034
Short name T12
Test name
Test status
Simulation time 5928031405 ps
CPU time 53.08 seconds
Started Jun 06 01:14:14 PM PDT 24
Finished Jun 06 01:15:08 PM PDT 24
Peak memory 216160 kb
Host smart-5a2baf8a-8ad5-45ad-b91e-5cd65147fadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690338034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1690338034
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.4086821108
Short name T71
Test name
Test status
Simulation time 4221832040 ps
CPU time 33.75 seconds
Started Jun 06 01:15:03 PM PDT 24
Finished Jun 06 01:15:38 PM PDT 24
Peak memory 216736 kb
Host smart-f9bf566d-281d-4f12-8af3-ec4da3ac092c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086821108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.4086821108
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1801210387
Short name T325
Test name
Test status
Simulation time 945089473969 ps
CPU time 1374.56 seconds
Started Jun 06 01:14:58 PM PDT 24
Finished Jun 06 01:37:54 PM PDT 24
Peak memory 225120 kb
Host smart-b86776f9-efb2-4a65-ad7d-3e027354da08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801210387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1801210387
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3105668879
Short name T217
Test name
Test status
Simulation time 10651696550 ps
CPU time 52.23 seconds
Started Jun 06 01:14:57 PM PDT 24
Finished Jun 06 01:15:51 PM PDT 24
Peak memory 219008 kb
Host smart-da52382b-8037-4136-b953-4b2f29f7be03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105668879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3105668879
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2749284885
Short name T124
Test name
Test status
Simulation time 2761471104 ps
CPU time 14.94 seconds
Started Jun 06 01:15:04 PM PDT 24
Finished Jun 06 01:15:19 PM PDT 24
Peak memory 218396 kb
Host smart-cf059a80-d5e3-4941-b05d-6bd3499964ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2749284885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2749284885
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1943368821
Short name T64
Test name
Test status
Simulation time 16368888635 ps
CPU time 39.05 seconds
Started Jun 06 01:14:58 PM PDT 24
Finished Jun 06 01:15:39 PM PDT 24
Peak memory 216604 kb
Host smart-2aeb9de0-7d8d-4809-86a1-b51153f899a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943368821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1943368821
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.117981996
Short name T341
Test name
Test status
Simulation time 75896058239 ps
CPU time 183.09 seconds
Started Jun 06 01:14:58 PM PDT 24
Finished Jun 06 01:18:02 PM PDT 24
Peak memory 220608 kb
Host smart-375cee57-6ed4-4e94-b9e0-0d2b02e5a322
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117981996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.117981996
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2002392006
Short name T234
Test name
Test status
Simulation time 13621832667 ps
CPU time 28.47 seconds
Started Jun 06 01:15:07 PM PDT 24
Finished Jun 06 01:15:36 PM PDT 24
Peak memory 217080 kb
Host smart-d776080a-a5b8-4f7d-b7d9-8ec4ec01b7a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002392006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2002392006
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2383298145
Short name T279
Test name
Test status
Simulation time 48021259914 ps
CPU time 446.93 seconds
Started Jun 06 01:15:06 PM PDT 24
Finished Jun 06 01:22:34 PM PDT 24
Peak memory 224476 kb
Host smart-ba66d5f5-a125-49a5-a5b0-a733c0ca2200
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383298145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2383298145
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2146420678
Short name T171
Test name
Test status
Simulation time 6129499244 ps
CPU time 29.85 seconds
Started Jun 06 01:15:11 PM PDT 24
Finished Jun 06 01:15:42 PM PDT 24
Peak memory 219064 kb
Host smart-450f0c61-b277-4813-9d74-35acd5e2e863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146420678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2146420678
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3176508114
Short name T345
Test name
Test status
Simulation time 483471406 ps
CPU time 10.26 seconds
Started Jun 06 01:15:06 PM PDT 24
Finished Jun 06 01:15:17 PM PDT 24
Peak memory 218960 kb
Host smart-32905d20-1a88-4a80-8caa-71de689b5c45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176508114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3176508114
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1454958913
Short name T257
Test name
Test status
Simulation time 16401417055 ps
CPU time 74.7 seconds
Started Jun 06 01:15:12 PM PDT 24
Finished Jun 06 01:16:27 PM PDT 24
Peak memory 215992 kb
Host smart-e5c5e8c9-64c0-4a5f-bdc7-542058e5a200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454958913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1454958913
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2947351829
Short name T199
Test name
Test status
Simulation time 1225768529 ps
CPU time 32.29 seconds
Started Jun 06 01:15:05 PM PDT 24
Finished Jun 06 01:15:38 PM PDT 24
Peak memory 218904 kb
Host smart-82360083-9001-49e5-8e18-8febb064600d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947351829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2947351829
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1672053909
Short name T351
Test name
Test status
Simulation time 16421956505 ps
CPU time 33.36 seconds
Started Jun 06 01:15:09 PM PDT 24
Finished Jun 06 01:15:44 PM PDT 24
Peak memory 217180 kb
Host smart-49386243-d9c7-4867-ab05-96143d2e4bae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672053909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1672053909
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2967583255
Short name T272
Test name
Test status
Simulation time 46496279942 ps
CPU time 410.09 seconds
Started Jun 06 01:15:04 PM PDT 24
Finished Jun 06 01:21:55 PM PDT 24
Peak memory 229312 kb
Host smart-a9f2014f-ab63-465d-9ca5-83e9ffaa0f4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967583255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2967583255
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.287597864
Short name T3
Test name
Test status
Simulation time 2934435154 ps
CPU time 25.64 seconds
Started Jun 06 01:15:09 PM PDT 24
Finished Jun 06 01:15:35 PM PDT 24
Peak memory 218476 kb
Host smart-865d697a-1843-404a-9166-737fe3f63711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287597864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.287597864
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2817657865
Short name T138
Test name
Test status
Simulation time 6515064212 ps
CPU time 28.6 seconds
Started Jun 06 01:15:12 PM PDT 24
Finished Jun 06 01:15:42 PM PDT 24
Peak memory 217456 kb
Host smart-3c170c19-2f4f-4a73-9bf5-668384955162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2817657865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2817657865
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1068940859
Short name T184
Test name
Test status
Simulation time 719014168 ps
CPU time 28.62 seconds
Started Jun 06 01:15:08 PM PDT 24
Finished Jun 06 01:15:37 PM PDT 24
Peak memory 216344 kb
Host smart-d7792687-f90d-45d5-a276-a5fa101a894d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068940859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1068940859
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1262599287
Short name T7
Test name
Test status
Simulation time 661842537 ps
CPU time 8.35 seconds
Started Jun 06 01:15:18 PM PDT 24
Finished Jun 06 01:15:28 PM PDT 24
Peak memory 216740 kb
Host smart-ea3d7f5c-e99d-4acb-a84a-af11d4b13fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262599287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1262599287
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3653875477
Short name T176
Test name
Test status
Simulation time 63125938775 ps
CPU time 706.33 seconds
Started Jun 06 01:15:14 PM PDT 24
Finished Jun 06 01:27:02 PM PDT 24
Peak memory 235032 kb
Host smart-15bf542c-f4f1-4819-a881-748f38958fcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653875477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3653875477
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1085314500
Short name T170
Test name
Test status
Simulation time 17622105729 ps
CPU time 34.39 seconds
Started Jun 06 01:15:19 PM PDT 24
Finished Jun 06 01:15:55 PM PDT 24
Peak memory 219064 kb
Host smart-619756f6-8bf6-442e-8e48-20118af31879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085314500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1085314500
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3059968465
Short name T230
Test name
Test status
Simulation time 11590776699 ps
CPU time 26.79 seconds
Started Jun 06 01:15:16 PM PDT 24
Finished Jun 06 01:15:44 PM PDT 24
Peak memory 217452 kb
Host smart-6c5226c4-4ff2-46bb-8d42-5755aa12f247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3059968465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3059968465
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2084007384
Short name T261
Test name
Test status
Simulation time 4786040552 ps
CPU time 49.28 seconds
Started Jun 06 01:15:06 PM PDT 24
Finished Jun 06 01:15:56 PM PDT 24
Peak memory 216496 kb
Host smart-3e5a1169-46e2-43e4-9127-26f320fa934e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084007384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2084007384
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4292026785
Short name T337
Test name
Test status
Simulation time 43932910613 ps
CPU time 131.54 seconds
Started Jun 06 01:15:06 PM PDT 24
Finished Jun 06 01:17:19 PM PDT 24
Peak memory 219732 kb
Host smart-b87fbe56-9c79-49b7-a211-486ebf69323c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292026785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4292026785
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.246146047
Short name T19
Test name
Test status
Simulation time 176785642673 ps
CPU time 1658.07 seconds
Started Jun 06 01:15:16 PM PDT 24
Finished Jun 06 01:42:55 PM PDT 24
Peak memory 238340 kb
Host smart-2f4f79ba-4ce9-4f73-97d4-dba67f496540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246146047 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.246146047
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.382245991
Short name T303
Test name
Test status
Simulation time 497144292 ps
CPU time 10.11 seconds
Started Jun 06 01:15:17 PM PDT 24
Finished Jun 06 01:15:28 PM PDT 24
Peak memory 216588 kb
Host smart-c7d70dd7-652b-44cb-876e-4ac2c4688083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382245991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.382245991
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.494586055
Short name T157
Test name
Test status
Simulation time 73580257789 ps
CPU time 392.15 seconds
Started Jun 06 01:15:16 PM PDT 24
Finished Jun 06 01:21:49 PM PDT 24
Peak memory 219200 kb
Host smart-89dcd482-0b4f-4e76-ab8b-992ecc609774
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494586055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.494586055
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.724087087
Short name T354
Test name
Test status
Simulation time 10456060391 ps
CPU time 51.18 seconds
Started Jun 06 01:15:16 PM PDT 24
Finished Jun 06 01:16:08 PM PDT 24
Peak memory 219024 kb
Host smart-cdcaf7df-db8e-4263-8d38-fca0c477fe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724087087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.724087087
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.388520138
Short name T177
Test name
Test status
Simulation time 7140891974 ps
CPU time 30.09 seconds
Started Jun 06 01:15:16 PM PDT 24
Finished Jun 06 01:15:47 PM PDT 24
Peak memory 219120 kb
Host smart-5c146f26-5151-40a9-807b-d87a274d7e17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=388520138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.388520138
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2392158284
Short name T215
Test name
Test status
Simulation time 7386783186 ps
CPU time 44.31 seconds
Started Jun 06 01:15:14 PM PDT 24
Finished Jun 06 01:16:00 PM PDT 24
Peak memory 216744 kb
Host smart-6c841592-cf65-42ff-949a-5c782d918da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392158284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2392158284
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1645908479
Short name T9
Test name
Test status
Simulation time 22752943891 ps
CPU time 76.46 seconds
Started Jun 06 01:15:17 PM PDT 24
Finished Jun 06 01:16:35 PM PDT 24
Peak memory 218464 kb
Host smart-c1ddcf87-1f9f-4c99-a60b-d354f10dfe05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645908479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1645908479
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.564692806
Short name T30
Test name
Test status
Simulation time 2702224238 ps
CPU time 24.2 seconds
Started Jun 06 01:15:30 PM PDT 24
Finished Jun 06 01:15:55 PM PDT 24
Peak memory 216688 kb
Host smart-4c39a9b0-22a9-4a86-bda0-51fa50b10a02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564692806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.564692806
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2542010699
Short name T43
Test name
Test status
Simulation time 38391157015 ps
CPU time 286.94 seconds
Started Jun 06 01:15:16 PM PDT 24
Finished Jun 06 01:20:04 PM PDT 24
Peak memory 242416 kb
Host smart-b5119569-9c2f-4f16-bf64-8beafb121629
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542010699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2542010699
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.750089035
Short name T305
Test name
Test status
Simulation time 675063040 ps
CPU time 19.07 seconds
Started Jun 06 01:15:16 PM PDT 24
Finished Jun 06 01:15:37 PM PDT 24
Peak memory 218920 kb
Host smart-fdc50412-0f95-483b-a57e-d1724ef87eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750089035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.750089035
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4064212582
Short name T137
Test name
Test status
Simulation time 17146717693 ps
CPU time 33.03 seconds
Started Jun 06 01:15:17 PM PDT 24
Finished Jun 06 01:15:51 PM PDT 24
Peak memory 219136 kb
Host smart-2d4db83c-e2d8-4c18-8f1c-ed01dbee60e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4064212582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4064212582
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1749647418
Short name T300
Test name
Test status
Simulation time 1381245819 ps
CPU time 31.08 seconds
Started Jun 06 01:15:15 PM PDT 24
Finished Jun 06 01:15:48 PM PDT 24
Peak memory 215576 kb
Host smart-1105730f-675d-4b73-b960-82264b4e330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749647418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1749647418
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2172963813
Short name T94
Test name
Test status
Simulation time 20733898028 ps
CPU time 111.28 seconds
Started Jun 06 01:15:16 PM PDT 24
Finished Jun 06 01:17:08 PM PDT 24
Peak memory 219676 kb
Host smart-86c20b80-1e53-482b-8574-64831e0eccd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172963813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2172963813
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1962522304
Short name T174
Test name
Test status
Simulation time 1124877928 ps
CPU time 15.25 seconds
Started Jun 06 01:15:28 PM PDT 24
Finished Jun 06 01:15:44 PM PDT 24
Peak memory 216536 kb
Host smart-13d5bc50-c730-4cbd-bf5d-7b39f9a2fdb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962522304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1962522304
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4068348149
Short name T1
Test name
Test status
Simulation time 15568377971 ps
CPU time 219 seconds
Started Jun 06 01:15:27 PM PDT 24
Finished Jun 06 01:19:07 PM PDT 24
Peak memory 237028 kb
Host smart-82b68f09-e318-4b77-8dfa-cb9bcd6e0f51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068348149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4068348149
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.216955536
Short name T46
Test name
Test status
Simulation time 1376671706 ps
CPU time 19.7 seconds
Started Jun 06 01:15:27 PM PDT 24
Finished Jun 06 01:15:48 PM PDT 24
Peak memory 218876 kb
Host smart-cc6e84b3-586e-4a06-af8d-765bbf21bda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216955536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.216955536
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.107600220
Short name T14
Test name
Test status
Simulation time 3063380918 ps
CPU time 29.74 seconds
Started Jun 06 01:15:26 PM PDT 24
Finished Jun 06 01:15:57 PM PDT 24
Peak memory 219108 kb
Host smart-5ca8a1c2-39f9-414d-a4f9-a5008372a006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107600220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.107600220
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2956339254
Short name T187
Test name
Test status
Simulation time 5764836309 ps
CPU time 65.38 seconds
Started Jun 06 01:15:25 PM PDT 24
Finished Jun 06 01:16:31 PM PDT 24
Peak memory 216132 kb
Host smart-e18c0468-d4df-4671-9637-37965dab749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956339254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2956339254
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.672957394
Short name T91
Test name
Test status
Simulation time 1386762220 ps
CPU time 37.13 seconds
Started Jun 06 01:15:26 PM PDT 24
Finished Jun 06 01:16:05 PM PDT 24
Peak memory 218884 kb
Host smart-665c636a-fdd3-4772-b396-f5d1f31d585a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672957394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.672957394
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2683627268
Short name T182
Test name
Test status
Simulation time 2480806448 ps
CPU time 22.47 seconds
Started Jun 06 01:15:26 PM PDT 24
Finished Jun 06 01:15:50 PM PDT 24
Peak memory 216604 kb
Host smart-edd6b4ce-411c-4135-9a1b-b113af8ffa0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683627268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2683627268
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.356054282
Short name T286
Test name
Test status
Simulation time 10670189129 ps
CPU time 186 seconds
Started Jun 06 01:15:27 PM PDT 24
Finished Jun 06 01:18:34 PM PDT 24
Peak memory 218256 kb
Host smart-110cd6c4-e12b-402d-9be9-fe354c468272
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356054282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.356054282
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.556559929
Short name T164
Test name
Test status
Simulation time 2016825850 ps
CPU time 31.91 seconds
Started Jun 06 01:15:53 PM PDT 24
Finished Jun 06 01:16:25 PM PDT 24
Peak memory 218924 kb
Host smart-81d2aac3-0496-4f75-bf47-4a063d519012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556559929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.556559929
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3763841366
Short name T139
Test name
Test status
Simulation time 401796854 ps
CPU time 12.68 seconds
Started Jun 06 01:15:26 PM PDT 24
Finished Jun 06 01:15:40 PM PDT 24
Peak memory 218500 kb
Host smart-95ec852e-1104-4791-9857-f49f1b3b318b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3763841366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3763841366
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2874019833
Short name T315
Test name
Test status
Simulation time 2036301168 ps
CPU time 27.2 seconds
Started Jun 06 01:15:26 PM PDT 24
Finished Jun 06 01:15:54 PM PDT 24
Peak memory 215932 kb
Host smart-c643e9b1-9427-47d9-b0dc-cadd4c6c7c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874019833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2874019833
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3803960381
Short name T225
Test name
Test status
Simulation time 23114873744 ps
CPU time 96.8 seconds
Started Jun 06 01:15:25 PM PDT 24
Finished Jun 06 01:17:03 PM PDT 24
Peak memory 219044 kb
Host smart-229e47f1-60ab-46ae-9cf5-13d80c3b471b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803960381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3803960381
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2615260229
Short name T114
Test name
Test status
Simulation time 1372725734 ps
CPU time 8.25 seconds
Started Jun 06 01:15:26 PM PDT 24
Finished Jun 06 01:15:36 PM PDT 24
Peak memory 216692 kb
Host smart-2dae7589-30f3-4a1b-98bb-43a2df4e96bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615260229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2615260229
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3810483777
Short name T343
Test name
Test status
Simulation time 31493220558 ps
CPU time 268.87 seconds
Started Jun 06 01:15:25 PM PDT 24
Finished Jun 06 01:19:55 PM PDT 24
Peak memory 230912 kb
Host smart-9153232e-9852-4378-9866-3068692d559d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810483777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3810483777
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.837603765
Short name T353
Test name
Test status
Simulation time 23319972201 ps
CPU time 54.87 seconds
Started Jun 06 01:15:28 PM PDT 24
Finished Jun 06 01:16:23 PM PDT 24
Peak memory 219052 kb
Host smart-7d6cdc9a-93ef-4666-955e-79cad9eaa362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837603765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.837603765
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1913867730
Short name T61
Test name
Test status
Simulation time 5720144934 ps
CPU time 27.34 seconds
Started Jun 06 01:15:28 PM PDT 24
Finished Jun 06 01:15:56 PM PDT 24
Peak memory 211400 kb
Host smart-ba844ff2-aff5-437c-be89-f4664eb363e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1913867730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1913867730
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3763399207
Short name T166
Test name
Test status
Simulation time 1838211174 ps
CPU time 33.6 seconds
Started Jun 06 01:15:30 PM PDT 24
Finished Jun 06 01:16:04 PM PDT 24
Peak memory 216096 kb
Host smart-ffae2446-242c-40d0-bc75-8da6963bcb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763399207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3763399207
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3951713240
Short name T333
Test name
Test status
Simulation time 41464562651 ps
CPU time 140.11 seconds
Started Jun 06 01:15:26 PM PDT 24
Finished Jun 06 01:17:47 PM PDT 24
Peak memory 221324 kb
Host smart-d1893c36-a484-4061-98a2-4022a41c02eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951713240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3951713240
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2843329212
Short name T70
Test name
Test status
Simulation time 167504319 ps
CPU time 8.64 seconds
Started Jun 06 01:15:26 PM PDT 24
Finished Jun 06 01:15:36 PM PDT 24
Peak memory 216608 kb
Host smart-08588241-8f67-4e3c-95c0-994ae5cf99b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843329212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2843329212
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2767595580
Short name T338
Test name
Test status
Simulation time 40706362215 ps
CPU time 532.29 seconds
Started Jun 06 01:15:26 PM PDT 24
Finished Jun 06 01:24:20 PM PDT 24
Peak memory 233436 kb
Host smart-40bc6f61-1181-4421-91e7-390eaab30632
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767595580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2767595580
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3042908494
Short name T59
Test name
Test status
Simulation time 7005143059 ps
CPU time 62.52 seconds
Started Jun 06 01:15:27 PM PDT 24
Finished Jun 06 01:16:31 PM PDT 24
Peak memory 218828 kb
Host smart-402bf9af-ff7a-4fbf-a254-3304bf0556c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042908494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3042908494
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3205402152
Short name T339
Test name
Test status
Simulation time 4138943634 ps
CPU time 22.97 seconds
Started Jun 06 01:15:29 PM PDT 24
Finished Jun 06 01:15:52 PM PDT 24
Peak memory 210984 kb
Host smart-70635689-6e13-478d-9e69-726139bea5e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205402152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3205402152
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2401588908
Short name T223
Test name
Test status
Simulation time 21116050453 ps
CPU time 52.32 seconds
Started Jun 06 01:15:31 PM PDT 24
Finished Jun 06 01:16:24 PM PDT 24
Peak memory 215832 kb
Host smart-8c4186f0-81e3-45b1-9dcf-a579637b34f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401588908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2401588908
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1688517525
Short name T57
Test name
Test status
Simulation time 16741431358 ps
CPU time 186.26 seconds
Started Jun 06 01:15:27 PM PDT 24
Finished Jun 06 01:18:35 PM PDT 24
Peak memory 219392 kb
Host smart-0d3fd694-3cda-4459-8c7a-cb2f4d0baf50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688517525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1688517525
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3214120734
Short name T76
Test name
Test status
Simulation time 3774738518 ps
CPU time 14.37 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:14:29 PM PDT 24
Peak memory 216752 kb
Host smart-688f9a17-81be-4152-a814-ba4a2749718d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214120734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3214120734
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2000359540
Short name T306
Test name
Test status
Simulation time 308749506734 ps
CPU time 828.33 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:28:03 PM PDT 24
Peak memory 230252 kb
Host smart-400457bc-3115-451b-9c38-1f5c13c9a7ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000359540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2000359540
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1700894601
Short name T254
Test name
Test status
Simulation time 6662277438 ps
CPU time 58.52 seconds
Started Jun 06 01:14:10 PM PDT 24
Finished Jun 06 01:15:10 PM PDT 24
Peak memory 219076 kb
Host smart-191de45c-9e77-4c3d-be11-ced5d2937804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700894601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1700894601
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.33792674
Short name T240
Test name
Test status
Simulation time 2735547849 ps
CPU time 26.9 seconds
Started Jun 06 01:14:12 PM PDT 24
Finished Jun 06 01:14:41 PM PDT 24
Peak memory 219052 kb
Host smart-8b818b64-c40b-415a-8f88-14e6161e31d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33792674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.33792674
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3922486746
Short name T21
Test name
Test status
Simulation time 9763198817 ps
CPU time 34.34 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:14:49 PM PDT 24
Peak memory 216000 kb
Host smart-60298318-e1d4-4013-8a78-727a5fb0fa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922486746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3922486746
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1572178158
Short name T10
Test name
Test status
Simulation time 42355901873 ps
CPU time 155.11 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:16:50 PM PDT 24
Peak memory 219088 kb
Host smart-4ce2b677-ec03-4f47-b080-e6e1ba3c6a69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572178158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1572178158
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2924188405
Short name T75
Test name
Test status
Simulation time 4267011901 ps
CPU time 32.81 seconds
Started Jun 06 01:15:36 PM PDT 24
Finished Jun 06 01:16:10 PM PDT 24
Peak memory 216660 kb
Host smart-1d9866c1-0845-44e7-a7c0-eeb20187ac49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924188405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2924188405
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3088735708
Short name T296
Test name
Test status
Simulation time 1615946098 ps
CPU time 27.21 seconds
Started Jun 06 01:15:35 PM PDT 24
Finished Jun 06 01:16:04 PM PDT 24
Peak memory 218920 kb
Host smart-f5985d36-ce7c-43f9-8bb8-3075f4c0b35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088735708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3088735708
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1481735098
Short name T281
Test name
Test status
Simulation time 753544335 ps
CPU time 10.04 seconds
Started Jun 06 01:15:37 PM PDT 24
Finished Jun 06 01:15:48 PM PDT 24
Peak memory 219012 kb
Host smart-d9d108be-2218-423c-bbb0-8008c7edd073
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1481735098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1481735098
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1920010070
Short name T159
Test name
Test status
Simulation time 6915197057 ps
CPU time 61.35 seconds
Started Jun 06 01:15:35 PM PDT 24
Finished Jun 06 01:16:37 PM PDT 24
Peak memory 218704 kb
Host smart-ebeb94ac-fff5-4a5e-9d83-75ea886606c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920010070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1920010070
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.439495407
Short name T340
Test name
Test status
Simulation time 141778452734 ps
CPU time 297.35 seconds
Started Jun 06 01:15:36 PM PDT 24
Finished Jun 06 01:20:34 PM PDT 24
Peak memory 219608 kb
Host smart-73a37a48-8161-422d-bec8-0306cda4a09e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439495407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.439495407
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.4100361085
Short name T346
Test name
Test status
Simulation time 17780504225 ps
CPU time 34.15 seconds
Started Jun 06 01:15:37 PM PDT 24
Finished Jun 06 01:16:12 PM PDT 24
Peak memory 217180 kb
Host smart-a45345c4-c7a9-45f0-bdf0-37b051c4efab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100361085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.4100361085
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.856938559
Short name T320
Test name
Test status
Simulation time 42856131711 ps
CPU time 428.42 seconds
Started Jun 06 01:15:36 PM PDT 24
Finished Jun 06 01:22:45 PM PDT 24
Peak memory 214580 kb
Host smart-8bf052c9-3e68-416c-93f7-ed8ab3a6cfbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856938559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.856938559
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.850487880
Short name T212
Test name
Test status
Simulation time 8524271503 ps
CPU time 68.37 seconds
Started Jun 06 01:15:36 PM PDT 24
Finished Jun 06 01:16:46 PM PDT 24
Peak memory 219012 kb
Host smart-53673385-87d3-4de2-995b-505254d56e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850487880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.850487880
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3704725493
Short name T111
Test name
Test status
Simulation time 7485761497 ps
CPU time 21.1 seconds
Started Jun 06 01:15:35 PM PDT 24
Finished Jun 06 01:15:56 PM PDT 24
Peak memory 211440 kb
Host smart-51691b3c-3bc8-48a2-8fc3-24088eabcbc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3704725493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3704725493
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1028581696
Short name T203
Test name
Test status
Simulation time 354452819 ps
CPU time 20.04 seconds
Started Jun 06 01:15:35 PM PDT 24
Finished Jun 06 01:15:57 PM PDT 24
Peak memory 217408 kb
Host smart-2417f7c0-05f0-457b-9b48-f9a60e2fe2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028581696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1028581696
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3602814374
Short name T253
Test name
Test status
Simulation time 376851889 ps
CPU time 24.13 seconds
Started Jun 06 01:15:34 PM PDT 24
Finished Jun 06 01:15:59 PM PDT 24
Peak memory 218908 kb
Host smart-9b7de588-cd77-40e4-b426-183cc84a0937
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602814374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3602814374
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3250183878
Short name T248
Test name
Test status
Simulation time 609430277 ps
CPU time 12.51 seconds
Started Jun 06 01:15:33 PM PDT 24
Finished Jun 06 01:15:47 PM PDT 24
Peak memory 216640 kb
Host smart-6b73022b-bd7b-4992-bae0-0f5052a390fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250183878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3250183878
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3985773606
Short name T110
Test name
Test status
Simulation time 6832788680 ps
CPU time 225.82 seconds
Started Jun 06 01:15:38 PM PDT 24
Finished Jun 06 01:19:25 PM PDT 24
Peak memory 225792 kb
Host smart-109fca5b-44ae-45c5-acfb-5f17f1f613fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985773606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3985773606
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.13352608
Short name T262
Test name
Test status
Simulation time 332448739 ps
CPU time 19.38 seconds
Started Jun 06 01:15:34 PM PDT 24
Finished Jun 06 01:15:54 PM PDT 24
Peak memory 218956 kb
Host smart-861c20c7-2f8a-477d-bcaf-53fc5719cce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13352608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.13352608
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1941297114
Short name T122
Test name
Test status
Simulation time 1467684415 ps
CPU time 12.44 seconds
Started Jun 06 01:15:35 PM PDT 24
Finished Jun 06 01:15:49 PM PDT 24
Peak memory 218480 kb
Host smart-f7873d23-fc47-4e38-abdd-5ab3efc57473
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1941297114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1941297114
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2099157844
Short name T255
Test name
Test status
Simulation time 9788578141 ps
CPU time 36.41 seconds
Started Jun 06 01:15:37 PM PDT 24
Finished Jun 06 01:16:14 PM PDT 24
Peak memory 216180 kb
Host smart-bbe215ba-252b-4525-a128-f87aab2cfcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099157844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2099157844
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1480567621
Short name T336
Test name
Test status
Simulation time 14501013986 ps
CPU time 63.96 seconds
Started Jun 06 01:15:37 PM PDT 24
Finished Jun 06 01:16:42 PM PDT 24
Peak memory 216972 kb
Host smart-a46f6a7c-e185-4582-b1be-f3aad555286d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480567621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1480567621
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.859049849
Short name T222
Test name
Test status
Simulation time 6587639272 ps
CPU time 19.44 seconds
Started Jun 06 01:15:36 PM PDT 24
Finished Jun 06 01:15:57 PM PDT 24
Peak memory 217056 kb
Host smart-4a0dc4a1-92c7-45ee-a19b-4b6d06a4fae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859049849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.859049849
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.630454028
Short name T249
Test name
Test status
Simulation time 241150570466 ps
CPU time 1125.13 seconds
Started Jun 06 01:15:36 PM PDT 24
Finished Jun 06 01:34:23 PM PDT 24
Peak memory 217556 kb
Host smart-2570df6f-fae8-4cff-afae-a48398e02892
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630454028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.630454028
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.449999909
Short name T321
Test name
Test status
Simulation time 7467842065 ps
CPU time 65 seconds
Started Jun 06 01:15:35 PM PDT 24
Finished Jun 06 01:16:41 PM PDT 24
Peak memory 219044 kb
Host smart-cbda0fc7-e2f8-469c-b133-8579dc170519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449999909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.449999909
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1510535567
Short name T307
Test name
Test status
Simulation time 685345372 ps
CPU time 10.26 seconds
Started Jun 06 01:15:39 PM PDT 24
Finished Jun 06 01:15:50 PM PDT 24
Peak memory 219236 kb
Host smart-d91a96b2-a4d1-4c5c-a80a-2b293bf1473d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1510535567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1510535567
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1611143890
Short name T298
Test name
Test status
Simulation time 690985033 ps
CPU time 20.71 seconds
Started Jun 06 01:15:35 PM PDT 24
Finished Jun 06 01:15:57 PM PDT 24
Peak memory 215652 kb
Host smart-45b23fe3-97f2-4500-8472-f1404ad23ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611143890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1611143890
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3126677491
Short name T13
Test name
Test status
Simulation time 1849692266 ps
CPU time 28.52 seconds
Started Jun 06 01:15:37 PM PDT 24
Finished Jun 06 01:16:06 PM PDT 24
Peak memory 215208 kb
Host smart-b25e5e20-3ca6-4669-8fe2-83bbf5ff86ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126677491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3126677491
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3999170898
Short name T276
Test name
Test status
Simulation time 15654270259 ps
CPU time 31.32 seconds
Started Jun 06 01:15:47 PM PDT 24
Finished Jun 06 01:16:19 PM PDT 24
Peak memory 217016 kb
Host smart-8f05df2e-c269-4a16-bab2-35ab070166fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999170898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3999170898
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2667247866
Short name T33
Test name
Test status
Simulation time 334326910431 ps
CPU time 361.69 seconds
Started Jun 06 01:15:45 PM PDT 24
Finished Jun 06 01:21:48 PM PDT 24
Peak memory 239444 kb
Host smart-c2f4d7d9-07c8-49bd-9acc-f4a4ef97eb78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667247866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2667247866
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2864124182
Short name T165
Test name
Test status
Simulation time 10287632182 ps
CPU time 49.67 seconds
Started Jun 06 01:15:50 PM PDT 24
Finished Jun 06 01:16:40 PM PDT 24
Peak memory 218940 kb
Host smart-a9e096ab-bb15-4ad6-9ede-af7c52565390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864124182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2864124182
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.627049441
Short name T141
Test name
Test status
Simulation time 3198619364 ps
CPU time 28.67 seconds
Started Jun 06 01:15:46 PM PDT 24
Finished Jun 06 01:16:16 PM PDT 24
Peak memory 211068 kb
Host smart-eca33072-6a2c-4af5-b7a9-695a5357a449
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=627049441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.627049441
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.228575289
Short name T191
Test name
Test status
Simulation time 4517766177 ps
CPU time 51.2 seconds
Started Jun 06 01:15:44 PM PDT 24
Finished Jun 06 01:16:36 PM PDT 24
Peak memory 215740 kb
Host smart-5fa89517-9f7d-40f1-84da-78873562c29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228575289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.228575289
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2506836261
Short name T329
Test name
Test status
Simulation time 60664531801 ps
CPU time 154.2 seconds
Started Jun 06 01:15:46 PM PDT 24
Finished Jun 06 01:18:21 PM PDT 24
Peak memory 227240 kb
Host smart-fcc6cb8a-393e-4afe-82f6-2b55e255dda6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506836261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2506836261
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.935730545
Short name T156
Test name
Test status
Simulation time 4603286897 ps
CPU time 15.74 seconds
Started Jun 06 01:15:46 PM PDT 24
Finished Jun 06 01:16:03 PM PDT 24
Peak memory 217120 kb
Host smart-a0d2a548-34fc-44a3-a35a-4370376cd13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935730545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.935730545
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1665882283
Short name T158
Test name
Test status
Simulation time 147831452754 ps
CPU time 748.73 seconds
Started Jun 06 01:15:44 PM PDT 24
Finished Jun 06 01:28:14 PM PDT 24
Peak memory 236052 kb
Host smart-4fe5a3e0-0f03-4302-8aaf-add167d78edb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665882283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1665882283
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3633626334
Short name T60
Test name
Test status
Simulation time 8528575939 ps
CPU time 67.94 seconds
Started Jun 06 01:15:57 PM PDT 24
Finished Jun 06 01:17:06 PM PDT 24
Peak memory 219000 kb
Host smart-ef40dd68-771e-4b20-bb0d-efc24af72044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633626334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3633626334
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1807717462
Short name T334
Test name
Test status
Simulation time 1408070544 ps
CPU time 18.87 seconds
Started Jun 06 01:15:47 PM PDT 24
Finished Jun 06 01:16:07 PM PDT 24
Peak memory 218872 kb
Host smart-0c272acc-9fd7-4c6a-ad0e-696b5c4e4c5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1807717462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1807717462
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2757301340
Short name T290
Test name
Test status
Simulation time 1440412648 ps
CPU time 20.32 seconds
Started Jun 06 01:15:44 PM PDT 24
Finished Jun 06 01:16:06 PM PDT 24
Peak memory 216500 kb
Host smart-6ed0bcfe-10f2-4c90-aa61-62ec2b627dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757301340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2757301340
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1155641889
Short name T178
Test name
Test status
Simulation time 3013607808 ps
CPU time 47.89 seconds
Started Jun 06 01:15:45 PM PDT 24
Finished Jun 06 01:16:35 PM PDT 24
Peak memory 219212 kb
Host smart-90d32c17-f36e-4caa-96f9-f2cdbad57475
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155641889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1155641889
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2688071850
Short name T332
Test name
Test status
Simulation time 4341262379 ps
CPU time 32.12 seconds
Started Jun 06 01:15:48 PM PDT 24
Finished Jun 06 01:16:21 PM PDT 24
Peak memory 217012 kb
Host smart-4fe31962-3123-4b98-968f-dee509c8335a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688071850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2688071850
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.970720791
Short name T269
Test name
Test status
Simulation time 24151593728 ps
CPU time 214.76 seconds
Started Jun 06 01:15:47 PM PDT 24
Finished Jun 06 01:19:23 PM PDT 24
Peak memory 239248 kb
Host smart-afbf9e8f-dc6c-4bb8-a023-ebdc20fb1f87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970720791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.970720791
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.702297421
Short name T201
Test name
Test status
Simulation time 11038839771 ps
CPU time 52.37 seconds
Started Jun 06 01:15:42 PM PDT 24
Finished Jun 06 01:16:35 PM PDT 24
Peak memory 218960 kb
Host smart-78acbb0b-b133-47f8-8cdc-a9e1b9aaaf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702297421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.702297421
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.934046255
Short name T147
Test name
Test status
Simulation time 185981267 ps
CPU time 10.62 seconds
Started Jun 06 01:15:43 PM PDT 24
Finished Jun 06 01:15:55 PM PDT 24
Peak memory 218956 kb
Host smart-dd331f43-2bb6-4f4c-aebb-9cf33fb0c0fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=934046255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.934046255
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1190920022
Short name T245
Test name
Test status
Simulation time 1781198598 ps
CPU time 63.95 seconds
Started Jun 06 01:15:45 PM PDT 24
Finished Jun 06 01:16:50 PM PDT 24
Peak memory 218908 kb
Host smart-3204327e-6b8a-458e-af47-c60e98f29d37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190920022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1190920022
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3840868104
Short name T62
Test name
Test status
Simulation time 2993345768 ps
CPU time 25.11 seconds
Started Jun 06 01:15:45 PM PDT 24
Finished Jun 06 01:16:11 PM PDT 24
Peak memory 216812 kb
Host smart-b99959f2-8ab4-4b2d-bcca-bb7cdd37e898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840868104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3840868104
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3939398772
Short name T308
Test name
Test status
Simulation time 133547053401 ps
CPU time 633.84 seconds
Started Jun 06 01:15:48 PM PDT 24
Finished Jun 06 01:26:22 PM PDT 24
Peak memory 227796 kb
Host smart-56d9bfc2-dce7-49e4-92ed-fdd72eac5641
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939398772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3939398772
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1496790823
Short name T331
Test name
Test status
Simulation time 1835457494 ps
CPU time 19.34 seconds
Started Jun 06 01:15:46 PM PDT 24
Finished Jun 06 01:16:07 PM PDT 24
Peak memory 218928 kb
Host smart-d61d74e1-e270-407b-adcb-175461fb1121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496790823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1496790823
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1405651332
Short name T314
Test name
Test status
Simulation time 6205979178 ps
CPU time 19.2 seconds
Started Jun 06 01:15:44 PM PDT 24
Finished Jun 06 01:16:04 PM PDT 24
Peak memory 217316 kb
Host smart-2a1bd187-a8a1-4301-86fa-17e064d678c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405651332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1405651332
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4270954853
Short name T258
Test name
Test status
Simulation time 4910173849 ps
CPU time 53.28 seconds
Started Jun 06 01:15:44 PM PDT 24
Finished Jun 06 01:16:39 PM PDT 24
Peak memory 216568 kb
Host smart-bc7659f0-b9e6-43dd-af35-f60483deabd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270954853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4270954853
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1817314476
Short name T218
Test name
Test status
Simulation time 5381408315 ps
CPU time 37.33 seconds
Started Jun 06 01:15:45 PM PDT 24
Finished Jun 06 01:16:24 PM PDT 24
Peak memory 218948 kb
Host smart-218804f6-79b4-4171-83a0-48667271015a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817314476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1817314476
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1635341077
Short name T51
Test name
Test status
Simulation time 88137179283 ps
CPU time 832.57 seconds
Started Jun 06 01:15:45 PM PDT 24
Finished Jun 06 01:29:39 PM PDT 24
Peak memory 235548 kb
Host smart-8269dcfa-88a7-47bd-856c-4923a3f6ecd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635341077 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1635341077
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3773155995
Short name T229
Test name
Test status
Simulation time 689327372 ps
CPU time 8.39 seconds
Started Jun 06 01:15:43 PM PDT 24
Finished Jun 06 01:15:53 PM PDT 24
Peak memory 216356 kb
Host smart-1d11aaa9-5e45-443a-ad5a-ae1e349b2f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773155995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3773155995
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2302387422
Short name T259
Test name
Test status
Simulation time 136695146209 ps
CPU time 533.53 seconds
Started Jun 06 01:15:43 PM PDT 24
Finished Jun 06 01:24:38 PM PDT 24
Peak memory 236808 kb
Host smart-58b6308c-d90b-4d34-bc69-7efb572cc6d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302387422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2302387422
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2750884411
Short name T350
Test name
Test status
Simulation time 7012337883 ps
CPU time 60.97 seconds
Started Jun 06 01:15:44 PM PDT 24
Finished Jun 06 01:16:46 PM PDT 24
Peak memory 219056 kb
Host smart-a0ca80f1-a5ad-4f78-a8d8-9a576036fe4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750884411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2750884411
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.699972330
Short name T148
Test name
Test status
Simulation time 8690867292 ps
CPU time 27.72 seconds
Started Jun 06 01:15:48 PM PDT 24
Finished Jun 06 01:16:17 PM PDT 24
Peak memory 219052 kb
Host smart-8828d391-00a6-4dfa-8ce6-883cd6381972
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699972330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.699972330
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1247488555
Short name T153
Test name
Test status
Simulation time 10258299112 ps
CPU time 51.72 seconds
Started Jun 06 01:15:44 PM PDT 24
Finished Jun 06 01:16:37 PM PDT 24
Peak memory 215804 kb
Host smart-1c8f1afb-c04b-405b-8e36-9150758bd4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247488555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1247488555
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3308661341
Short name T65
Test name
Test status
Simulation time 3928797119 ps
CPU time 14.69 seconds
Started Jun 06 01:15:55 PM PDT 24
Finished Jun 06 01:16:11 PM PDT 24
Peak memory 216620 kb
Host smart-b05899bd-51d4-4576-ad10-413eda246410
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308661341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3308661341
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.169366615
Short name T155
Test name
Test status
Simulation time 239093593849 ps
CPU time 487.25 seconds
Started Jun 06 01:15:45 PM PDT 24
Finished Jun 06 01:23:53 PM PDT 24
Peak memory 226244 kb
Host smart-f1cb3db7-1dde-4ef2-b86b-a8136c44e4e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169366615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.169366615
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3670990209
Short name T161
Test name
Test status
Simulation time 84760161373 ps
CPU time 51.9 seconds
Started Jun 06 01:15:45 PM PDT 24
Finished Jun 06 01:16:39 PM PDT 24
Peak memory 218960 kb
Host smart-01385787-4fa8-431d-ac09-b6c731ef92e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670990209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3670990209
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3247951223
Short name T302
Test name
Test status
Simulation time 11317666607 ps
CPU time 26.89 seconds
Started Jun 06 01:15:46 PM PDT 24
Finished Jun 06 01:16:14 PM PDT 24
Peak memory 211688 kb
Host smart-82fd03ca-f49b-4c66-9503-b4743f78078e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247951223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3247951223
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3476145393
Short name T31
Test name
Test status
Simulation time 13386027691 ps
CPU time 68.18 seconds
Started Jun 06 01:15:48 PM PDT 24
Finished Jun 06 01:16:57 PM PDT 24
Peak memory 216156 kb
Host smart-8b0ec14f-fd4b-4cf1-bb4b-34084f9c9b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476145393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3476145393
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1240091719
Short name T116
Test name
Test status
Simulation time 13277641890 ps
CPU time 28.97 seconds
Started Jun 06 01:14:14 PM PDT 24
Finished Jun 06 01:14:44 PM PDT 24
Peak memory 217128 kb
Host smart-fa434158-b58d-4ca7-b7fd-a7fa0bfb0269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240091719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1240091719
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2690702091
Short name T162
Test name
Test status
Simulation time 31653800661 ps
CPU time 322.53 seconds
Started Jun 06 01:14:12 PM PDT 24
Finished Jun 06 01:19:36 PM PDT 24
Peak memory 234192 kb
Host smart-549aa0d6-1f5d-4118-93fb-daf34858d834
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690702091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2690702091
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2092604499
Short name T211
Test name
Test status
Simulation time 5084769535 ps
CPU time 48.54 seconds
Started Jun 06 01:14:11 PM PDT 24
Finished Jun 06 01:15:00 PM PDT 24
Peak memory 216564 kb
Host smart-766fc248-e20c-4a8e-9b0e-1875a4fc748b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092604499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2092604499
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3114769494
Short name T344
Test name
Test status
Simulation time 1055693387 ps
CPU time 17.56 seconds
Started Jun 06 01:14:12 PM PDT 24
Finished Jun 06 01:14:31 PM PDT 24
Peak memory 219000 kb
Host smart-006b5fc6-df1d-4750-87de-a0464748ea00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3114769494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3114769494
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3701385184
Short name T265
Test name
Test status
Simulation time 1433303893 ps
CPU time 20.41 seconds
Started Jun 06 01:14:12 PM PDT 24
Finished Jun 06 01:14:33 PM PDT 24
Peak memory 216436 kb
Host smart-a23062d7-c4ff-457a-8e60-db81f9bf3621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701385184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3701385184
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1909240364
Short name T38
Test name
Test status
Simulation time 10004178590 ps
CPU time 24.21 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:14:39 PM PDT 24
Peak memory 214124 kb
Host smart-86ba7777-4a31-45a0-9f0a-cdaa5a761248
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909240364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1909240364
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.15172790
Short name T50
Test name
Test status
Simulation time 25775705681 ps
CPU time 2595.82 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:57:31 PM PDT 24
Peak memory 230088 kb
Host smart-e14e928d-998d-41b8-81d3-7affb943da28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15172790 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.15172790
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3216238069
Short name T207
Test name
Test status
Simulation time 13383845311 ps
CPU time 28.67 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:14:44 PM PDT 24
Peak memory 217192 kb
Host smart-e6bc3d06-eaaa-4be0-ae56-8151038406e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216238069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3216238069
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2194491162
Short name T299
Test name
Test status
Simulation time 6108676559 ps
CPU time 56.04 seconds
Started Jun 06 01:14:14 PM PDT 24
Finished Jun 06 01:15:12 PM PDT 24
Peak memory 219536 kb
Host smart-9217d1ca-85ba-461a-bff3-d28f6684ddc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194491162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2194491162
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1567672974
Short name T264
Test name
Test status
Simulation time 15565654501 ps
CPU time 29.27 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:14:44 PM PDT 24
Peak memory 217348 kb
Host smart-56f4d27f-3305-4c7f-a93c-643a5716f542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567672974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1567672974
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1415718279
Short name T140
Test name
Test status
Simulation time 51588816304 ps
CPU time 66.51 seconds
Started Jun 06 01:14:14 PM PDT 24
Finished Jun 06 01:15:22 PM PDT 24
Peak memory 216688 kb
Host smart-c0faf9ae-d7cf-40e9-9b8f-7a141a87be6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415718279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1415718279
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.262631173
Short name T123
Test name
Test status
Simulation time 1726834436 ps
CPU time 38.22 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:14:52 PM PDT 24
Peak memory 217544 kb
Host smart-e3f48043-e877-45a6-b33c-38983a3b1119
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262631173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.262631173
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3364015199
Short name T294
Test name
Test status
Simulation time 331802550 ps
CPU time 8.53 seconds
Started Jun 06 01:14:11 PM PDT 24
Finished Jun 06 01:14:21 PM PDT 24
Peak memory 216600 kb
Host smart-d72eee34-74d1-4b43-b070-00b87b3b7931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364015199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3364015199
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2218109866
Short name T4
Test name
Test status
Simulation time 44438201076 ps
CPU time 526.31 seconds
Started Jun 06 01:14:14 PM PDT 24
Finished Jun 06 01:23:02 PM PDT 24
Peak memory 235960 kb
Host smart-136abed3-d44b-432c-aaf4-6ebd7cc7ee20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218109866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2218109866
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4015219848
Short name T238
Test name
Test status
Simulation time 58556415760 ps
CPU time 70.54 seconds
Started Jun 06 01:14:20 PM PDT 24
Finished Jun 06 01:15:31 PM PDT 24
Peak memory 219048 kb
Host smart-8a1c36c1-cc83-48c1-8142-b588cc9dd619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015219848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.4015219848
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2224813940
Short name T236
Test name
Test status
Simulation time 3195645643 ps
CPU time 29.21 seconds
Started Jun 06 01:14:11 PM PDT 24
Finished Jun 06 01:14:41 PM PDT 24
Peak memory 211192 kb
Host smart-d71dbfdc-af4f-45bc-9f05-9a77624a0ab0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2224813940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2224813940
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1454134232
Short name T154
Test name
Test status
Simulation time 2686414290 ps
CPU time 24.78 seconds
Started Jun 06 01:14:12 PM PDT 24
Finished Jun 06 01:14:38 PM PDT 24
Peak memory 216524 kb
Host smart-ed4ad3b7-4db5-4ee8-a066-9effb7ca60c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454134232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1454134232
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4156815253
Short name T224
Test name
Test status
Simulation time 3730861324 ps
CPU time 73.79 seconds
Started Jun 06 01:14:12 PM PDT 24
Finished Jun 06 01:15:27 PM PDT 24
Peak memory 219488 kb
Host smart-aa2df39b-6932-455e-a55a-e417402a745d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156815253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4156815253
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3665723151
Short name T239
Test name
Test status
Simulation time 3242304653 ps
CPU time 27.58 seconds
Started Jun 06 01:14:19 PM PDT 24
Finished Jun 06 01:14:48 PM PDT 24
Peak memory 216840 kb
Host smart-cdbcacce-9e10-456c-8b0f-fe3a046eecff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665723151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3665723151
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1842763992
Short name T244
Test name
Test status
Simulation time 75603289601 ps
CPU time 273.22 seconds
Started Jun 06 01:14:12 PM PDT 24
Finished Jun 06 01:18:47 PM PDT 24
Peak memory 217508 kb
Host smart-cf7aef52-edc0-45c4-9cc9-3245fced00fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842763992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1842763992
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2545848612
Short name T213
Test name
Test status
Simulation time 22243750315 ps
CPU time 51.57 seconds
Started Jun 06 01:14:10 PM PDT 24
Finished Jun 06 01:15:02 PM PDT 24
Peak memory 218932 kb
Host smart-50d7e992-5c3d-438b-bdf3-a7ad90299875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545848612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2545848612
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3825315758
Short name T36
Test name
Test status
Simulation time 3814562774 ps
CPU time 31.78 seconds
Started Jun 06 01:14:15 PM PDT 24
Finished Jun 06 01:14:48 PM PDT 24
Peak memory 219052 kb
Host smart-2eb6e681-2c9d-4f6d-85ab-7eb434506892
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3825315758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3825315758
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2669099980
Short name T348
Test name
Test status
Simulation time 8525041248 ps
CPU time 80.35 seconds
Started Jun 06 01:14:09 PM PDT 24
Finished Jun 06 01:15:30 PM PDT 24
Peak memory 216700 kb
Host smart-78b9fcf9-10f0-4b77-9026-ce66363dce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669099980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2669099980
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2971383647
Short name T144
Test name
Test status
Simulation time 45319573954 ps
CPU time 99.9 seconds
Started Jun 06 01:14:13 PM PDT 24
Finished Jun 06 01:15:55 PM PDT 24
Peak memory 219096 kb
Host smart-872fe41d-5034-4017-9844-5d03fc32e11e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971383647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2971383647
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1415217297
Short name T109
Test name
Test status
Simulation time 13162994175 ps
CPU time 20.24 seconds
Started Jun 06 01:14:23 PM PDT 24
Finished Jun 06 01:14:44 PM PDT 24
Peak memory 216944 kb
Host smart-a19c98a2-a196-4260-be9c-d7b7676cedf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415217297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1415217297
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2542839070
Short name T228
Test name
Test status
Simulation time 32096806037 ps
CPU time 338.41 seconds
Started Jun 06 01:14:22 PM PDT 24
Finished Jun 06 01:20:01 PM PDT 24
Peak memory 215360 kb
Host smart-6ddc3ab0-1376-4d63-a24a-80dfe2ac4d97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542839070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2542839070
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3190702901
Short name T311
Test name
Test status
Simulation time 16389354474 ps
CPU time 67.8 seconds
Started Jun 06 01:14:21 PM PDT 24
Finished Jun 06 01:15:30 PM PDT 24
Peak memory 219052 kb
Host smart-dbd990ae-95fe-4ae5-b2e9-02b4297cebe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190702901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3190702901
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.853249828
Short name T195
Test name
Test status
Simulation time 725934040 ps
CPU time 10.52 seconds
Started Jun 06 01:14:23 PM PDT 24
Finished Jun 06 01:14:34 PM PDT 24
Peak memory 219236 kb
Host smart-af1dbf71-8de1-435c-8002-b4447ad307cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853249828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.853249828
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.604454026
Short name T149
Test name
Test status
Simulation time 29897230453 ps
CPU time 60.33 seconds
Started Jun 06 01:14:21 PM PDT 24
Finished Jun 06 01:15:22 PM PDT 24
Peak memory 217068 kb
Host smart-e7d2e740-f19f-44bd-a315-587d83910b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604454026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.604454026
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.4145021932
Short name T108
Test name
Test status
Simulation time 5941627144 ps
CPU time 72.91 seconds
Started Jun 06 01:14:22 PM PDT 24
Finished Jun 06 01:15:36 PM PDT 24
Peak memory 218380 kb
Host smart-ff3d71d2-b9f5-4051-b9ca-615fcdb9f17b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145021932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.4145021932
Directory /workspace/9.rom_ctrl_stress_all/latest
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