Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32091	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

405561

1

T1

24

T3

12

T4

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	127386	1			T1	200		T3	12		T4	267
values[0x0]	152407	1			T11	19670		T12	30436		T13	12704
values[0x1]	157859	1			T11	20480		T12	31456		T13	13282

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15531	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

422121

1

T1

120

T3

12

T4

145

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1894	1			T4	9		T29	1		T111	34
valid_sources[0x01]	1553	1			T1	1		T17	1		T29	1
valid_sources[0x02]	1859	1			T1	1		T6	1		T9	1
valid_sources[0x03]	1479	1			T7	1		T26	2		T32	1
valid_sources[0x04]	1961	1			T9	3		T108	1		T110	5
valid_sources[0x05]	1444	1			T4	5		T6	1		T8	1
valid_sources[0x06]	1621	1			T1	1		T6	1		T7	1
valid_sources[0x07]	1741	1			T9	2		T10	2		T26	3
valid_sources[0x08]	1919	1			T1	1		T10	1		T11	202
valid_sources[0x09]	1822	1			T5	1		T8	2		T17	1
valid_sources[0x0a]	1459	1			T1	3		T14	1		T11	216
valid_sources[0x0b]	1574	1			T1	1		T17	4		T32	1
valid_sources[0x0c]	1426	1			T6	1		T7	1		T8	2
valid_sources[0x0d]	1433	1			T1	1		T6	2		T7	1
valid_sources[0x0e]	1565	1			T26	1		T110	2		T11	191
valid_sources[0x0f]	1691	1			T6	2		T10	3		T26	3
valid_sources[0x10]	1721	1			T1	1		T6	3		T8	1
valid_sources[0x11]	1434	1			T5	1		T26	1		T29	2
valid_sources[0x12]	1549	1			T1	2		T7	4		T8	1
valid_sources[0x13]	1498	1			T4	6		T8	1		T17	8
valid_sources[0x14]	1752	1			T6	5		T8	1		T110	2
valid_sources[0x15]	1525	1			T1	1		T4	7		T9	1
valid_sources[0x16]	1925	1			T5	2		T10	2		T17	1
valid_sources[0x17]	1478	1			T10	1		T32	3		T108	1
valid_sources[0x18]	1464	1			T9	2		T32	1		T14	1
valid_sources[0x19]	1453	1			T1	1		T7	1		T10	4
valid_sources[0x1a]	1710	1			T17	1		T26	2		T32	2
valid_sources[0x1b]	1637	1			T10	2		T17	1		T14	1
valid_sources[0x1c]	1431	1			T1	1		T6	2		T7	2
valid_sources[0x1d]	1714	1			T1	1		T7	1		T9	1
valid_sources[0x1e]	1538	1			T10	2		T26	3		T11	227
valid_sources[0x1f]	3129	1			T1	3		T8	1		T10	1
valid_sources[0x20]	1812	1			T5	1		T10	2		T17	1
valid_sources[0x21]	1787	1			T29	1		T108	1		T110	3
valid_sources[0x22]	1472	1			T1	2		T26	6		T14	1
valid_sources[0x23]	2627	1			T6	2		T10	1		T11	182
valid_sources[0x24]	1494	1			T26	2		T29	3		T80	7
valid_sources[0x25]	1641	1			T1	1		T8	1		T10	1
valid_sources[0x26]	2343	1			T1	2		T26	3		T32	2
valid_sources[0x27]	1897	1			T17	1		T32	1		T14	1
valid_sources[0x28]	1829	1			T3	12		T26	8		T11	211
valid_sources[0x29]	1461	1			T1	1		T5	1		T8	1
valid_sources[0x2a]	1549	1			T1	1		T4	7		T7	2
valid_sources[0x2b]	1711	1			T9	1		T10	2		T108	2
valid_sources[0x2c]	1656	1			T1	1		T6	2		T8	2
valid_sources[0x2d]	1489	1			T1	1		T8	2		T10	2
valid_sources[0x2e]	1459	1			T5	6		T10	2		T17	2
valid_sources[0x2f]	1434	1			T1	1		T10	4		T26	1
valid_sources[0x30]	1623	1			T1	1		T8	1		T10	2
valid_sources[0x31]	1606	1			T1	2		T8	1		T10	1
valid_sources[0x32]	1584	1			T4	8		T8	1		T61	1
valid_sources[0x33]	2303	1			T4	2		T26	2		T32	1
valid_sources[0x34]	1385	1			T1	2		T6	1		T7	1
valid_sources[0x35]	1395	1			T1	3		T4	5		T10	2
valid_sources[0x36]	1484	1			T14	1		T11	226		T54	3
valid_sources[0x37]	2004	1			T8	5		T17	2		T32	1
valid_sources[0x38]	2387	1			T1	1		T5	2		T10	3
valid_sources[0x39]	1979	1			T1	2		T8	1		T10	1
valid_sources[0x3a]	1489	1			T1	1		T9	2		T10	3
valid_sources[0x3b]	1369	1			T11	194		T54	3		T125	7
valid_sources[0x3c]	1418	1			T1	2		T8	1		T26	3
valid_sources[0x3d]	1523	1			T32	2		T110	7		T11	181
valid_sources[0x3e]	1715	1			T1	1		T6	6		T26	1
valid_sources[0x3f]	1445	1			T17	3		T11	214		T82	1
valid_sources[0x40]	1496	1			T4	12		T8	4		T10	2
valid_sources[0x41]	1738	1			T1	1		T7	1		T9	1
valid_sources[0x42]	2353	1			T1	2		T8	1		T26	3
valid_sources[0x43]	1730	1			T6	1		T10	1		T32	2
valid_sources[0x44]	1441	1			T1	1		T32	1		T14	1
valid_sources[0x45]	1474	1			T26	3		T14	1		T11	216
valid_sources[0x46]	2476	1			T1	3		T5	2		T8	1
valid_sources[0x47]	1423	1			T32	1		T108	1		T11	201
valid_sources[0x48]	1457	1			T6	1		T10	3		T17	4
valid_sources[0x49]	1527	1			T8	1		T10	1		T26	1
valid_sources[0x4a]	1725	1			T10	1		T32	2		T29	1
valid_sources[0x4b]	2020	1			T1	1		T7	3		T8	2
valid_sources[0x4c]	1856	1			T10	1		T29	1		T11	191
valid_sources[0x4d]	1941	1			T8	1		T9	1		T10	1
valid_sources[0x4e]	1451	1			T1	1		T32	2		T29	1
valid_sources[0x4f]	1728	1			T5	3		T8	1		T10	1
valid_sources[0x50]	1472	1			T9	1		T26	2		T61	1
valid_sources[0x51]	1437	1			T5	2		T10	3		T32	3
valid_sources[0x52]	1662	1			T1	1		T32	1		T29	1
valid_sources[0x53]	1483	1			T10	2		T26	2		T32	2
valid_sources[0x54]	1458	1			T4	16		T8	1		T10	2
valid_sources[0x55]	1470	1			T1	1		T7	1		T8	3
valid_sources[0x56]	1426	1			T10	1		T14	1		T11	223
valid_sources[0x57]	1934	1			T1	1		T9	1		T10	1
valid_sources[0x58]	1830	1			T1	2		T8	2		T17	1
valid_sources[0x59]	1522	1			T10	1		T26	4		T32	1
valid_sources[0x5a]	1859	1			T1	2		T10	1		T17	1
valid_sources[0x5b]	1458	1			T5	1		T26	1		T14	1
valid_sources[0x5c]	2880	1			T1	3		T8	1		T61	1
valid_sources[0x5d]	1937	1			T1	2		T8	2		T10	3
valid_sources[0x5e]	1508	1			T6	1		T10	2		T26	3
valid_sources[0x5f]	2231	1			T1	3		T6	1		T17	1
valid_sources[0x60]	1462	1			T1	2		T8	2		T32	1
valid_sources[0x61]	1475	1			T1	2		T10	1		T29	1
valid_sources[0x62]	2729	1			T8	2		T10	1		T26	1
valid_sources[0x63]	1689	1			T1	1		T4	13		T5	4
valid_sources[0x64]	2399	1			T1	2		T7	1		T10	2
valid_sources[0x65]	1529	1			T6	4		T17	3		T14	1
valid_sources[0x66]	1536	1			T1	1		T5	1		T6	1
valid_sources[0x67]	1669	1			T1	1		T9	1		T10	1
valid_sources[0x68]	2643	1			T5	1		T6	1		T10	3
valid_sources[0x69]	1450	1			T8	1		T32	1		T14	1
valid_sources[0x6a]	2567	1			T1	1		T8	1		T26	1
valid_sources[0x6b]	1493	1			T1	2		T5	2		T8	1
valid_sources[0x6c]	1543	1			T17	4		T29	2		T61	1
valid_sources[0x6d]	1521	1			T1	2		T10	1		T17	1
valid_sources[0x6e]	2448	1			T32	1		T11	205		T54	3
valid_sources[0x6f]	1567	1			T9	1		T26	3		T11	206
valid_sources[0x70]	1677	1			T1	1		T8	2		T14	1
valid_sources[0x71]	1493	1			T1	1		T7	1		T9	1
valid_sources[0x72]	1572	1			T1	1		T5	4		T17	4
valid_sources[0x73]	1875	1			T1	1		T4	3		T10	2
valid_sources[0x74]	1725	1			T1	1		T4	15		T17	1
valid_sources[0x75]	1624	1			T1	2		T4	2		T5	2
valid_sources[0x76]	1933	1			T7	2		T17	5		T26	1
valid_sources[0x77]	1610	1			T1	1		T6	1		T9	1
valid_sources[0x78]	1624	1			T1	2		T8	2		T10	1
valid_sources[0x79]	1662	1			T10	1		T26	2		T61	1
valid_sources[0x7a]	1429	1			T1	2		T4	4		T5	1
valid_sources[0x7b]	2182	1			T1	1		T26	3		T108	2
valid_sources[0x7c]	1662	1			T1	2		T6	1		T7	1
valid_sources[0x7d]	1514	1			T9	1		T17	2		T29	1
valid_sources[0x7e]	1896	1			T26	1		T32	1		T80	3
valid_sources[0x7f]	1741	1			T6	1		T17	4		T29	1
valid_sources[0x80]	2322	1			T1	1		T8	2		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

103474

1

T1

24

T3

12

T4

24

values[0x0]

all_enables

biggest_size

151131

1

T11

19510

T12

30209

T13

12606

values[0x1]

all_enables

biggest_size

150956

1

T11

19572

T12

30060

T13

12700

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35433	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

316796

1

T2

5

T3

12

T5

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	91262	1			T3	29		T5	32		T6	32
values[0x0]	121228	1			T2	9		T24	2		T25	6
values[0x1]	139739	1			T2	11		T24	3		T25	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17564	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

334665

1

T2

7

T3

15

T5

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1470	1			T18	1		T11	185		T126	1
valid_sources[0x01]	1313	1			T80	1		T11	153		T127	1
valid_sources[0x02]	1315	1			T11	162		T19	43		T82	5
valid_sources[0x03]	1230	1			T10	2		T11	202		T12	286
valid_sources[0x04]	1349	1			T80	2		T11	140		T81	1
valid_sources[0x05]	1640	1			T2	5		T80	2		T11	165
valid_sources[0x06]	1990	1			T11	173		T12	261		T128	2
valid_sources[0x07]	1370	1			T24	1		T11	178		T34	1
valid_sources[0x08]	1518	1			T61	1		T11	175		T16	2
valid_sources[0x09]	1188	1			T8	1		T24	1		T11	166
valid_sources[0x0a]	1296	1			T80	1		T11	157		T127	1
valid_sources[0x0b]	1301	1			T11	153		T12	265		T13	3
valid_sources[0x0c]	1880	1			T11	169		T129	1		T37	25
valid_sources[0x0d]	1577	1			T10	2		T24	1		T11	149
valid_sources[0x0e]	1279	1			T11	162		T12	250		T13	9
valid_sources[0x0f]	1467	1			T108	2		T18	1		T80	1
valid_sources[0x10]	1632	1			T11	167		T33	5		T126	1
valid_sources[0x11]	1706	1			T2	5		T10	1		T61	1
valid_sources[0x12]	1247	1			T6	1		T10	1		T11	164
valid_sources[0x13]	1613	1			T10	1		T61	1		T11	147
valid_sources[0x14]	1200	1			T6	1		T61	2		T11	158
valid_sources[0x15]	1067	1			T11	168		T130	2		T12	205
valid_sources[0x16]	1224	1			T8	4		T11	162		T81	1
valid_sources[0x17]	2338	1			T11	169		T129	1		T12	262
valid_sources[0x18]	1389	1			T18	1		T80	1		T11	166
valid_sources[0x19]	1315	1			T6	4		T10	1		T131	1
valid_sources[0x1a]	1192	1			T10	1		T11	172		T126	1
valid_sources[0x1b]	1255	1			T61	2		T80	1		T11	164
valid_sources[0x1c]	1361	1			T11	185		T12	208		T92	1
valid_sources[0x1d]	1385	1			T10	1		T80	1		T11	161
valid_sources[0x1e]	1191	1			T17	6		T29	1		T11	136
valid_sources[0x1f]	1249	1			T11	153		T56	4		T81	2
valid_sources[0x20]	1234	1			T8	2		T61	2		T80	1
valid_sources[0x21]	1290	1			T10	1		T18	1		T80	3
valid_sources[0x22]	1298	1			T2	1		T10	1		T14	32
valid_sources[0x23]	1439	1			T6	2		T80	1		T11	169
valid_sources[0x24]	1184	1			T29	1		T11	146		T82	1
valid_sources[0x25]	998	1			T17	1		T29	2		T11	130
valid_sources[0x26]	1463	1			T108	3		T11	173		T82	1
valid_sources[0x27]	1081	1			T11	155		T130	2		T12	210
valid_sources[0x28]	1101	1			T11	159		T132	3		T12	190
valid_sources[0x29]	1249	1			T29	1		T80	1		T131	2
valid_sources[0x2a]	1686	1			T11	171		T133	1		T16	5
valid_sources[0x2b]	1440	1			T11	153		T126	1		T12	242
valid_sources[0x2c]	1557	1			T11	160		T129	1		T12	283
valid_sources[0x2d]	1631	1			T17	4		T80	1		T11	144
valid_sources[0x2e]	1871	1			T11	152		T33	3		T34	1
valid_sources[0x2f]	1261	1			T27	1		T131	1		T11	169
valid_sources[0x30]	1106	1			T10	2		T11	162		T39	1
valid_sources[0x31]	1544	1			T11	162		T82	1		T12	238
valid_sources[0x32]	1237	1			T29	1		T18	1		T131	5
valid_sources[0x33]	2079	1			T11	178		T53	7		T12	273
valid_sources[0x34]	1090	1			T80	1		T11	171		T34	1
valid_sources[0x35]	1014	1			T8	1		T17	1		T11	161
valid_sources[0x36]	1320	1			T80	1		T11	170		T16	1
valid_sources[0x37]	1837	1			T10	1		T11	162		T16	1
valid_sources[0x38]	1269	1			T18	2		T11	146		T81	2
valid_sources[0x39]	1801	1			T10	1		T11	175		T134	2
valid_sources[0x3a]	1249	1			T11	177		T126	1		T12	251
valid_sources[0x3b]	1349	1			T8	1		T10	1		T11	171
valid_sources[0x3c]	1362	1			T11	171		T82	1		T127	1
valid_sources[0x3d]	1446	1			T8	2		T10	1		T11	158
valid_sources[0x3e]	1705	1			T6	2		T8	2		T29	4
valid_sources[0x3f]	1289	1			T10	1		T17	6		T11	140
valid_sources[0x40]	1239	1			T11	177		T127	2		T12	242
valid_sources[0x41]	1176	1			T11	157		T82	1		T133	1
valid_sources[0x42]	1269	1			T80	1		T11	197		T12	255
valid_sources[0x43]	1207	1			T11	154		T126	1		T82	1
valid_sources[0x44]	1220	1			T108	5		T131	1		T11	139
valid_sources[0x45]	1692	1			T80	1		T11	171		T130	1
valid_sources[0x46]	1282	1			T11	154		T34	1		T12	248
valid_sources[0x47]	1174	1			T17	2		T11	151		T126	1
valid_sources[0x48]	1158	1			T11	161		T12	258		T92	2
valid_sources[0x49]	1297	1			T5	32		T10	1		T108	2
valid_sources[0x4a]	1130	1			T11	196		T16	1		T12	275
valid_sources[0x4b]	1402	1			T80	1		T11	170		T129	1
valid_sources[0x4c]	1463	1			T11	172		T129	1		T133	1
valid_sources[0x4d]	1334	1			T108	1		T80	1		T11	179
valid_sources[0x4e]	1365	1			T8	1		T11	171		T12	238
valid_sources[0x4f]	1333	1			T80	1		T11	166		T16	2
valid_sources[0x50]	1170	1			T11	168		T12	213		T92	1
valid_sources[0x51]	1367	1			T80	1		T11	151		T34	1
valid_sources[0x52]	1488	1			T10	1		T11	151		T81	1
valid_sources[0x53]	1281	1			T10	1		T11	159		T67	1
valid_sources[0x54]	1383	1			T108	1		T131	1		T11	169
valid_sources[0x55]	1629	1			T10	2		T29	2		T131	1
valid_sources[0x56]	1579	1			T11	156		T81	1		T135	3
valid_sources[0x57]	1548	1			T10	1		T11	161		T12	208
valid_sources[0x58]	1509	1			T10	2		T11	175		T81	3
valid_sources[0x59]	1731	1			T10	2		T17	1		T11	164
valid_sources[0x5a]	1400	1			T8	1		T11	158		T127	1
valid_sources[0x5b]	1447	1			T11	157		T133	1		T12	269
valid_sources[0x5c]	1239	1			T80	1		T11	155		T127	1
valid_sources[0x5d]	1198	1			T8	3		T11	138		T12	282
valid_sources[0x5e]	1829	1			T11	162		T132	1		T12	265
valid_sources[0x5f]	1302	1			T10	1		T80	1		T131	1
valid_sources[0x60]	1112	1			T6	1		T11	152		T82	1
valid_sources[0x61]	1098	1			T17	3		T80	2		T11	179
valid_sources[0x62]	1820	1			T8	4		T80	2		T11	172
valid_sources[0x63]	1168	1			T108	3		T80	1		T11	155
valid_sources[0x64]	1231	1			T11	178		T33	3		T12	254
valid_sources[0x65]	1369	1			T29	1		T18	1		T11	159
valid_sources[0x66]	1269	1			T10	4		T11	153		T81	1
valid_sources[0x67]	2080	1			T11	179		T64	4		T81	1
valid_sources[0x68]	1370	1			T29	1		T108	5		T11	193
valid_sources[0x69]	1409	1			T18	1		T11	156		T82	1
valid_sources[0x6a]	1160	1			T18	1		T131	2		T11	176
valid_sources[0x6b]	1770	1			T10	1		T11	153		T81	1
valid_sources[0x6c]	1248	1			T136	1		T11	162		T126	1
valid_sources[0x6d]	1797	1			T11	169		T65	1		T132	2
valid_sources[0x6e]	1024	1			T11	131		T12	257		T13	2
valid_sources[0x6f]	1547	1			T6	1		T131	1		T11	153
valid_sources[0x70]	1400	1			T10	1		T80	1		T11	139
valid_sources[0x71]	1490	1			T108	1		T80	1		T11	156
valid_sources[0x72]	1410	1			T61	1		T11	169		T81	1
valid_sources[0x73]	1266	1			T10	2		T80	1		T11	178
valid_sources[0x74]	1663	1			T11	160		T34	1		T12	262
valid_sources[0x75]	1079	1			T8	6		T17	1		T80	1
valid_sources[0x76]	1095	1			T131	1		T11	156		T34	1
valid_sources[0x77]	1465	1			T6	3		T17	3		T11	184
valid_sources[0x78]	1387	1			T8	1		T80	1		T11	158
valid_sources[0x79]	1308	1			T8	12		T10	1		T108	1
valid_sources[0x7a]	1262	1			T10	2		T80	2		T11	165
valid_sources[0x7b]	1349	1			T6	1		T10	1		T11	181
valid_sources[0x7c]	1285	1			T6	1		T11	148		T12	281
valid_sources[0x7d]	1180	1			T10	1		T11	168		T66	4
valid_sources[0x7e]	1417	1			T3	29		T7	32		T61	3
valid_sources[0x7f]	1449	1			T10	1		T17	4		T80	1
valid_sources[0x80]	1047	1			T8	1		T11	182		T81	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

80388

1

T3

12

T5

17

T6

10

values[0x0]

all_enables

biggest_size

118309

1

T2

4

T24

1

T25

2

values[0x1]

all_enables

biggest_size

118099

1

T2

1

T24

1

T11

13976