Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

748935

1

T1

176

T4

243

T5

72

full_word

472545

1

T1

24

T3

8

T4

24

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1221190	1			T1	200		T3	8		T4	267
auto[TlIntgErrCmd]	101	1			T58	7		T59	10		T60	11
auto[TlIntgErrData]	96	1			T59	7		T60	5		T117	3
auto[TlIntgErrBoth]	93	1			T58	3		T59	3		T60	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

209735

1

T1

200

T3

8

T4

267

auto[1]

1011745

1

T11

134583

T12

203547

T13

83601

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	96509	1			T1	176		T4	243		T5	72
auto[TlIntgErrNone]	partial	auto[1]	652153	1			T11	87642		T12	131888		T13	53549
auto[TlIntgErrNone]	full_word	auto[0]	113087	1			T1	24		T3	8		T4	24
auto[TlIntgErrNone]	full_word	auto[1]	359441	1			T11	46941		T12	71659		T13	30052
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T58	3		T59	4		T60	7
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T58	4		T59	6		T60	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T60	1		T116	1		T121	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T122	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T59	3		T60	3		T117	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T59	4		T60	2		T117	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T119	1		T116	2		T123	2
auto[TlIntgErrData]	full_word	auto[1]	1	1			T124	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T58	2		T59	1		T60	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T58	1		T59	2		T60	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T113	1		T122	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T60	1		T114	1		T122	1