Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2636921

1

T1

51

T2

54

T4

258

full_word

1692490

1

T1

5

T2

6

T4

29

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4329101	1			T1	56		T2	60		T4	287
auto[TlIntgErrCmd]	98	1			T51	3		T52	5		T53	3
auto[TlIntgErrData]	105	1			T51	4		T52	11		T53	7
auto[TlIntgErrBoth]	107	1			T51	3		T52	4		T53	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

691200

1

T1

56

T2

60

T4

287

auto[1]

3638211

1

T13

148873

T14

141240

T15

289257

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	290572	1			T1	51		T2	54		T4	258
auto[TlIntgErrNone]	partial	auto[1]	2346064	1			T13	94726		T14	91464		T15	184485
auto[TlIntgErrNone]	full_word	auto[0]	400474	1			T1	5		T2	6		T4	29
auto[TlIntgErrNone]	full_word	auto[1]	1291991	1			T13	54147		T14	49776		T15	104772
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T52	2		T53	2		T99	3
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T51	3		T52	3		T53	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T97	1		T102	1		T103	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T101	1		T104	1		-	-
auto[TlIntgErrData]	partial	auto[0]	54	1			T51	2		T52	8		T53	4
auto[TlIntgErrData]	partial	auto[1]	38	1			T51	1		T52	2		T53	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T52	1		T105	1		T104	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T51	1		T53	1		T98	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T52	1		T53	2		T99	3
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T51	3		T52	3		T53	7
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T102	1		T106	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T53	1		T101	1		T107	1