Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41066	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

746978

1

T5

23

T6

5

T8

150145

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	214418	1			T5	224		T6	49		T8	38142
values[0x0]	281752	1			T8	56908		T24	19505		T25	10958
values[0x1]	291874	1			T8	58806		T24	20092		T25	11403

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20321	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

767723

1

T5

131

T6

30

T8

151750

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3094	1			T8	639		T10	1		T14	5
valid_sources[0x01]	3121	1			T8	572		T13	1		T24	194
valid_sources[0x02]	2947	1			T5	2		T8	537		T16	12
valid_sources[0x03]	3110	1			T5	2		T8	594		T11	12
valid_sources[0x04]	2999	1			T8	525		T13	5		T129	1
valid_sources[0x05]	3009	1			T8	512		T10	1		T13	1
valid_sources[0x06]	3061	1			T5	7		T8	600		T13	1
valid_sources[0x07]	3082	1			T8	529		T10	1		T13	3
valid_sources[0x08]	3060	1			T8	532		T74	1		T39	2
valid_sources[0x09]	3023	1			T8	619		T13	1		T129	1
valid_sources[0x0a]	3018	1			T8	619		T11	5		T74	1
valid_sources[0x0b]	2975	1			T8	600		T13	1		T74	4
valid_sources[0x0c]	2971	1			T5	12		T8	514		T11	2
valid_sources[0x0d]	2953	1			T5	4		T8	581		T129	1
valid_sources[0x0e]	3155	1			T5	2		T8	587		T10	1
valid_sources[0x0f]	3045	1			T5	8		T8	609		T129	1
valid_sources[0x10]	3101	1			T8	619		T129	2		T74	1
valid_sources[0x11]	3158	1			T5	1		T8	640		T13	1
valid_sources[0x12]	3069	1			T8	649		T74	2		T130	1
valid_sources[0x13]	3163	1			T5	1		T8	629		T13	4
valid_sources[0x14]	3053	1			T8	626		T24	195		T25	120
valid_sources[0x15]	2994	1			T8	517		T10	1		T74	1
valid_sources[0x16]	3090	1			T5	2		T8	530		T11	5
valid_sources[0x17]	3026	1			T8	600		T10	1		T129	4
valid_sources[0x18]	3126	1			T8	638		T114	1		T129	1
valid_sources[0x19]	3030	1			T8	611		T129	1		T74	1
valid_sources[0x1a]	3084	1			T8	564		T10	1		T13	1
valid_sources[0x1b]	3027	1			T8	559		T10	1		T13	1
valid_sources[0x1c]	3081	1			T8	572		T129	3		T74	1
valid_sources[0x1d]	3146	1			T8	662		T10	1		T74	3
valid_sources[0x1e]	2919	1			T5	3		T8	525		T129	2
valid_sources[0x1f]	3031	1			T8	606		T13	1		T114	1
valid_sources[0x20]	3089	1			T5	2		T8	635		T10	1
valid_sources[0x21]	3141	1			T8	588		T13	1		T74	2
valid_sources[0x22]	3067	1			T8	622		T13	1		T24	237
valid_sources[0x23]	3027	1			T5	5		T8	654		T10	3
valid_sources[0x24]	3067	1			T5	1		T8	624		T114	1
valid_sources[0x25]	3080	1			T8	622		T13	4		T129	1
valid_sources[0x26]	3033	1			T8	639		T129	1		T130	4
valid_sources[0x27]	3028	1			T8	645		T9	6		T13	2
valid_sources[0x28]	3152	1			T5	4		T8	661		T129	1
valid_sources[0x29]	3027	1			T5	2		T8	618		T129	1
valid_sources[0x2a]	3089	1			T5	4		T8	610		T19	1
valid_sources[0x2b]	3045	1			T8	609		T10	1		T13	2
valid_sources[0x2c]	2916	1			T8	593		T74	1		T24	170
valid_sources[0x2d]	3058	1			T8	622		T14	8		T129	1
valid_sources[0x2e]	3204	1			T8	660		T10	3		T129	1
valid_sources[0x2f]	3150	1			T8	627		T10	2		T11	9
valid_sources[0x30]	3159	1			T8	551		T13	2		T130	1
valid_sources[0x31]	3076	1			T8	652		T13	3		T130	1
valid_sources[0x32]	3136	1			T5	6		T8	587		T13	1
valid_sources[0x33]	3125	1			T5	2		T8	619		T10	2
valid_sources[0x34]	3025	1			T8	606		T13	2		T114	1
valid_sources[0x35]	3140	1			T8	567		T10	2		T129	1
valid_sources[0x36]	3037	1			T8	564		T10	1		T114	2
valid_sources[0x37]	2934	1			T8	543		T13	2		T74	1
valid_sources[0x38]	3200	1			T5	3		T8	633		T13	1
valid_sources[0x39]	3222	1			T5	3		T8	566		T14	4
valid_sources[0x3a]	3041	1			T8	541		T10	1		T114	1
valid_sources[0x3b]	2996	1			T5	2		T8	557		T13	1
valid_sources[0x3c]	3037	1			T8	586		T74	6		T24	201
valid_sources[0x3d]	3026	1			T8	556		T10	2		T11	2
valid_sources[0x3e]	3064	1			T5	1		T8	561		T74	2
valid_sources[0x3f]	3026	1			T5	1		T6	25		T8	617
valid_sources[0x40]	3131	1			T8	647		T129	1		T74	1
valid_sources[0x41]	3213	1			T8	707		T74	1		T24	215
valid_sources[0x42]	3061	1			T8	598		T64	6		T129	1
valid_sources[0x43]	3228	1			T5	1		T8	618		T10	1
valid_sources[0x44]	3122	1			T5	1		T8	657		T13	3
valid_sources[0x45]	3008	1			T8	555		T130	3		T24	177
valid_sources[0x46]	3124	1			T5	4		T8	667		T13	1
valid_sources[0x47]	2986	1			T5	2		T8	592		T13	4
valid_sources[0x48]	3183	1			T8	640		T15	42		T114	2
valid_sources[0x49]	3207	1			T5	3		T8	639		T74	1
valid_sources[0x4a]	3032	1			T8	624		T10	1		T129	1
valid_sources[0x4b]	2978	1			T8	544		T10	1		T114	2
valid_sources[0x4c]	3176	1			T5	2		T8	551		T10	1
valid_sources[0x4d]	3120	1			T8	638		T131	6		T24	200
valid_sources[0x4e]	2989	1			T8	554		T10	2		T113	12
valid_sources[0x4f]	3082	1			T8	594		T74	1		T130	1
valid_sources[0x50]	3042	1			T5	3		T8	564		T74	1
valid_sources[0x51]	2968	1			T8	574		T114	1		T129	2
valid_sources[0x52]	3068	1			T8	625		T14	1		T129	1
valid_sources[0x53]	3014	1			T8	580		T13	2		T114	4
valid_sources[0x54]	3046	1			T8	608		T10	1		T24	192
valid_sources[0x55]	3195	1			T8	698		T10	1		T129	1
valid_sources[0x56]	3065	1			T8	606		T10	2		T13	1
valid_sources[0x57]	2896	1			T8	539		T10	1		T13	5
valid_sources[0x58]	3080	1			T8	626		T10	2		T24	212
valid_sources[0x59]	2995	1			T5	2		T8	611		T10	2
valid_sources[0x5a]	3032	1			T5	8		T8	599		T10	2
valid_sources[0x5b]	3132	1			T8	640		T10	1		T114	1
valid_sources[0x5c]	3024	1			T8	559		T74	2		T130	2
valid_sources[0x5d]	2995	1			T8	660		T13	2		T129	1
valid_sources[0x5e]	3006	1			T8	528		T10	1		T13	1
valid_sources[0x5f]	3081	1			T8	586		T13	2		T129	1
valid_sources[0x60]	3148	1			T8	572		T130	1		T24	231
valid_sources[0x61]	2974	1			T8	568		T13	1		T129	3
valid_sources[0x62]	3099	1			T8	604		T10	1		T129	1
valid_sources[0x63]	2966	1			T5	3		T8	493		T64	9
valid_sources[0x64]	2938	1			T8	633		T74	2		T24	216
valid_sources[0x65]	3008	1			T8	582		T13	1		T130	1
valid_sources[0x66]	3057	1			T8	567		T10	1		T13	1
valid_sources[0x67]	3172	1			T8	582		T10	1		T129	1
valid_sources[0x68]	2967	1			T8	582		T64	2		T129	2
valid_sources[0x69]	2911	1			T5	5		T8	514		T10	1
valid_sources[0x6a]	3167	1			T8	684		T13	1		T129	2
valid_sources[0x6b]	3168	1			T8	640		T129	1		T24	236
valid_sources[0x6c]	3182	1			T8	691		T13	1		T64	3
valid_sources[0x6d]	3036	1			T8	687		T10	1		T129	1
valid_sources[0x6e]	3001	1			T8	599		T13	4		T19	1
valid_sources[0x6f]	3086	1			T8	593		T10	2		T114	2
valid_sources[0x70]	3088	1			T8	603		T64	1		T114	1
valid_sources[0x71]	3044	1			T5	6		T8	539		T10	1
valid_sources[0x72]	3111	1			T8	645		T13	1		T64	2
valid_sources[0x73]	3132	1			T5	3		T8	647		T129	4
valid_sources[0x74]	3228	1			T8	744		T64	12		T74	3
valid_sources[0x75]	2931	1			T8	489		T74	3		T24	206
valid_sources[0x76]	3118	1			T5	2		T8	614		T24	201
valid_sources[0x77]	3105	1			T8	668		T74	1		T24	211
valid_sources[0x78]	3222	1			T5	4		T8	696		T129	1
valid_sources[0x79]	3186	1			T5	5		T8	624		T64	2
valid_sources[0x7a]	3157	1			T8	582		T13	2		T64	10
valid_sources[0x7b]	2998	1			T8	582		T10	1		T74	1
valid_sources[0x7c]	3198	1			T8	617		T13	1		T129	3
valid_sources[0x7d]	3096	1			T8	620		T74	2		T24	223
valid_sources[0x7e]	3123	1			T5	3		T8	640		T74	4
valid_sources[0x7f]	3027	1			T8	607		T10	1		T13	2
valid_sources[0x80]	3049	1			T8	595		T10	1		T13	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

188492

1

T5

23

T6

5

T8

37445

values[0x0]

all_enables

biggest_size

279338

1

T8

56456

T24

19332

T25

10852

values[0x1]

all_enables

biggest_size

279148

1

T8

56244

T24

19214

T25

10875

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59799	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

576077

1

T1

1

T4

1

T5

38

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	161945	1			T1	1		T3	1		T4	1
values[0x0]	219658	1			T2	5		T8	42729		T17	7
values[0x1]	254273	1			T2	5		T8	49655		T17	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28134	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

607742

1

T1

1

T2

1

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2521	1			T8	475		T24	157		T25	74
valid_sources[0x01]	2432	1			T8	442		T24	143		T25	96
valid_sources[0x02]	2351	1			T8	469		T11	1		T38	4
valid_sources[0x03]	2555	1			T8	510		T24	202		T25	103
valid_sources[0x04]	2507	1			T8	482		T14	96		T46	1
valid_sources[0x05]	2561	1			T8	474		T11	4		T40	1
valid_sources[0x06]	2594	1			T8	476		T9	2		T74	2
valid_sources[0x07]	2351	1			T8	443		T24	164		T25	98
valid_sources[0x08]	2470	1			T8	425		T9	1		T24	194
valid_sources[0x09]	2601	1			T8	462		T23	2		T24	158
valid_sources[0x0a]	2400	1			T8	471		T40	1		T24	159
valid_sources[0x0b]	2482	1			T8	477		T24	146		T12	1
valid_sources[0x0c]	2525	1			T8	487		T18	1		T37	1
valid_sources[0x0d]	2536	1			T8	502		T24	153		T25	93
valid_sources[0x0e]	2428	1			T8	439		T37	1		T40	3
valid_sources[0x0f]	2494	1			T8	465		T13	2		T24	147
valid_sources[0x10]	2684	1			T8	482		T24	184		T25	93
valid_sources[0x11]	2371	1			T8	473		T9	1		T24	153
valid_sources[0x12]	2387	1			T8	428		T13	3		T39	4
valid_sources[0x13]	2524	1			T8	434		T74	1		T24	190
valid_sources[0x14]	2580	1			T8	502		T24	184		T25	76
valid_sources[0x15]	2406	1			T6	1		T8	480		T24	151
valid_sources[0x16]	2513	1			T8	500		T23	1		T24	197
valid_sources[0x17]	2614	1			T8	491		T24	217		T25	83
valid_sources[0x18]	2581	1			T8	472		T74	2		T24	167
valid_sources[0x19]	2478	1			T8	492		T74	3		T24	137
valid_sources[0x1a]	2517	1			T8	494		T24	138		T25	86
valid_sources[0x1b]	2406	1			T8	472		T74	3		T131	5
valid_sources[0x1c]	2403	1			T8	454		T37	1		T24	162
valid_sources[0x1d]	2369	1			T8	457		T24	162		T25	109
valid_sources[0x1e]	2367	1			T8	451		T45	1		T74	1
valid_sources[0x1f]	2528	1			T8	483		T38	3		T24	183
valid_sources[0x20]	2602	1			T8	449		T16	7		T24	223
valid_sources[0x21]	2573	1			T8	468		T24	156		T25	104
valid_sources[0x22]	2452	1			T8	450		T24	139		T25	86
valid_sources[0x23]	2458	1			T8	489		T9	1		T24	160
valid_sources[0x24]	2445	1			T8	471		T24	130		T25	101
valid_sources[0x25]	2461	1			T8	477		T24	172		T25	101
valid_sources[0x26]	2430	1			T6	1		T8	482		T24	175
valid_sources[0x27]	2358	1			T8	475		T24	218		T25	83
valid_sources[0x28]	2384	1			T8	489		T24	128		T25	103
valid_sources[0x29]	2423	1			T8	493		T13	4		T17	7
valid_sources[0x2a]	2547	1			T8	469		T13	2		T18	1
valid_sources[0x2b]	2322	1			T8	477		T9	2		T19	1
valid_sources[0x2c]	2407	1			T6	1		T8	462		T9	1
valid_sources[0x2d]	2605	1			T8	508		T24	170		T25	94
valid_sources[0x2e]	2372	1			T1	1		T8	482		T24	119
valid_sources[0x2f]	2349	1			T6	1		T8	464		T13	4
valid_sources[0x30]	2435	1			T8	496		T74	4		T24	160
valid_sources[0x31]	2406	1			T8	448		T24	174		T25	93
valid_sources[0x32]	2502	1			T8	522		T19	5		T131	3
valid_sources[0x33]	2731	1			T8	467		T74	3		T24	179
valid_sources[0x34]	2524	1			T8	491		T24	158		T25	95
valid_sources[0x35]	2456	1			T8	445		T24	193		T25	100
valid_sources[0x36]	2493	1			T8	455		T11	2		T24	180
valid_sources[0x37]	2494	1			T8	452		T18	1		T24	153
valid_sources[0x38]	2618	1			T8	486		T23	1		T38	1
valid_sources[0x39]	2564	1			T8	467		T18	1		T24	185
valid_sources[0x3a]	2366	1			T8	462		T18	1		T24	162
valid_sources[0x3b]	2611	1			T8	477		T18	1		T74	4
valid_sources[0x3c]	2480	1			T8	450		T11	3		T24	135
valid_sources[0x3d]	2295	1			T8	441		T18	1		T38	1
valid_sources[0x3e]	2405	1			T8	489		T40	1		T24	132
valid_sources[0x3f]	2384	1			T6	1		T8	465		T74	2
valid_sources[0x40]	2494	1			T8	476		T24	187		T25	82
valid_sources[0x41]	2544	1			T8	493		T38	4		T24	153
valid_sources[0x42]	2564	1			T8	473		T11	1		T45	1
valid_sources[0x43]	2408	1			T8	472		T38	2		T24	158
valid_sources[0x44]	2456	1			T8	484		T18	1		T74	3
valid_sources[0x45]	2403	1			T8	463		T48	5		T24	160
valid_sources[0x46]	2466	1			T6	1		T8	460		T24	189
valid_sources[0x47]	2513	1			T8	490		T13	4		T24	198
valid_sources[0x48]	2488	1			T6	1		T8	438		T18	1
valid_sources[0x49]	2413	1			T8	489		T13	4		T24	118
valid_sources[0x4a]	2470	1			T8	463		T24	122		T25	106
valid_sources[0x4b]	2613	1			T8	489		T40	1		T131	3
valid_sources[0x4c]	2479	1			T8	467		T40	1		T24	162
valid_sources[0x4d]	2370	1			T8	455		T24	178		T25	88
valid_sources[0x4e]	2442	1			T8	450		T9	2		T24	192
valid_sources[0x4f]	2462	1			T8	482		T9	1		T24	154
valid_sources[0x50]	2340	1			T8	443		T18	1		T24	214
valid_sources[0x51]	2552	1			T8	488		T24	216		T25	92
valid_sources[0x52]	2486	1			T8	484		T24	147		T25	96
valid_sources[0x53]	2500	1			T8	460		T40	1		T24	169
valid_sources[0x54]	2449	1			T8	510		T74	2		T40	2
valid_sources[0x55]	2501	1			T8	448		T18	1		T24	222
valid_sources[0x56]	2471	1			T8	498		T13	3		T24	182
valid_sources[0x57]	2493	1			T8	479		T24	176		T25	81
valid_sources[0x58]	2524	1			T6	1		T8	484		T37	2
valid_sources[0x59]	2339	1			T8	456		T18	1		T24	158
valid_sources[0x5a]	2604	1			T8	483		T74	8		T24	169
valid_sources[0x5b]	2649	1			T8	456		T45	1		T24	207
valid_sources[0x5c]	2615	1			T8	503		T74	4		T24	193
valid_sources[0x5d]	2470	1			T8	496		T9	1		T74	3
valid_sources[0x5e]	2580	1			T8	491		T40	1		T24	190
valid_sources[0x5f]	2669	1			T8	489		T24	205		T25	103
valid_sources[0x60]	2598	1			T8	488		T24	170		T25	94
valid_sources[0x61]	2680	1			T8	497		T24	193		T25	105
valid_sources[0x62]	2366	1			T8	459		T24	146		T25	86
valid_sources[0x63]	2451	1			T8	503		T24	174		T25	120
valid_sources[0x64]	2415	1			T8	473		T24	94		T25	95
valid_sources[0x65]	2409	1			T8	484		T19	1		T24	138
valid_sources[0x66]	2465	1			T8	483		T74	8		T24	182
valid_sources[0x67]	2391	1			T8	492		T74	1		T24	149
valid_sources[0x68]	2436	1			T8	457		T24	134		T25	94
valid_sources[0x69]	2407	1			T8	475		T24	165		T12	1
valid_sources[0x6a]	2342	1			T8	462		T24	181		T25	81
valid_sources[0x6b]	2415	1			T8	442		T24	159		T25	105
valid_sources[0x6c]	2339	1			T6	2		T8	452		T24	126
valid_sources[0x6d]	2532	1			T8	466		T19	1		T24	174
valid_sources[0x6e]	2518	1			T8	495		T11	1		T74	1
valid_sources[0x6f]	2463	1			T6	1		T8	487		T74	1
valid_sources[0x70]	2486	1			T8	516		T24	141		T25	89
valid_sources[0x71]	2642	1			T8	485		T23	1		T24	200
valid_sources[0x72]	2620	1			T8	517		T24	201		T25	102
valid_sources[0x73]	2436	1			T8	462		T24	191		T25	91
valid_sources[0x74]	2432	1			T8	466		T9	2		T74	3
valid_sources[0x75]	2443	1			T8	475		T9	1		T24	170
valid_sources[0x76]	2626	1			T6	1		T8	470		T18	1
valid_sources[0x77]	2483	1			T8	473		T40	2		T24	154
valid_sources[0x78]	2559	1			T8	470		T24	157		T12	1
valid_sources[0x79]	2497	1			T8	480		T16	15		T24	143
valid_sources[0x7a]	2565	1			T8	501		T24	160		T25	99
valid_sources[0x7b]	2397	1			T6	1		T8	474		T17	6
valid_sources[0x7c]	2576	1			T8	495		T40	2		T24	136
valid_sources[0x7d]	2568	1			T8	524		T9	1		T24	165
valid_sources[0x7e]	2582	1			T8	491		T24	225		T12	1
valid_sources[0x7f]	2528	1			T8	473		T11	1		T24	189
valid_sources[0x80]	2366	1			T8	495		T24	160		T25	91

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

146327

1

T1

1

T4

1

T5

38

values[0x0]

all_enables

biggest_size

214749

1

T8

41882

T17

1

T23

1

values[0x1]

all_enables

biggest_size

215001

1

T8

41862

T17

1

T23

3