Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1358966

1

T5

201

T6

44

T8

263191

full_word

869692

1

T5

23

T6

5

T8

174372

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2228408	1			T5	224		T6	49		T8	437563
auto[TlIntgErrCmd]	87	1			T56	3		T57	3		T58	2
auto[TlIntgErrData]	86	1			T56	3		T57	4		T58	4
auto[TlIntgErrBoth]	77	1			T56	4		T57	3		T58	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

363851

1

T5

224

T6

49

T8

67558

auto[1]

1864807

1

T8

370005

T24

129145

T25

75723

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157360	1			T5	201		T6	44		T8	26572
auto[TlIntgErrNone]	partial	auto[1]	1201386	1			T8	236619		T24	83394		T25	49661
auto[TlIntgErrNone]	full_word	auto[0]	206394	1			T5	23		T6	5		T8	40986
auto[TlIntgErrNone]	full_word	auto[1]	663268	1			T8	133386		T24	45751		T25	26062
auto[TlIntgErrCmd]	partial	auto[0]	27	1			T56	1		T57	2		T123	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T56	2		T57	1		T58	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T123	1		T121	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T123	2		T115	1		T116	1
auto[TlIntgErrData]	partial	auto[0]	28	1			T56	1		T57	1		T58	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T56	2		T57	2		T58	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T120	1		T118	1		T126	1
auto[TlIntgErrData]	full_word	auto[1]	11	1			T57	1		T115	2		T116	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T56	2		T123	1		T120	2
auto[TlIntgErrBoth]	partial	auto[1]	40	1			T56	2		T57	3		T58	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T58	1		T118	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T116	1		T124	1		-	-