Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43186	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

801314

1

T1

18

T2

9

T4

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	229032	1			T1	249		T2	9		T4	69
values[0x0]	302097	1			T11	23000		T13	12087		T14	36632
values[0x1]	313371	1			T11	23608		T13	12260		T14	37998

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21712	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

822788

1

T1

144

T2

9

T4

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2747	1			T1	3		T9	2		T11	244
valid_sources[0x01]	3362	1			T11	242		T15	1		T60	2
valid_sources[0x02]	3428	1			T1	5		T11	215		T125	2
valid_sources[0x03]	3016	1			T1	2		T5	2		T7	1
valid_sources[0x04]	3635	1			T7	3		T9	1		T10	2
valid_sources[0x05]	2468	1			T5	1		T8	6		T11	241
valid_sources[0x06]	3444	1			T5	2		T7	5		T9	1
valid_sources[0x07]	3749	1			T10	1		T11	260		T125	2
valid_sources[0x08]	3455	1			T1	6		T5	1		T9	1
valid_sources[0x09]	3247	1			T1	5		T5	2		T7	2
valid_sources[0x0a]	2819	1			T5	2		T7	2		T11	217
valid_sources[0x0b]	3832	1			T5	1		T11	253		T12	1
valid_sources[0x0c]	2854	1			T1	9		T5	2		T7	1
valid_sources[0x0d]	3506	1			T5	5		T9	1		T11	221
valid_sources[0x0e]	2964	1			T5	2		T7	3		T11	247
valid_sources[0x0f]	2760	1			T5	4		T11	255		T12	3
valid_sources[0x10]	3631	1			T1	8		T7	1		T9	3
valid_sources[0x11]	3365	1			T5	1		T7	2		T9	7
valid_sources[0x12]	3314	1			T2	2		T7	3		T10	6
valid_sources[0x13]	3415	1			T9	3		T11	248		T125	1
valid_sources[0x14]	2617	1			T5	1		T7	4		T11	210
valid_sources[0x15]	3892	1			T5	2		T9	8		T11	257
valid_sources[0x16]	3015	1			T1	1		T7	5		T9	3
valid_sources[0x17]	3754	1			T5	5		T10	2		T11	235
valid_sources[0x18]	3568	1			T1	8		T9	1		T11	257
valid_sources[0x19]	3436	1			T5	2		T7	3		T9	2
valid_sources[0x1a]	2772	1			T5	1		T11	286		T74	2
valid_sources[0x1b]	2652	1			T2	2		T9	5		T10	1
valid_sources[0x1c]	3348	1			T5	1		T11	234		T15	1
valid_sources[0x1d]	2583	1			T1	3		T5	3		T7	2
valid_sources[0x1e]	4251	1			T1	1		T5	1		T7	1
valid_sources[0x1f]	2668	1			T11	302		T125	2		T13	119
valid_sources[0x20]	4021	1			T5	2		T7	3		T9	2
valid_sources[0x21]	5190	1			T1	1		T5	3		T11	277
valid_sources[0x22]	3638	1			T5	3		T9	2		T10	1
valid_sources[0x23]	3216	1			T5	1		T11	261		T74	1
valid_sources[0x24]	2781	1			T5	2		T7	3		T11	217
valid_sources[0x25]	3124	1			T5	1		T11	277		T125	2
valid_sources[0x26]	2616	1			T2	1		T5	4		T9	1
valid_sources[0x27]	3179	1			T5	1		T9	4		T10	2
valid_sources[0x28]	4522	1			T5	1		T10	4		T11	237
valid_sources[0x29]	3386	1			T5	2		T9	2		T11	249
valid_sources[0x2a]	3651	1			T7	1		T11	222		T125	3
valid_sources[0x2b]	3933	1			T7	1		T11	249		T15	1
valid_sources[0x2c]	3044	1			T9	2		T11	223		T125	3
valid_sources[0x2d]	3810	1			T5	4		T7	1		T10	1
valid_sources[0x2e]	3343	1			T5	3		T9	2		T11	239
valid_sources[0x2f]	5031	1			T9	1		T11	230		T125	1
valid_sources[0x30]	3389	1			T5	2		T7	9		T9	4
valid_sources[0x31]	2941	1			T5	1		T7	1		T11	267
valid_sources[0x32]	3261	1			T7	3		T9	1		T11	250
valid_sources[0x33]	2876	1			T1	1		T5	1		T10	1
valid_sources[0x34]	2554	1			T5	1		T9	3		T11	235
valid_sources[0x35]	3051	1			T1	10		T10	2		T11	243
valid_sources[0x36]	4376	1			T5	3		T9	2		T11	241
valid_sources[0x37]	3119	1			T5	1		T7	1		T10	2
valid_sources[0x38]	2621	1			T5	1		T7	1		T10	3
valid_sources[0x39]	2807	1			T11	252		T12	1		T125	1
valid_sources[0x3a]	4186	1			T5	1		T9	3		T11	223
valid_sources[0x3b]	2774	1			T5	1		T7	1		T9	1
valid_sources[0x3c]	5032	1			T1	2		T5	2		T10	2
valid_sources[0x3d]	3026	1			T9	1		T11	284		T12	2
valid_sources[0x3e]	3943	1			T1	4		T5	5		T9	2
valid_sources[0x3f]	3335	1			T5	3		T7	2		T9	5
valid_sources[0x40]	4482	1			T10	12		T11	241		T15	1
valid_sources[0x41]	3773	1			T5	2		T9	3		T11	242
valid_sources[0x42]	3383	1			T5	2		T7	3		T9	1
valid_sources[0x43]	4046	1			T5	1		T10	1		T11	223
valid_sources[0x44]	3021	1			T1	1		T7	1		T11	217
valid_sources[0x45]	4279	1			T1	3		T9	1		T11	231
valid_sources[0x46]	3339	1			T1	2		T5	2		T7	5
valid_sources[0x47]	3948	1			T1	6		T5	1		T7	2
valid_sources[0x48]	6745	1			T5	1		T11	209		T60	1
valid_sources[0x49]	3552	1			T1	1		T11	238		T125	3
valid_sources[0x4a]	3070	1			T1	4		T11	215		T12	2
valid_sources[0x4b]	3016	1			T5	1		T11	224		T12	6
valid_sources[0x4c]	3282	1			T5	2		T9	1		T10	2
valid_sources[0x4d]	2985	1			T11	252		T74	1		T125	1
valid_sources[0x4e]	2841	1			T5	3		T10	1		T11	234
valid_sources[0x4f]	3684	1			T5	1		T11	252		T125	4
valid_sources[0x50]	2958	1			T1	4		T5	2		T9	3
valid_sources[0x51]	4020	1			T5	2		T7	4		T9	1
valid_sources[0x52]	2754	1			T5	2		T10	3		T11	241
valid_sources[0x53]	3374	1			T5	2		T11	228		T15	1
valid_sources[0x54]	3401	1			T5	3		T9	1		T11	238
valid_sources[0x55]	3837	1			T1	1		T11	267		T64	1
valid_sources[0x56]	2537	1			T11	234		T15	3		T125	3
valid_sources[0x57]	3009	1			T10	1		T11	251		T58	24
valid_sources[0x58]	2773	1			T1	4		T5	3		T9	1
valid_sources[0x59]	4402	1			T5	1		T11	254		T12	3
valid_sources[0x5a]	3648	1			T5	2		T7	2		T9	1
valid_sources[0x5b]	3056	1			T1	1		T5	1		T7	3
valid_sources[0x5c]	2946	1			T1	1		T9	3		T11	260
valid_sources[0x5d]	3875	1			T5	2		T9	4		T11	264
valid_sources[0x5e]	3955	1			T5	1		T9	1		T11	266
valid_sources[0x5f]	3166	1			T1	4		T5	2		T7	6
valid_sources[0x60]	4138	1			T5	1		T11	254		T16	1
valid_sources[0x61]	3114	1			T1	7		T5	2		T9	3
valid_sources[0x62]	2743	1			T5	2		T9	2		T11	237
valid_sources[0x63]	2543	1			T1	8		T7	3		T11	234
valid_sources[0x64]	2754	1			T5	2		T10	12		T11	218
valid_sources[0x65]	3166	1			T7	7		T11	237		T16	6
valid_sources[0x66]	3232	1			T1	4		T5	3		T7	4
valid_sources[0x67]	2862	1			T10	8		T11	234		T125	1
valid_sources[0x68]	2637	1			T1	5		T5	1		T7	5
valid_sources[0x69]	3500	1			T10	7		T11	245		T15	2
valid_sources[0x6a]	3468	1			T5	1		T7	2		T11	265
valid_sources[0x6b]	3050	1			T5	2		T11	236		T13	121
valid_sources[0x6c]	3273	1			T5	2		T7	2		T9	1
valid_sources[0x6d]	3275	1			T5	2		T9	2		T11	253
valid_sources[0x6e]	4012	1			T5	2		T7	1		T10	4
valid_sources[0x6f]	4175	1			T1	1		T5	1		T10	2
valid_sources[0x70]	2994	1			T5	1		T10	1		T11	256
valid_sources[0x71]	3381	1			T9	1		T11	248		T12	1
valid_sources[0x72]	2663	1			T5	3		T7	1		T9	1
valid_sources[0x73]	2789	1			T5	2		T7	2		T11	268
valid_sources[0x74]	3173	1			T5	1		T7	2		T11	250
valid_sources[0x75]	4018	1			T2	1		T9	2		T11	244
valid_sources[0x76]	2820	1			T1	1		T5	1		T7	1
valid_sources[0x77]	3385	1			T11	268		T15	1		T16	2
valid_sources[0x78]	2761	1			T11	257		T74	1		T125	1
valid_sources[0x79]	2858	1			T5	4		T7	4		T9	4
valid_sources[0x7a]	3765	1			T5	1		T7	2		T9	1
valid_sources[0x7b]	2713	1			T1	2		T5	3		T10	4
valid_sources[0x7c]	2704	1			T5	4		T7	1		T9	1
valid_sources[0x7d]	2760	1			T1	4		T7	6		T9	1
valid_sources[0x7e]	3976	1			T4	35		T5	1		T7	1
valid_sources[0x7f]	4406	1			T5	1		T9	2		T11	220
valid_sources[0x80]	3010	1			T4	16		T5	1		T7	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

202325

1

T1

18

T2

9

T4

4

values[0x0]

all_enables

biggest_size

299405

1

T11

22792

T13

11970

T14

36305

values[0x1]

all_enables

biggest_size

299584

1

T11

22558

T13

11756

T14

36378

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

630989

1

T2

7

T3

1

T6

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	176266	1			T2	18		T3	1		T6	1
values[0x0]	241135	1			T23	5		T24	6		T11	18467
values[0x1]	278231	1			T23	5		T24	8		T11	21338

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

665339

1

T2

10

T3

1

T6

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2756	1			T8	1		T11	196		T13	96
valid_sources[0x01]	2829	1			T11	238		T16	1		T13	106
valid_sources[0x02]	3196	1			T11	255		T13	93		T14	277
valid_sources[0x03]	2188	1			T11	317		T13	88		T41	1
valid_sources[0x04]	2753	1			T11	167		T13	91		T48	1
valid_sources[0x05]	3361	1			T11	253		T13	77		T122	12
valid_sources[0x06]	3172	1			T11	270		T16	2		T64	1
valid_sources[0x07]	2745	1			T11	175		T13	100		T83	1
valid_sources[0x08]	2746	1			T11	226		T13	100		T48	1
valid_sources[0x09]	1671	1			T6	1		T11	233		T66	1
valid_sources[0x0a]	2407	1			T11	217		T13	96		T83	1
valid_sources[0x0b]	2592	1			T11	229		T13	73		T18	3
valid_sources[0x0c]	2126	1			T11	280		T16	1		T66	1
valid_sources[0x0d]	2514	1			T11	220		T16	1		T13	109
valid_sources[0x0e]	2884	1			T11	338		T13	96		T18	1
valid_sources[0x0f]	2692	1			T11	183		T66	3		T13	104
valid_sources[0x10]	2838	1			T8	1		T11	163		T13	96
valid_sources[0x11]	2329	1			T11	171		T13	99		T18	2
valid_sources[0x12]	3301	1			T11	175		T64	1		T13	94
valid_sources[0x13]	2247	1			T11	255		T59	4		T13	102
valid_sources[0x14]	2214	1			T11	111		T13	96		T18	3
valid_sources[0x15]	3370	1			T11	278		T13	99		T83	1
valid_sources[0x16]	3575	1			T11	166		T13	118		T86	1
valid_sources[0x17]	2615	1			T11	201		T13	100		T18	2
valid_sources[0x18]	2719	1			T8	1		T11	169		T13	85
valid_sources[0x19]	2915	1			T8	1		T11	303		T13	88
valid_sources[0x1a]	3184	1			T11	151		T13	100		T40	22
valid_sources[0x1b]	2512	1			T11	147		T13	89		T30	1
valid_sources[0x1c]	4197	1			T11	284		T13	78		T83	1
valid_sources[0x1d]	3018	1			T11	76		T13	90		T88	2
valid_sources[0x1e]	2980	1			T11	154		T13	73		T14	280
valid_sources[0x1f]	3001	1			T11	137		T64	1		T13	86
valid_sources[0x20]	2207	1			T11	137		T13	90		T126	2
valid_sources[0x21]	3115	1			T11	238		T13	93		T126	1
valid_sources[0x22]	2681	1			T8	1		T11	174		T123	4
valid_sources[0x23]	2135	1			T11	291		T70	3		T13	105
valid_sources[0x24]	2763	1			T11	275		T13	84		T18	1
valid_sources[0x25]	2676	1			T11	217		T13	101		T48	1
valid_sources[0x26]	3118	1			T8	1		T11	166		T123	2
valid_sources[0x27]	2920	1			T11	233		T13	106		T48	1
valid_sources[0x28]	1868	1			T11	221		T13	99		T127	10
valid_sources[0x29]	2177	1			T11	241		T13	90		T18	1
valid_sources[0x2a]	3283	1			T11	168		T13	112		T14	260
valid_sources[0x2b]	2452	1			T8	1		T11	151		T66	1
valid_sources[0x2c]	2925	1			T11	268		T16	1		T13	111
valid_sources[0x2d]	2581	1			T11	185		T13	88		T83	1
valid_sources[0x2e]	3352	1			T11	172		T13	112		T43	1
valid_sources[0x2f]	2914	1			T11	295		T64	1		T13	106
valid_sources[0x30]	2219	1			T11	184		T13	97		T83	5
valid_sources[0x31]	2736	1			T8	1		T11	141		T13	100
valid_sources[0x32]	2535	1			T2	1		T11	314		T25	10
valid_sources[0x33]	3063	1			T11	86		T13	86		T30	1
valid_sources[0x34]	2830	1			T11	188		T13	91		T83	4
valid_sources[0x35]	2472	1			T8	1		T11	107		T13	96
valid_sources[0x36]	2322	1			T11	148		T13	92		T86	6
valid_sources[0x37]	2771	1			T11	274		T13	88		T14	421
valid_sources[0x38]	2922	1			T11	239		T16	1		T66	2
valid_sources[0x39]	2750	1			T11	164		T16	2		T13	90
valid_sources[0x3a]	2853	1			T11	206		T13	107		T83	1
valid_sources[0x3b]	2417	1			T11	245		T13	92		T18	2
valid_sources[0x3c]	2748	1			T3	1		T11	99		T123	1
valid_sources[0x3d]	2531	1			T11	201		T13	104		T18	3
valid_sources[0x3e]	2767	1			T11	259		T13	109		T43	2
valid_sources[0x3f]	2214	1			T8	1		T11	160		T13	91
valid_sources[0x40]	2630	1			T11	178		T13	101		T86	1
valid_sources[0x41]	2566	1			T11	185		T16	1		T13	87
valid_sources[0x42]	2896	1			T11	198		T13	112		T83	1
valid_sources[0x43]	2357	1			T11	169		T13	78		T18	2
valid_sources[0x44]	2939	1			T11	238		T13	107		T48	3
valid_sources[0x45]	2387	1			T11	241		T13	76		T83	1
valid_sources[0x46]	2819	1			T11	168		T16	3		T13	84
valid_sources[0x47]	2520	1			T11	231		T51	5		T13	97
valid_sources[0x48]	3076	1			T11	189		T64	1		T66	1
valid_sources[0x49]	2137	1			T11	201		T123	1		T13	90
valid_sources[0x4a]	3360	1			T11	233		T64	1		T13	115
valid_sources[0x4b]	2651	1			T11	172		T13	86		T83	1
valid_sources[0x4c]	2314	1			T11	115		T13	105		T14	394
valid_sources[0x4d]	2187	1			T11	159		T66	2		T13	78
valid_sources[0x4e]	2448	1			T11	109		T66	1		T13	105
valid_sources[0x4f]	3144	1			T11	135		T13	92		T14	306
valid_sources[0x50]	2807	1			T11	191		T66	2		T13	106
valid_sources[0x51]	2354	1			T11	167		T13	107		T18	2
valid_sources[0x52]	2500	1			T11	234		T13	102		T18	2
valid_sources[0x53]	2920	1			T11	174		T16	1		T13	86
valid_sources[0x54]	2384	1			T11	204		T13	115		T45	6
valid_sources[0x55]	2712	1			T11	183		T13	106		T128	11
valid_sources[0x56]	2145	1			T11	250		T19	15		T66	1
valid_sources[0x57]	3133	1			T11	247		T13	90		T83	4
valid_sources[0x58]	2890	1			T11	209		T13	101		T18	2
valid_sources[0x59]	3425	1			T11	292		T64	1		T13	95
valid_sources[0x5a]	3822	1			T11	170		T13	92		T84	2
valid_sources[0x5b]	2508	1			T11	178		T13	86		T48	1
valid_sources[0x5c]	1766	1			T11	76		T13	105		T18	7
valid_sources[0x5d]	2535	1			T8	1		T11	139		T123	1
valid_sources[0x5e]	2771	1			T11	207		T66	1		T13	91
valid_sources[0x5f]	2247	1			T11	157		T13	90		T126	1
valid_sources[0x60]	2585	1			T11	293		T13	92		T83	1
valid_sources[0x61]	2828	1			T11	184		T13	100		T83	1
valid_sources[0x62]	2735	1			T11	339		T13	106		T48	3
valid_sources[0x63]	3026	1			T11	165		T13	95		T85	1
valid_sources[0x64]	2749	1			T24	14		T11	336		T27	1
valid_sources[0x65]	2610	1			T11	131		T16	1		T13	98
valid_sources[0x66]	2848	1			T11	276		T13	95		T83	3
valid_sources[0x67]	3147	1			T11	345		T13	110		T18	4
valid_sources[0x68]	2941	1			T8	1		T11	113		T66	1
valid_sources[0x69]	2599	1			T11	203		T26	1		T64	2
valid_sources[0x6a]	2749	1			T11	206		T64	2		T13	113
valid_sources[0x6b]	2851	1			T2	4		T11	141		T13	69
valid_sources[0x6c]	2383	1			T11	360		T13	88		T20	2
valid_sources[0x6d]	3405	1			T11	93		T66	1		T13	102
valid_sources[0x6e]	2455	1			T11	175		T13	98		T84	1
valid_sources[0x6f]	2622	1			T2	1		T11	279		T16	1
valid_sources[0x70]	3459	1			T23	10		T11	79		T13	94
valid_sources[0x71]	2833	1			T11	160		T64	1		T13	99
valid_sources[0x72]	3044	1			T11	199		T13	113		T83	4
valid_sources[0x73]	2308	1			T11	164		T13	103		T87	17
valid_sources[0x74]	3855	1			T11	223		T13	103		T48	2
valid_sources[0x75]	3390	1			T11	194		T13	100		T72	2
valid_sources[0x76]	2635	1			T11	297		T13	81		T18	2
valid_sources[0x77]	2804	1			T11	271		T66	1		T13	96
valid_sources[0x78]	2842	1			T11	127		T13	92		T30	1
valid_sources[0x79]	2493	1			T11	262		T64	2		T13	97
valid_sources[0x7a]	3106	1			T11	141		T13	93		T83	2
valid_sources[0x7b]	2122	1			T11	174		T64	1		T13	91
valid_sources[0x7c]	3020	1			T11	258		T13	119		T18	1
valid_sources[0x7d]	3319	1			T11	283		T13	94		T83	1
valid_sources[0x7e]	2559	1			T11	347		T13	111		T30	2
valid_sources[0x7f]	2797	1			T11	307		T13	75		T83	1
valid_sources[0x80]	2797	1			T11	258		T64	1		T13	93

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

159654

1

T2

7

T3

1

T6

1

values[0x0]

all_enables

biggest_size

235830

1

T23

2

T24

1

T11

18120

values[0x1]

all_enables

biggest_size

235505

1

T24

1

T11

18159

T25

3