Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1480351

1

T1

231

T4

65

T5

331

full_word

936656

1

T1

18

T2

6

T4

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2416677	1			T1	249		T2	6		T4	69
auto[TlIntgErrCmd]	108	1			T61	1		T62	6		T63	6
auto[TlIntgErrData]	104	1			T61	4		T62	8		T63	6
auto[TlIntgErrBoth]	118	1			T61	5		T62	6		T63	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

393084

1

T1

249

T2

6

T4

69

auto[1]

2023923

1

T11

154132

T13

79766

T14

243545

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	170894	1			T1	231		T4	65		T5	331
auto[TlIntgErrNone]	partial	auto[1]	1309155	1			T11	99994		T13	51441		T14	156921
auto[TlIntgErrNone]	full_word	auto[0]	222031	1			T1	18		T2	6		T4	4
auto[TlIntgErrNone]	full_word	auto[1]	714597	1			T11	54138		T13	28325		T14	86624
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T62	2		T63	2		T111	3
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T62	4		T63	4		T111	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T119	1		T120	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T61	1		T111	1		T117	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T61	1		T62	3		T63	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T61	2		T62	4		T63	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T61	1		T119	1		T118	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T62	1		T63	1		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T61	1		T62	4		T63	4
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T61	3		T62	1		T63	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T61	1		T63	2		T121	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T62	1		T111	1		T117	1