Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 96.89 91.99 97.72 100.00 98.28 97.45 98.37


Total test records in report: 455
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T301 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.537198419 Jun 13 01:11:56 PM PDT 24 Jun 13 01:16:03 PM PDT 24 48854675096 ps
T302 /workspace/coverage/default/24.rom_ctrl_alert_test.1751378910 Jun 13 01:12:42 PM PDT 24 Jun 13 01:13:14 PM PDT 24 12590470370 ps
T303 /workspace/coverage/default/14.rom_ctrl_stress_all.64241019 Jun 13 01:11:53 PM PDT 24 Jun 13 01:12:58 PM PDT 24 4343115114 ps
T304 /workspace/coverage/default/28.rom_ctrl_stress_all.3115191464 Jun 13 01:12:41 PM PDT 24 Jun 13 01:14:21 PM PDT 24 9413667483 ps
T305 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3145835976 Jun 13 01:11:53 PM PDT 24 Jun 13 01:12:19 PM PDT 24 5512556925 ps
T306 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1622485876 Jun 13 01:12:51 PM PDT 24 Jun 13 01:13:53 PM PDT 24 47067434200 ps
T307 /workspace/coverage/default/28.rom_ctrl_smoke.3498607467 Jun 13 01:12:43 PM PDT 24 Jun 13 01:13:10 PM PDT 24 835013426 ps
T308 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2303094962 Jun 13 01:12:25 PM PDT 24 Jun 13 01:12:49 PM PDT 24 10040063934 ps
T309 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1205536867 Jun 13 01:13:26 PM PDT 24 Jun 13 01:13:38 PM PDT 24 184989982 ps
T310 /workspace/coverage/default/36.rom_ctrl_smoke.2085407811 Jun 13 01:12:54 PM PDT 24 Jun 13 01:13:43 PM PDT 24 7650410833 ps
T311 /workspace/coverage/default/24.rom_ctrl_stress_all.3341492762 Jun 13 01:12:26 PM PDT 24 Jun 13 01:14:51 PM PDT 24 61684501031 ps
T312 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3056696415 Jun 13 01:11:39 PM PDT 24 Jun 13 01:22:53 PM PDT 24 86516959013 ps
T313 /workspace/coverage/default/2.rom_ctrl_alert_test.1192921750 Jun 13 01:11:39 PM PDT 24 Jun 13 01:12:05 PM PDT 24 2634801048 ps
T314 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2769260992 Jun 13 01:12:46 PM PDT 24 Jun 13 01:15:59 PM PDT 24 16558869812 ps
T315 /workspace/coverage/default/43.rom_ctrl_stress_all.2709553768 Jun 13 01:13:09 PM PDT 24 Jun 13 01:14:34 PM PDT 24 15314990918 ps
T316 /workspace/coverage/default/28.rom_ctrl_alert_test.2902972206 Jun 13 01:12:40 PM PDT 24 Jun 13 01:13:07 PM PDT 24 5591495964 ps
T317 /workspace/coverage/default/39.rom_ctrl_stress_all.3644899134 Jun 13 01:13:02 PM PDT 24 Jun 13 01:14:21 PM PDT 24 11868228635 ps
T318 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.435384800 Jun 13 01:12:46 PM PDT 24 Jun 13 01:17:22 PM PDT 24 54729202850 ps
T319 /workspace/coverage/default/7.rom_ctrl_smoke.340478718 Jun 13 01:11:47 PM PDT 24 Jun 13 01:12:55 PM PDT 24 8140402766 ps
T320 /workspace/coverage/default/35.rom_ctrl_stress_all.2415542928 Jun 13 01:12:54 PM PDT 24 Jun 13 01:13:13 PM PDT 24 4131619119 ps
T321 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2053548016 Jun 13 01:11:52 PM PDT 24 Jun 13 01:12:17 PM PDT 24 6018870677 ps
T322 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3198414412 Jun 13 01:12:55 PM PDT 24 Jun 13 01:26:04 PM PDT 24 404083817718 ps
T323 /workspace/coverage/default/0.rom_ctrl_smoke.3350948820 Jun 13 01:11:28 PM PDT 24 Jun 13 01:12:13 PM PDT 24 3056813531 ps
T324 /workspace/coverage/default/18.rom_ctrl_alert_test.1955326577 Jun 13 01:12:10 PM PDT 24 Jun 13 01:12:26 PM PDT 24 3593844863 ps
T325 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2895935231 Jun 13 01:11:53 PM PDT 24 Jun 13 01:12:55 PM PDT 24 31392727718 ps
T326 /workspace/coverage/default/31.rom_ctrl_smoke.3657530662 Jun 13 01:12:47 PM PDT 24 Jun 13 01:13:25 PM PDT 24 4956290984 ps
T327 /workspace/coverage/default/19.rom_ctrl_stress_all.2515099636 Jun 13 01:12:11 PM PDT 24 Jun 13 01:12:38 PM PDT 24 854448639 ps
T328 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2089609080 Jun 13 01:12:55 PM PDT 24 Jun 13 01:13:51 PM PDT 24 23967661965 ps
T329 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1499623670 Jun 13 01:13:26 PM PDT 24 Jun 13 01:14:34 PM PDT 24 7980117646 ps
T330 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.277351469 Jun 13 01:12:35 PM PDT 24 Jun 13 01:13:40 PM PDT 24 38408199972 ps
T331 /workspace/coverage/default/48.rom_ctrl_stress_all.2752482252 Jun 13 01:13:24 PM PDT 24 Jun 13 01:13:46 PM PDT 24 373875037 ps
T332 /workspace/coverage/default/37.rom_ctrl_smoke.3056624798 Jun 13 01:12:55 PM PDT 24 Jun 13 01:13:45 PM PDT 24 16430746547 ps
T30 /workspace/coverage/default/0.rom_ctrl_sec_cm.1273255551 Jun 13 01:11:36 PM PDT 24 Jun 13 01:13:33 PM PDT 24 855585067 ps
T333 /workspace/coverage/default/20.rom_ctrl_smoke.1621079827 Jun 13 01:12:10 PM PDT 24 Jun 13 01:13:06 PM PDT 24 41227602210 ps
T334 /workspace/coverage/default/3.rom_ctrl_smoke.3987152550 Jun 13 01:11:39 PM PDT 24 Jun 13 01:12:15 PM PDT 24 1685271635 ps
T335 /workspace/coverage/default/17.rom_ctrl_smoke.1486785507 Jun 13 01:12:02 PM PDT 24 Jun 13 01:12:24 PM PDT 24 1442328530 ps
T336 /workspace/coverage/default/1.rom_ctrl_stress_all.4018309424 Jun 13 01:11:38 PM PDT 24 Jun 13 01:14:05 PM PDT 24 20448278313 ps
T337 /workspace/coverage/default/22.rom_ctrl_stress_all.2595549459 Jun 13 01:12:17 PM PDT 24 Jun 13 01:12:41 PM PDT 24 1762093551 ps
T338 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3870042991 Jun 13 01:12:41 PM PDT 24 Jun 13 01:24:33 PM PDT 24 539403359916 ps
T339 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2629746592 Jun 13 01:13:26 PM PDT 24 Jun 13 01:13:52 PM PDT 24 690184698 ps
T340 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.462461620 Jun 13 01:13:24 PM PDT 24 Jun 13 01:14:00 PM PDT 24 17804870527 ps
T341 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.249976009 Jun 13 01:11:53 PM PDT 24 Jun 13 01:13:03 PM PDT 24 58413415073 ps
T342 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1021481336 Jun 13 01:13:02 PM PDT 24 Jun 13 01:13:32 PM PDT 24 1310942675 ps
T343 /workspace/coverage/default/45.rom_ctrl_stress_all.2353249368 Jun 13 01:13:15 PM PDT 24 Jun 13 01:13:56 PM PDT 24 7079675595 ps
T344 /workspace/coverage/default/37.rom_ctrl_stress_all.2047618393 Jun 13 01:12:55 PM PDT 24 Jun 13 01:14:10 PM PDT 24 4356202125 ps
T345 /workspace/coverage/default/40.rom_ctrl_alert_test.1752741206 Jun 13 01:13:12 PM PDT 24 Jun 13 01:13:44 PM PDT 24 3692623927 ps
T117 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4145215393 Jun 13 01:11:39 PM PDT 24 Jun 13 01:11:51 PM PDT 24 183634797 ps
T346 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1088486703 Jun 13 01:12:08 PM PDT 24 Jun 13 01:17:06 PM PDT 24 16388973010 ps
T347 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2954828393 Jun 13 01:12:55 PM PDT 24 Jun 13 01:13:35 PM PDT 24 12661776975 ps
T348 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.145635790 Jun 13 01:12:07 PM PDT 24 Jun 13 01:12:32 PM PDT 24 2745726254 ps
T349 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.968376565 Jun 13 01:11:39 PM PDT 24 Jun 13 01:12:46 PM PDT 24 7299509271 ps
T350 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2305085886 Jun 13 01:11:53 PM PDT 24 Jun 13 01:12:43 PM PDT 24 24512115167 ps
T351 /workspace/coverage/default/29.rom_ctrl_smoke.2166759123 Jun 13 01:12:41 PM PDT 24 Jun 13 01:14:02 PM PDT 24 33474506575 ps
T352 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.531400836 Jun 13 01:11:38 PM PDT 24 Jun 13 01:14:30 PM PDT 24 18342551313 ps
T353 /workspace/coverage/default/19.rom_ctrl_alert_test.3445196502 Jun 13 01:12:10 PM PDT 24 Jun 13 01:12:19 PM PDT 24 174321467 ps
T354 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1373562530 Jun 13 01:12:38 PM PDT 24 Jun 13 01:12:50 PM PDT 24 606554997 ps
T355 /workspace/coverage/default/6.rom_ctrl_smoke.675903557 Jun 13 01:11:45 PM PDT 24 Jun 13 01:12:57 PM PDT 24 15003992313 ps
T356 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.58429034 Jun 13 01:11:54 PM PDT 24 Jun 13 01:12:21 PM PDT 24 3293078846 ps
T357 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.427244697 Jun 13 01:12:02 PM PDT 24 Jun 13 01:12:31 PM PDT 24 55728389173 ps
T358 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4125720759 Jun 13 01:12:03 PM PDT 24 Jun 13 01:12:28 PM PDT 24 17066004729 ps
T48 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2531303079 Jun 13 02:40:57 PM PDT 24 Jun 13 02:41:28 PM PDT 24 5603687932 ps
T49 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2935548871 Jun 13 02:41:15 PM PDT 24 Jun 13 02:41:35 PM PDT 24 5606299239 ps
T50 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2850925 Jun 13 02:41:14 PM PDT 24 Jun 13 02:42:44 PM PDT 24 4195601901 ps
T78 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3349099628 Jun 13 02:40:56 PM PDT 24 Jun 13 02:41:31 PM PDT 24 14825321561 ps
T79 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2455577740 Jun 13 02:41:09 PM PDT 24 Jun 13 02:41:30 PM PDT 24 7306899774 ps
T118 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4265053095 Jun 13 02:41:15 PM PDT 24 Jun 13 02:42:57 PM PDT 24 21316485746 ps
T51 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.523474822 Jun 13 02:40:56 PM PDT 24 Jun 13 02:41:15 PM PDT 24 993759350 ps
T359 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3311919780 Jun 13 02:41:04 PM PDT 24 Jun 13 02:41:19 PM PDT 24 3808129445 ps
T114 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2219133503 Jun 13 02:41:05 PM PDT 24 Jun 13 02:41:26 PM PDT 24 2353019882 ps
T52 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4068089050 Jun 13 02:41:12 PM PDT 24 Jun 13 02:41:24 PM PDT 24 189208257 ps
T77 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3309572403 Jun 13 02:41:04 PM PDT 24 Jun 13 02:41:36 PM PDT 24 4499352601 ps
T119 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3903206067 Jun 13 02:41:03 PM PDT 24 Jun 13 02:41:32 PM PDT 24 3109783601 ps
T360 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3607283379 Jun 13 02:41:09 PM PDT 24 Jun 13 02:41:30 PM PDT 24 914167864 ps
T80 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2909166285 Jun 13 02:40:55 PM PDT 24 Jun 13 02:41:17 PM PDT 24 1268019352 ps
T361 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1439009291 Jun 13 02:40:57 PM PDT 24 Jun 13 02:41:32 PM PDT 24 11968747316 ps
T81 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1087469629 Jun 13 02:41:16 PM PDT 24 Jun 13 02:41:35 PM PDT 24 3439888071 ps
T62 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.631467409 Jun 13 02:41:13 PM PDT 24 Jun 13 02:42:41 PM PDT 24 460190800 ps
T362 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.729172978 Jun 13 02:41:14 PM PDT 24 Jun 13 02:41:29 PM PDT 24 918078920 ps
T363 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.606384632 Jun 13 02:40:59 PM PDT 24 Jun 13 02:41:30 PM PDT 24 15143732858 ps
T120 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1425618182 Jun 13 02:41:12 PM PDT 24 Jun 13 02:41:43 PM PDT 24 3286771178 ps
T364 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.690990627 Jun 13 02:40:58 PM PDT 24 Jun 13 02:41:12 PM PDT 24 184812658 ps
T63 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1414282875 Jun 13 02:41:08 PM PDT 24 Jun 13 02:42:52 PM PDT 24 3597276590 ps
T82 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.49015001 Jun 13 02:41:13 PM PDT 24 Jun 13 02:41:24 PM PDT 24 688990017 ps
T121 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.969737809 Jun 13 02:41:09 PM PDT 24 Jun 13 02:41:26 PM PDT 24 3277668539 ps
T365 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1237380534 Jun 13 02:41:14 PM PDT 24 Jun 13 02:41:55 PM PDT 24 1434365765 ps
T83 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.78226495 Jun 13 02:41:09 PM PDT 24 Jun 13 02:41:33 PM PDT 24 5326187171 ps
T125 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.420532033 Jun 13 02:40:57 PM PDT 24 Jun 13 02:42:33 PM PDT 24 3073756567 ps
T84 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.493464610 Jun 13 02:41:02 PM PDT 24 Jun 13 02:42:14 PM PDT 24 19241595128 ps
T366 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.269173876 Jun 13 02:40:55 PM PDT 24 Jun 13 02:41:25 PM PDT 24 1507676447 ps
T123 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3287538061 Jun 13 02:41:06 PM PDT 24 Jun 13 02:42:41 PM PDT 24 9247347405 ps
T85 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2088180663 Jun 13 02:41:11 PM PDT 24 Jun 13 02:41:34 PM PDT 24 5470282357 ps
T367 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3571381172 Jun 13 02:41:21 PM PDT 24 Jun 13 02:42:56 PM PDT 24 39781823794 ps
T368 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2011536197 Jun 13 02:40:57 PM PDT 24 Jun 13 02:41:34 PM PDT 24 27548843231 ps
T86 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1746442450 Jun 13 02:41:14 PM PDT 24 Jun 13 02:43:16 PM PDT 24 15060945650 ps
T369 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2493349931 Jun 13 02:40:55 PM PDT 24 Jun 13 02:41:23 PM PDT 24 2230076575 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4046123168 Jun 13 02:41:01 PM PDT 24 Jun 13 02:42:01 PM PDT 24 2145312574 ps
T94 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1738479898 Jun 13 02:41:06 PM PDT 24 Jun 13 02:41:22 PM PDT 24 2469426432 ps
T115 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3017958559 Jun 13 02:41:15 PM PDT 24 Jun 13 02:41:27 PM PDT 24 216839240 ps
T370 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1744116467 Jun 13 02:41:12 PM PDT 24 Jun 13 02:41:43 PM PDT 24 18230046746 ps
T371 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1633481543 Jun 13 02:41:08 PM PDT 24 Jun 13 02:41:39 PM PDT 24 3174501424 ps
T128 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2751228877 Jun 13 02:41:08 PM PDT 24 Jun 13 02:44:02 PM PDT 24 12944716804 ps
T95 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2119350666 Jun 13 02:41:53 PM PDT 24 Jun 13 02:43:43 PM PDT 24 25575793816 ps
T372 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.136756197 Jun 13 02:41:09 PM PDT 24 Jun 13 02:42:09 PM PDT 24 2058306294 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1986374827 Jun 13 02:41:06 PM PDT 24 Jun 13 02:42:31 PM PDT 24 380373689 ps
T130 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3037050294 Jun 13 02:40:55 PM PDT 24 Jun 13 02:42:30 PM PDT 24 4699539128 ps
T374 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3687276487 Jun 13 02:41:03 PM PDT 24 Jun 13 02:41:14 PM PDT 24 167650930 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2794540178 Jun 13 02:40:58 PM PDT 24 Jun 13 02:41:11 PM PDT 24 174383834 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2103636527 Jun 13 02:40:59 PM PDT 24 Jun 13 02:41:32 PM PDT 24 10142227934 ps
T129 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.839202379 Jun 13 02:41:08 PM PDT 24 Jun 13 02:44:12 PM PDT 24 16596955294 ps
T116 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2570772567 Jun 13 02:41:02 PM PDT 24 Jun 13 02:41:31 PM PDT 24 10666047416 ps
T131 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1840248006 Jun 13 02:41:06 PM PDT 24 Jun 13 02:42:37 PM PDT 24 4653420641 ps
T377 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1033421728 Jun 13 02:41:02 PM PDT 24 Jun 13 02:41:34 PM PDT 24 2294658227 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3192250475 Jun 13 02:40:58 PM PDT 24 Jun 13 02:41:24 PM PDT 24 9269412980 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3517703336 Jun 13 02:41:00 PM PDT 24 Jun 13 02:41:26 PM PDT 24 3957075131 ps
T380 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3766302193 Jun 13 02:41:04 PM PDT 24 Jun 13 02:41:28 PM PDT 24 3844323265 ps
T381 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2365035804 Jun 13 02:41:20 PM PDT 24 Jun 13 02:41:36 PM PDT 24 174235773 ps
T96 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1015713280 Jun 13 02:40:57 PM PDT 24 Jun 13 02:41:11 PM PDT 24 460488969 ps
T133 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3954862035 Jun 13 02:41:06 PM PDT 24 Jun 13 02:43:47 PM PDT 24 564657113 ps
T382 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2483972988 Jun 13 02:41:11 PM PDT 24 Jun 13 02:41:46 PM PDT 24 13657940763 ps
T383 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4283182719 Jun 13 02:40:57 PM PDT 24 Jun 13 02:41:14 PM PDT 24 668961862 ps
T384 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.726007261 Jun 13 02:40:55 PM PDT 24 Jun 13 02:41:18 PM PDT 24 576959904 ps
T385 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.577958944 Jun 13 02:41:20 PM PDT 24 Jun 13 02:41:51 PM PDT 24 21591245181 ps
T97 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2187910356 Jun 13 02:40:58 PM PDT 24 Jun 13 02:41:11 PM PDT 24 169288207 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.578121519 Jun 13 02:40:56 PM PDT 24 Jun 13 02:41:24 PM PDT 24 25466035447 ps
T387 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2853788467 Jun 13 02:41:05 PM PDT 24 Jun 13 02:41:37 PM PDT 24 3300679308 ps
T388 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.560188900 Jun 13 02:41:05 PM PDT 24 Jun 13 02:41:21 PM PDT 24 212191451 ps
T389 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3806334576 Jun 13 02:41:09 PM PDT 24 Jun 13 02:41:33 PM PDT 24 1818572840 ps
T390 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2316520451 Jun 13 02:41:14 PM PDT 24 Jun 13 02:41:38 PM PDT 24 4833527631 ps
T391 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3939271371 Jun 13 02:41:10 PM PDT 24 Jun 13 02:41:42 PM PDT 24 14599305091 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1366653986 Jun 13 02:41:05 PM PDT 24 Jun 13 02:41:31 PM PDT 24 5896252225 ps
T132 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.742962144 Jun 13 02:41:14 PM PDT 24 Jun 13 02:44:09 PM PDT 24 3375776485 ps
T124 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1569744702 Jun 13 02:41:09 PM PDT 24 Jun 13 02:43:33 PM PDT 24 67007957234 ps
T134 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2168779524 Jun 13 02:41:20 PM PDT 24 Jun 13 02:44:09 PM PDT 24 3001128653 ps
T393 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1536902374 Jun 13 02:40:56 PM PDT 24 Jun 13 02:41:27 PM PDT 24 5761744494 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2581285651 Jun 13 02:41:06 PM PDT 24 Jun 13 02:41:18 PM PDT 24 174652565 ps
T395 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3377576683 Jun 13 02:41:02 PM PDT 24 Jun 13 02:41:18 PM PDT 24 414806877 ps
T396 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.632463121 Jun 13 02:41:07 PM PDT 24 Jun 13 02:42:43 PM PDT 24 9805785269 ps
T135 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4157821474 Jun 13 02:40:59 PM PDT 24 Jun 13 02:43:53 PM PDT 24 6789148344 ps
T397 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.752525118 Jun 13 02:41:05 PM PDT 24 Jun 13 02:41:20 PM PDT 24 3717838016 ps
T398 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4038973011 Jun 13 02:41:12 PM PDT 24 Jun 13 02:41:50 PM PDT 24 11714462598 ps
T98 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2777747205 Jun 13 02:41:08 PM PDT 24 Jun 13 02:41:49 PM PDT 24 727229272 ps
T399 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3436078778 Jun 13 02:41:07 PM PDT 24 Jun 13 02:41:33 PM PDT 24 4655351778 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1293263034 Jun 13 02:40:54 PM PDT 24 Jun 13 02:41:25 PM PDT 24 3084589008 ps
T401 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1037413609 Jun 13 02:41:16 PM PDT 24 Jun 13 02:41:30 PM PDT 24 171009197 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1604601210 Jun 13 02:41:04 PM PDT 24 Jun 13 02:41:26 PM PDT 24 3653077630 ps
T126 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2043150137 Jun 13 02:41:49 PM PDT 24 Jun 13 02:44:48 PM PDT 24 6724358477 ps
T403 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2610400792 Jun 13 02:41:02 PM PDT 24 Jun 13 02:41:37 PM PDT 24 8057384894 ps
T404 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4112547126 Jun 13 02:41:09 PM PDT 24 Jun 13 02:41:32 PM PDT 24 7501668116 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4165565448 Jun 13 02:40:57 PM PDT 24 Jun 13 02:41:31 PM PDT 24 11497545608 ps
T100 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3882598848 Jun 13 02:41:09 PM PDT 24 Jun 13 02:43:04 PM PDT 24 51703983669 ps
T406 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.899235139 Jun 13 02:41:10 PM PDT 24 Jun 13 02:41:38 PM PDT 24 8504334132 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2169896053 Jun 13 02:40:57 PM PDT 24 Jun 13 02:41:34 PM PDT 24 8325459519 ps
T408 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2408324908 Jun 13 02:41:08 PM PDT 24 Jun 13 02:41:45 PM PDT 24 4276917440 ps
T409 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2488633945 Jun 13 02:41:03 PM PDT 24 Jun 13 02:41:31 PM PDT 24 8540179499 ps
T410 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3162843576 Jun 13 02:41:02 PM PDT 24 Jun 13 02:41:32 PM PDT 24 5688224941 ps
T101 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1417490027 Jun 13 02:41:02 PM PDT 24 Jun 13 02:42:22 PM PDT 24 12386219558 ps
T411 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3644390667 Jun 13 02:41:10 PM PDT 24 Jun 13 02:41:30 PM PDT 24 4327624756 ps
T412 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.733304338 Jun 13 02:41:09 PM PDT 24 Jun 13 02:41:44 PM PDT 24 15360378128 ps
T413 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4185436162 Jun 13 02:40:55 PM PDT 24 Jun 13 02:42:43 PM PDT 24 6981396713 ps
T414 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3030401947 Jun 13 02:41:19 PM PDT 24 Jun 13 02:41:38 PM PDT 24 860089382 ps
T415 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4294860560 Jun 13 02:41:14 PM PDT 24 Jun 13 02:41:44 PM PDT 24 13453322717 ps
T416 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.48356006 Jun 13 02:41:16 PM PDT 24 Jun 13 02:41:40 PM PDT 24 4708274858 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1952279722 Jun 13 02:41:05 PM PDT 24 Jun 13 02:41:34 PM PDT 24 2884307994 ps
T418 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2554542374 Jun 13 02:41:14 PM PDT 24 Jun 13 02:41:39 PM PDT 24 10760854918 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.989657969 Jun 13 02:41:04 PM PDT 24 Jun 13 02:41:27 PM PDT 24 15900970854 ps
T420 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1097348855 Jun 13 02:41:16 PM PDT 24 Jun 13 02:41:57 PM PDT 24 4674767953 ps
T421 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1794088387 Jun 13 02:41:13 PM PDT 24 Jun 13 02:41:46 PM PDT 24 3891479482 ps
T422 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4045919910 Jun 13 02:41:15 PM PDT 24 Jun 13 02:41:35 PM PDT 24 9290329006 ps
T423 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3210131400 Jun 13 02:41:08 PM PDT 24 Jun 13 02:41:25 PM PDT 24 6121378141 ps
T424 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.638076756 Jun 13 02:41:09 PM PDT 24 Jun 13 02:41:44 PM PDT 24 14321400942 ps
T425 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2978665600 Jun 13 02:41:11 PM PDT 24 Jun 13 02:41:38 PM PDT 24 6276020057 ps
T426 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3649261235 Jun 13 02:41:08 PM PDT 24 Jun 13 02:41:37 PM PDT 24 5751522926 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1097616470 Jun 13 02:40:56 PM PDT 24 Jun 13 02:41:18 PM PDT 24 10458886484 ps
T428 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1017370050 Jun 13 02:41:08 PM PDT 24 Jun 13 02:41:45 PM PDT 24 8793813595 ps
T429 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2500962395 Jun 13 02:41:09 PM PDT 24 Jun 13 02:41:30 PM PDT 24 1438339636 ps
T102 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.886744982 Jun 13 02:41:12 PM PDT 24 Jun 13 02:42:13 PM PDT 24 6604199434 ps
T430 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2395244880 Jun 13 02:41:13 PM PDT 24 Jun 13 02:41:37 PM PDT 24 2226200525 ps
T431 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2605073943 Jun 13 02:41:15 PM PDT 24 Jun 13 02:41:54 PM PDT 24 4395447519 ps
T103 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3451281249 Jun 13 02:41:01 PM PDT 24 Jun 13 02:41:31 PM PDT 24 20636145439 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1320301799 Jun 13 02:41:04 PM PDT 24 Jun 13 02:41:21 PM PDT 24 661924345 ps
T433 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1836731567 Jun 13 02:40:55 PM PDT 24 Jun 13 02:41:19 PM PDT 24 1935096003 ps
T127 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2558631967 Jun 13 02:41:01 PM PDT 24 Jun 13 02:44:02 PM PDT 24 8487869224 ps
T434 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3627733662 Jun 13 02:41:05 PM PDT 24 Jun 13 02:41:42 PM PDT 24 9301378921 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2615629928 Jun 13 02:40:59 PM PDT 24 Jun 13 02:41:26 PM PDT 24 9210255590 ps
T436 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.182181955 Jun 13 02:41:10 PM PDT 24 Jun 13 02:41:43 PM PDT 24 15477020080 ps
T437 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3927021602 Jun 13 02:41:00 PM PDT 24 Jun 13 02:44:02 PM PDT 24 5833406263 ps
T438 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3658347305 Jun 13 02:41:15 PM PDT 24 Jun 13 02:42:38 PM PDT 24 13963898853 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1181780818 Jun 13 02:40:55 PM PDT 24 Jun 13 02:43:13 PM PDT 24 17097274813 ps
T440 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3945161260 Jun 13 02:41:08 PM PDT 24 Jun 13 02:42:45 PM PDT 24 9500147964 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2106659266 Jun 13 02:40:56 PM PDT 24 Jun 13 02:41:17 PM PDT 24 176722528 ps
T442 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3518362449 Jun 13 02:41:07 PM PDT 24 Jun 13 02:41:36 PM PDT 24 4161941993 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4117177694 Jun 13 02:41:37 PM PDT 24 Jun 13 02:42:00 PM PDT 24 7472074405 ps
T444 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1977031550 Jun 13 02:41:09 PM PDT 24 Jun 13 02:41:22 PM PDT 24 170951308 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4287833377 Jun 13 02:40:54 PM PDT 24 Jun 13 02:41:09 PM PDT 24 688129182 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.355802281 Jun 13 02:40:57 PM PDT 24 Jun 13 02:43:16 PM PDT 24 17372185387 ps
T447 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.971694307 Jun 13 02:41:07 PM PDT 24 Jun 13 02:41:19 PM PDT 24 688873418 ps
T448 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2561059438 Jun 13 02:41:09 PM PDT 24 Jun 13 02:42:34 PM PDT 24 246314366 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1578070398 Jun 13 02:41:16 PM PDT 24 Jun 13 02:42:56 PM PDT 24 3031790335 ps
T450 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3045849899 Jun 13 02:41:14 PM PDT 24 Jun 13 02:41:33 PM PDT 24 1533551740 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1789079326 Jun 13 02:41:05 PM PDT 24 Jun 13 02:41:17 PM PDT 24 167386043 ps
T452 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1625167323 Jun 13 02:41:14 PM PDT 24 Jun 13 02:41:42 PM PDT 24 5720612292 ps
T453 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.615860412 Jun 13 02:41:05 PM PDT 24 Jun 13 02:41:38 PM PDT 24 2832416411 ps
T99 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.16728872 Jun 13 02:41:06 PM PDT 24 Jun 13 02:43:53 PM PDT 24 36226670765 ps
T454 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.931844447 Jun 13 02:40:57 PM PDT 24 Jun 13 02:42:25 PM PDT 24 28836300273 ps
T455 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.157941845 Jun 13 02:41:07 PM PDT 24 Jun 13 02:41:39 PM PDT 24 3297715209 ps

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3587197731
Short name T9
Test name
Test status
Simulation time 654806631759 ps
CPU time 841.89 seconds
Started Jun 13 01:13:24 PM PDT 24
Finished Jun 13 01:27:27 PM PDT 24
Peak memory 216928 kb
Host smart-8810b8b7-a22e-4ed7-807c-b6a3c54ccf59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587197731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3587197731
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.769463086
Short name T17
Test name
Test status
Simulation time 101802814691 ps
CPU time 1051.7 seconds
Started Jun 13 01:11:40 PM PDT 24
Finished Jun 13 01:29:13 PM PDT 24
Peak memory 238060 kb
Host smart-4b39f6f3-0334-4929-b13c-d9f28c92255b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769463086 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.769463086
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4125013219
Short name T6
Test name
Test status
Simulation time 9989212461 ps
CPU time 91.86 seconds
Started Jun 13 01:13:09 PM PDT 24
Finished Jun 13 01:14:42 PM PDT 24
Peak memory 219320 kb
Host smart-86d5023e-25e4-4b99-9623-806fedee8533
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125013219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4125013219
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2875191924
Short name T40
Test name
Test status
Simulation time 77534920480 ps
CPU time 645.86 seconds
Started Jun 13 01:11:45 PM PDT 24
Finished Jun 13 01:22:32 PM PDT 24
Peak memory 237440 kb
Host smart-3b974a12-bde7-49de-82de-127287949805
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875191924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2875191924
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2683097143
Short name T162
Test name
Test status
Simulation time 4388484994 ps
CPU time 184.09 seconds
Started Jun 13 01:13:03 PM PDT 24
Finished Jun 13 01:16:09 PM PDT 24
Peak memory 218884 kb
Host smart-f4c068f9-d19b-469f-adde-3aad771ced40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683097143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2683097143
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3520728679
Short name T70
Test name
Test status
Simulation time 3266732108 ps
CPU time 26.62 seconds
Started Jun 13 01:12:57 PM PDT 24
Finished Jun 13 01:13:25 PM PDT 24
Peak memory 217176 kb
Host smart-827ed2b6-5416-461d-9077-21d19716f383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520728679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3520728679
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.420532033
Short name T125
Test name
Test status
Simulation time 3073756567 ps
CPU time 90.45 seconds
Started Jun 13 02:40:57 PM PDT 24
Finished Jun 13 02:42:33 PM PDT 24
Peak memory 214272 kb
Host smart-6614fb11-bd83-43e4-bcbd-740abf3e9acb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420532033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.420532033
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3809766552
Short name T8
Test name
Test status
Simulation time 2197244837 ps
CPU time 17.56 seconds
Started Jun 13 01:11:44 PM PDT 24
Finished Jun 13 01:12:02 PM PDT 24
Peak memory 217484 kb
Host smart-f30d443c-e0db-42cd-be44-3dbdae2b728b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3809766552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3809766552
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.839202379
Short name T129
Test name
Test status
Simulation time 16596955294 ps
CPU time 180.01 seconds
Started Jun 13 02:41:08 PM PDT 24
Finished Jun 13 02:44:12 PM PDT 24
Peak memory 215040 kb
Host smart-259711b6-0963-48d7-abe3-79a7745b2d05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839202379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.839202379
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1702904285
Short name T24
Test name
Test status
Simulation time 2472886710 ps
CPU time 231.61 seconds
Started Jun 13 01:11:41 PM PDT 24
Finished Jun 13 01:15:34 PM PDT 24
Peak memory 237432 kb
Host smart-9dc54bd5-133c-405f-936c-c1ebfa329a36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702904285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1702904285
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4046123168
Short name T87
Test name
Test status
Simulation time 2145312574 ps
CPU time 56.29 seconds
Started Jun 13 02:41:01 PM PDT 24
Finished Jun 13 02:42:01 PM PDT 24
Peak memory 215876 kb
Host smart-23fac238-8c8a-45e1-8004-b735e3ebe6b7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046123168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.4046123168
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.427069727
Short name T13
Test name
Test status
Simulation time 886399932 ps
CPU time 20.91 seconds
Started Jun 13 01:13:12 PM PDT 24
Finished Jun 13 01:13:34 PM PDT 24
Peak memory 217008 kb
Host smart-1c9c17c6-d322-4e25-88d1-60daecf4e088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427069727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.427069727
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2043150137
Short name T126
Test name
Test status
Simulation time 6724358477 ps
CPU time 176.08 seconds
Started Jun 13 02:41:49 PM PDT 24
Finished Jun 13 02:44:48 PM PDT 24
Peak memory 214908 kb
Host smart-5297b256-e428-4d60-b093-940fdfa702b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043150137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2043150137
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4265053095
Short name T118
Test name
Test status
Simulation time 21316485746 ps
CPU time 98.76 seconds
Started Jun 13 02:41:15 PM PDT 24
Finished Jun 13 02:42:57 PM PDT 24
Peak memory 214864 kb
Host smart-ec749b4a-e336-4b20-aeb4-c4f3f15fe80c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265053095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4265053095
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3997422544
Short name T163
Test name
Test status
Simulation time 5468467456 ps
CPU time 51.54 seconds
Started Jun 13 01:12:08 PM PDT 24
Finished Jun 13 01:13:00 PM PDT 24
Peak memory 219272 kb
Host smart-2de3bfd3-363c-484a-9f22-befbc9cece15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997422544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3997422544
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2994080687
Short name T43
Test name
Test status
Simulation time 3077549132 ps
CPU time 38.66 seconds
Started Jun 13 01:12:02 PM PDT 24
Finished Jun 13 01:12:42 PM PDT 24
Peak memory 219264 kb
Host smart-5128d201-078f-4af5-a4f2-255f48d508fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994080687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2994080687
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2187910356
Short name T97
Test name
Test status
Simulation time 169288207 ps
CPU time 8.17 seconds
Started Jun 13 02:40:58 PM PDT 24
Finished Jun 13 02:41:11 PM PDT 24
Peak memory 211704 kb
Host smart-c1bc708a-8911-4be7-b3a8-5936049747d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187910356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2187910356
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1840248006
Short name T131
Test name
Test status
Simulation time 4653420641 ps
CPU time 86.98 seconds
Started Jun 13 02:41:06 PM PDT 24
Finished Jun 13 02:42:37 PM PDT 24
Peak memory 214652 kb
Host smart-2492247d-f7c3-491e-b64e-dec08d45943b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840248006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1840248006
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.648579318
Short name T104
Test name
Test status
Simulation time 4145656416 ps
CPU time 24.97 seconds
Started Jun 13 01:11:29 PM PDT 24
Finished Jun 13 01:11:55 PM PDT 24
Peak memory 214516 kb
Host smart-59316393-cd8a-4e08-98d1-8a98bed9ff95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648579318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.648579318
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.358447835
Short name T19
Test name
Test status
Simulation time 80341325655 ps
CPU time 7514.58 seconds
Started Jun 13 01:12:09 PM PDT 24
Finished Jun 13 03:17:25 PM PDT 24
Peak memory 232216 kb
Host smart-c755a544-b916-4d1d-8324-f1a6f0217505
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358447835 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.358447835
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2794540178
Short name T375
Test name
Test status
Simulation time 174383834 ps
CPU time 8.35 seconds
Started Jun 13 02:40:58 PM PDT 24
Finished Jun 13 02:41:11 PM PDT 24
Peak memory 211444 kb
Host smart-dd338b05-5be9-488a-a180-82ad148132b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794540178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2794540178
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1439009291
Short name T361
Test name
Test status
Simulation time 11968747316 ps
CPU time 29.62 seconds
Started Jun 13 02:40:57 PM PDT 24
Finished Jun 13 02:41:32 PM PDT 24
Peak memory 212868 kb
Host smart-81022232-60cc-41e1-a233-2b92188a0b45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439009291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1439009291
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4283182719
Short name T383
Test name
Test status
Simulation time 668961862 ps
CPU time 11.79 seconds
Started Jun 13 02:40:57 PM PDT 24
Finished Jun 13 02:41:14 PM PDT 24
Peak memory 211564 kb
Host smart-e98b385d-12ba-49d6-bdb3-8c89fe2b0deb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283182719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4283182719
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2531303079
Short name T48
Test name
Test status
Simulation time 5603687932 ps
CPU time 25.7 seconds
Started Jun 13 02:40:57 PM PDT 24
Finished Jun 13 02:41:28 PM PDT 24
Peak memory 217364 kb
Host smart-7de0e4ac-4ddb-4a3f-a165-02a374dc1ce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531303079 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2531303079
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3349099628
Short name T78
Test name
Test status
Simulation time 14825321561 ps
CPU time 29.09 seconds
Started Jun 13 02:40:56 PM PDT 24
Finished Jun 13 02:41:31 PM PDT 24
Peak memory 212636 kb
Host smart-39e5005e-c71d-471e-8ce7-46af216c2fdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349099628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3349099628
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2011536197
Short name T368
Test name
Test status
Simulation time 27548843231 ps
CPU time 31.63 seconds
Started Jun 13 02:40:57 PM PDT 24
Finished Jun 13 02:41:34 PM PDT 24
Peak memory 211692 kb
Host smart-aa2b9207-e0fe-4ed5-a8c7-1cc8946d805c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011536197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2011536197
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3517703336
Short name T379
Test name
Test status
Simulation time 3957075131 ps
CPU time 21.84 seconds
Started Jun 13 02:41:00 PM PDT 24
Finished Jun 13 02:41:26 PM PDT 24
Peak memory 211428 kb
Host smart-dbe3a3ad-a8af-493e-ac47-8f0d06ddcc4d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517703336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3517703336
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.355802281
Short name T446
Test name
Test status
Simulation time 17372185387 ps
CPU time 133.04 seconds
Started Jun 13 02:40:57 PM PDT 24
Finished Jun 13 02:43:16 PM PDT 24
Peak memory 216972 kb
Host smart-2d00ac5e-6959-4817-96c2-ddd2c5595c93
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355802281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.355802281
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2909166285
Short name T80
Test name
Test status
Simulation time 1268019352 ps
CPU time 16.24 seconds
Started Jun 13 02:40:55 PM PDT 24
Finished Jun 13 02:41:17 PM PDT 24
Peak memory 211848 kb
Host smart-6fc6906e-6246-48d7-9bd0-677b6a6e80ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909166285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2909166285
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.606384632
Short name T363
Test name
Test status
Simulation time 15143732858 ps
CPU time 26.11 seconds
Started Jun 13 02:40:59 PM PDT 24
Finished Jun 13 02:41:30 PM PDT 24
Peak memory 219444 kb
Host smart-cdde9b38-96fb-4da8-859d-185e178a7f38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606384632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.606384632
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3037050294
Short name T130
Test name
Test status
Simulation time 4699539128 ps
CPU time 88.68 seconds
Started Jun 13 02:40:55 PM PDT 24
Finished Jun 13 02:42:30 PM PDT 24
Peak memory 214704 kb
Host smart-d18dc8b0-8360-4d84-be13-c9ba50028503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037050294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3037050294
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1097616470
Short name T427
Test name
Test status
Simulation time 10458886484 ps
CPU time 16.16 seconds
Started Jun 13 02:40:56 PM PDT 24
Finished Jun 13 02:41:18 PM PDT 24
Peak memory 211688 kb
Host smart-8967d3db-5f8c-4d89-b3e4-1735d69e0922
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097616470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1097616470
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.269173876
Short name T366
Test name
Test status
Simulation time 1507676447 ps
CPU time 24.31 seconds
Started Jun 13 02:40:55 PM PDT 24
Finished Jun 13 02:41:25 PM PDT 24
Peak memory 212352 kb
Host smart-4ce69436-18e1-4933-940b-5772f84c30eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269173876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.269173876
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.690990627
Short name T364
Test name
Test status
Simulation time 184812658 ps
CPU time 8.98 seconds
Started Jun 13 02:40:58 PM PDT 24
Finished Jun 13 02:41:12 PM PDT 24
Peak memory 217468 kb
Host smart-754a6cf9-d2e1-45ad-ad02-5f3ab7b9e44e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690990627 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.690990627
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4287833377
Short name T445
Test name
Test status
Simulation time 688129182 ps
CPU time 8.23 seconds
Started Jun 13 02:40:54 PM PDT 24
Finished Jun 13 02:41:09 PM PDT 24
Peak memory 211660 kb
Host smart-0aa88146-7850-473a-970f-65e92f1dd37d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287833377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4287833377
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2169896053
Short name T407
Test name
Test status
Simulation time 8325459519 ps
CPU time 32.06 seconds
Started Jun 13 02:40:57 PM PDT 24
Finished Jun 13 02:41:34 PM PDT 24
Peak memory 211668 kb
Host smart-ea270a9f-b067-48e5-8be1-05db771e2bd5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169896053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2169896053
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4117177694
Short name T443
Test name
Test status
Simulation time 7472074405 ps
CPU time 18.39 seconds
Started Jun 13 02:41:37 PM PDT 24
Finished Jun 13 02:42:00 PM PDT 24
Peak memory 211348 kb
Host smart-04ec10ce-f2cf-42a6-945e-ab72aa0ba390
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117177694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4117177694
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2119350666
Short name T95
Test name
Test status
Simulation time 25575793816 ps
CPU time 108.52 seconds
Started Jun 13 02:41:53 PM PDT 24
Finished Jun 13 02:43:43 PM PDT 24
Peak memory 214548 kb
Host smart-0f298293-b21e-4314-add1-01b28a4b3f0d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119350666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2119350666
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4165565448
Short name T405
Test name
Test status
Simulation time 11497545608 ps
CPU time 28.43 seconds
Started Jun 13 02:40:57 PM PDT 24
Finished Jun 13 02:41:31 PM PDT 24
Peak memory 213416 kb
Host smart-4137e715-5aa3-4d21-9b79-50874908f1a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165565448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.4165565448
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.726007261
Short name T384
Test name
Test status
Simulation time 576959904 ps
CPU time 17.32 seconds
Started Jun 13 02:40:55 PM PDT 24
Finished Jun 13 02:41:18 PM PDT 24
Peak memory 218132 kb
Host smart-a0a564e8-b3e5-4109-9671-7b118cc854cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726007261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.726007261
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4185436162
Short name T413
Test name
Test status
Simulation time 6981396713 ps
CPU time 101.24 seconds
Started Jun 13 02:40:55 PM PDT 24
Finished Jun 13 02:42:43 PM PDT 24
Peak memory 214708 kb
Host smart-a0236e43-a217-4c8c-8a86-ddb1f565ff72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185436162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4185436162
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1633481543
Short name T371
Test name
Test status
Simulation time 3174501424 ps
CPU time 26.89 seconds
Started Jun 13 02:41:08 PM PDT 24
Finished Jun 13 02:41:39 PM PDT 24
Peak memory 217864 kb
Host smart-969829b0-ca5c-4877-b9a5-835a1ed10041
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633481543 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1633481543
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.969737809
Short name T121
Test name
Test status
Simulation time 3277668539 ps
CPU time 12.61 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:41:26 PM PDT 24
Peak memory 211756 kb
Host smart-62d36620-1eb1-43b3-b72d-2deb9fbb3d87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969737809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.969737809
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.136756197
Short name T372
Test name
Test status
Simulation time 2058306294 ps
CPU time 55.81 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:42:09 PM PDT 24
Peak memory 215584 kb
Host smart-f30256b1-7354-486d-ba22-36eec59fc832
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136756197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.136756197
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3939271371
Short name T391
Test name
Test status
Simulation time 14599305091 ps
CPU time 28.72 seconds
Started Jun 13 02:41:10 PM PDT 24
Finished Jun 13 02:41:42 PM PDT 24
Peak memory 213492 kb
Host smart-0c91ad83-ce9d-4028-9820-3818d44a3681
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939271371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3939271371
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3649261235
Short name T426
Test name
Test status
Simulation time 5751522926 ps
CPU time 24.96 seconds
Started Jun 13 02:41:08 PM PDT 24
Finished Jun 13 02:41:37 PM PDT 24
Peak memory 217944 kb
Host smart-72a622a0-e003-4961-9fcd-3e120a8ca3bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649261235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3649261235
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1414282875
Short name T63
Test name
Test status
Simulation time 3597276590 ps
CPU time 99.81 seconds
Started Jun 13 02:41:08 PM PDT 24
Finished Jun 13 02:42:52 PM PDT 24
Peak memory 214396 kb
Host smart-3fbf2fa4-ee3b-4f02-abe5-2f35afdb94ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414282875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1414282875
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4112547126
Short name T404
Test name
Test status
Simulation time 7501668116 ps
CPU time 18.82 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:41:32 PM PDT 24
Peak memory 216416 kb
Host smart-415975a6-35c3-4c67-9e96-0b49cb61417c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112547126 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4112547126
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2088180663
Short name T85
Test name
Test status
Simulation time 5470282357 ps
CPU time 19.18 seconds
Started Jun 13 02:41:11 PM PDT 24
Finished Jun 13 02:41:34 PM PDT 24
Peak memory 212892 kb
Host smart-b5cf90ba-1014-42b2-888a-91d132e5ed82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088180663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2088180663
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3945161260
Short name T440
Test name
Test status
Simulation time 9500147964 ps
CPU time 92.82 seconds
Started Jun 13 02:41:08 PM PDT 24
Finished Jun 13 02:42:45 PM PDT 24
Peak memory 215836 kb
Host smart-391d9edd-ea96-4de5-a477-7e307a21ffb2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945161260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3945161260
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.733304338
Short name T412
Test name
Test status
Simulation time 15360378128 ps
CPU time 30.89 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:41:44 PM PDT 24
Peak memory 213428 kb
Host smart-98e73c99-6e80-4f44-9271-1df06c88621a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733304338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.733304338
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2483972988
Short name T382
Test name
Test status
Simulation time 13657940763 ps
CPU time 31.88 seconds
Started Jun 13 02:41:11 PM PDT 24
Finished Jun 13 02:41:46 PM PDT 24
Peak memory 219320 kb
Host smart-d3ea2d00-9cd0-4f31-b017-fd86885ec9e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483972988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2483972988
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4068089050
Short name T52
Test name
Test status
Simulation time 189208257 ps
CPU time 9.03 seconds
Started Jun 13 02:41:12 PM PDT 24
Finished Jun 13 02:41:24 PM PDT 24
Peak memory 217328 kb
Host smart-a88e19fa-a0e1-4603-8f4e-603ddeabc3ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068089050 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4068089050
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1425618182
Short name T120
Test name
Test status
Simulation time 3286771178 ps
CPU time 27.51 seconds
Started Jun 13 02:41:12 PM PDT 24
Finished Jun 13 02:41:43 PM PDT 24
Peak memory 212228 kb
Host smart-1b5bf5d9-a231-4733-9a0a-e66ec9bcaa1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425618182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1425618182
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2777747205
Short name T98
Test name
Test status
Simulation time 727229272 ps
CPU time 36.89 seconds
Started Jun 13 02:41:08 PM PDT 24
Finished Jun 13 02:41:49 PM PDT 24
Peak memory 214512 kb
Host smart-6f957225-95c0-46f0-9c1e-51c3917b2b62
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777747205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2777747205
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2978665600
Short name T425
Test name
Test status
Simulation time 6276020057 ps
CPU time 23.11 seconds
Started Jun 13 02:41:11 PM PDT 24
Finished Jun 13 02:41:38 PM PDT 24
Peak memory 213540 kb
Host smart-ad5ba224-2e64-486f-b13d-ee32c1cdaab8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978665600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2978665600
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3607283379
Short name T360
Test name
Test status
Simulation time 914167864 ps
CPU time 17.21 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:41:30 PM PDT 24
Peak memory 219552 kb
Host smart-bb04b568-9296-496f-b277-926e231da2ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607283379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3607283379
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3806334576
Short name T389
Test name
Test status
Simulation time 1818572840 ps
CPU time 20.14 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:41:33 PM PDT 24
Peak memory 219468 kb
Host smart-4ea080a0-019f-4471-892e-282c8e03148b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806334576 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3806334576
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1977031550
Short name T444
Test name
Test status
Simulation time 170951308 ps
CPU time 8.14 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:41:22 PM PDT 24
Peak memory 211696 kb
Host smart-2630ea66-1cd0-40be-9ae1-bb74f4a6f660
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977031550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1977031550
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3882598848
Short name T100
Test name
Test status
Simulation time 51703983669 ps
CPU time 110.9 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:43:04 PM PDT 24
Peak memory 215632 kb
Host smart-86088032-6e79-4645-9424-fe13480e3f71
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882598848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3882598848
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3210131400
Short name T423
Test name
Test status
Simulation time 6121378141 ps
CPU time 12.69 seconds
Started Jun 13 02:41:08 PM PDT 24
Finished Jun 13 02:41:25 PM PDT 24
Peak memory 212244 kb
Host smart-c768e202-aa5e-4d1f-8c39-b3e6614681de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210131400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3210131400
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3518362449
Short name T442
Test name
Test status
Simulation time 4161941993 ps
CPU time 25.3 seconds
Started Jun 13 02:41:07 PM PDT 24
Finished Jun 13 02:41:36 PM PDT 24
Peak memory 218992 kb
Host smart-512b1541-ead1-4181-8851-06a35b8ff0cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518362449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3518362449
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.631467409
Short name T62
Test name
Test status
Simulation time 460190800 ps
CPU time 84.91 seconds
Started Jun 13 02:41:13 PM PDT 24
Finished Jun 13 02:42:41 PM PDT 24
Peak memory 214204 kb
Host smart-ba0e73e2-4722-43bc-a999-c41b46bc915c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631467409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.631467409
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.182181955
Short name T436
Test name
Test status
Simulation time 15477020080 ps
CPU time 29.71 seconds
Started Jun 13 02:41:10 PM PDT 24
Finished Jun 13 02:41:43 PM PDT 24
Peak memory 219376 kb
Host smart-6c8d7ab8-0709-4c13-a45a-b11dac7b65a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182181955 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.182181955
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.78226495
Short name T83
Test name
Test status
Simulation time 5326187171 ps
CPU time 20.3 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:41:33 PM PDT 24
Peak memory 213208 kb
Host smart-be04c440-ce1f-4541-a3b3-3bf04a000d99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78226495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.78226495
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1569744702
Short name T124
Test name
Test status
Simulation time 67007957234 ps
CPU time 139.78 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:43:33 PM PDT 24
Peak memory 214628 kb
Host smart-bde15f2e-90d4-4a52-9567-763cb25497a1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569744702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1569744702
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2500962395
Short name T429
Test name
Test status
Simulation time 1438339636 ps
CPU time 17.05 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:41:30 PM PDT 24
Peak memory 212692 kb
Host smart-43656f6f-a7ae-49f2-9b96-42cd2129c0cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500962395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2500962395
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3644390667
Short name T411
Test name
Test status
Simulation time 4327624756 ps
CPU time 16.82 seconds
Started Jun 13 02:41:10 PM PDT 24
Finished Jun 13 02:41:30 PM PDT 24
Peak memory 219440 kb
Host smart-81898bf3-dcdb-4dab-9200-f52913d13324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644390667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3644390667
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2561059438
Short name T448
Test name
Test status
Simulation time 246314366 ps
CPU time 81.35 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:42:34 PM PDT 24
Peak memory 214168 kb
Host smart-6c964d2b-fb63-4d7c-bcdc-3312e14afd56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561059438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2561059438
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2395244880
Short name T430
Test name
Test status
Simulation time 2226200525 ps
CPU time 20.88 seconds
Started Jun 13 02:41:13 PM PDT 24
Finished Jun 13 02:41:37 PM PDT 24
Peak memory 218800 kb
Host smart-751c4ab4-69a2-45ed-9f2a-c56ce451d786
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395244880 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2395244880
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2554542374
Short name T418
Test name
Test status
Simulation time 10760854918 ps
CPU time 22.55 seconds
Started Jun 13 02:41:14 PM PDT 24
Finished Jun 13 02:41:39 PM PDT 24
Peak memory 213052 kb
Host smart-27e377b8-711d-40e1-a450-f466981b7a27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554542374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2554542374
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1746442450
Short name T86
Test name
Test status
Simulation time 15060945650 ps
CPU time 119.09 seconds
Started Jun 13 02:41:14 PM PDT 24
Finished Jun 13 02:43:16 PM PDT 24
Peak memory 215640 kb
Host smart-dc09089b-e64e-4af5-bb65-84ceb0dda854
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746442450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1746442450
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1087469629
Short name T81
Test name
Test status
Simulation time 3439888071 ps
CPU time 16.73 seconds
Started Jun 13 02:41:16 PM PDT 24
Finished Jun 13 02:41:35 PM PDT 24
Peak memory 213128 kb
Host smart-d0595b2c-833d-4fdf-8fde-adae9938616f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087469629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1087469629
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2316520451
Short name T390
Test name
Test status
Simulation time 4833527631 ps
CPU time 20.56 seconds
Started Jun 13 02:41:14 PM PDT 24
Finished Jun 13 02:41:38 PM PDT 24
Peak memory 219608 kb
Host smart-2de58c87-f18a-4234-8640-3acbbea7bb79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316520451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2316520451
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1578070398
Short name T449
Test name
Test status
Simulation time 3031790335 ps
CPU time 97.09 seconds
Started Jun 13 02:41:16 PM PDT 24
Finished Jun 13 02:42:56 PM PDT 24
Peak memory 214476 kb
Host smart-bea0f396-4727-42dc-94b3-accbbd757c47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578070398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1578070398
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1794088387
Short name T421
Test name
Test status
Simulation time 3891479482 ps
CPU time 29.68 seconds
Started Jun 13 02:41:13 PM PDT 24
Finished Jun 13 02:41:46 PM PDT 24
Peak memory 219292 kb
Host smart-a30202ce-3c1e-4def-a57a-d8f3668c27a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794088387 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1794088387
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.49015001
Short name T82
Test name
Test status
Simulation time 688990017 ps
CPU time 8.13 seconds
Started Jun 13 02:41:13 PM PDT 24
Finished Jun 13 02:41:24 PM PDT 24
Peak memory 211372 kb
Host smart-808f5f26-0a02-4316-8a9d-71524e2f7bc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49015001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.49015001
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1237380534
Short name T365
Test name
Test status
Simulation time 1434365765 ps
CPU time 37.35 seconds
Started Jun 13 02:41:14 PM PDT 24
Finished Jun 13 02:41:55 PM PDT 24
Peak memory 214528 kb
Host smart-0e84088b-cc49-4c99-954c-030c08ddbdf2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237380534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1237380534
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2605073943
Short name T431
Test name
Test status
Simulation time 4395447519 ps
CPU time 35.92 seconds
Started Jun 13 02:41:15 PM PDT 24
Finished Jun 13 02:41:54 PM PDT 24
Peak memory 213360 kb
Host smart-2b40fb13-94ad-4838-bf19-fcc9d2497839
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605073943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2605073943
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.729172978
Short name T362
Test name
Test status
Simulation time 918078920 ps
CPU time 12.41 seconds
Started Jun 13 02:41:14 PM PDT 24
Finished Jun 13 02:41:29 PM PDT 24
Peak memory 217912 kb
Host smart-6aaf4eca-3f6f-4f3b-9aaa-a00326a6c267
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729172978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.729172978
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2168779524
Short name T134
Test name
Test status
Simulation time 3001128653 ps
CPU time 166.99 seconds
Started Jun 13 02:41:20 PM PDT 24
Finished Jun 13 02:44:09 PM PDT 24
Peak memory 214620 kb
Host smart-6e7dc04f-34d6-4f71-b394-80a6e320835f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168779524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2168779524
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.48356006
Short name T416
Test name
Test status
Simulation time 4708274858 ps
CPU time 21.58 seconds
Started Jun 13 02:41:16 PM PDT 24
Finished Jun 13 02:41:40 PM PDT 24
Peak memory 219804 kb
Host smart-431e9032-7f61-4227-9caf-ecec3acfb4aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48356006 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.48356006
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4045919910
Short name T422
Test name
Test status
Simulation time 9290329006 ps
CPU time 17.43 seconds
Started Jun 13 02:41:15 PM PDT 24
Finished Jun 13 02:41:35 PM PDT 24
Peak memory 213204 kb
Host smart-4807f74d-737b-4405-9672-669bf7d75e6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045919910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4045919910
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3045849899
Short name T450
Test name
Test status
Simulation time 1533551740 ps
CPU time 15.49 seconds
Started Jun 13 02:41:14 PM PDT 24
Finished Jun 13 02:41:33 PM PDT 24
Peak memory 212772 kb
Host smart-a2a961d3-2273-4da7-82d0-5c50090aacf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045849899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3045849899
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1037413609
Short name T401
Test name
Test status
Simulation time 171009197 ps
CPU time 11.65 seconds
Started Jun 13 02:41:16 PM PDT 24
Finished Jun 13 02:41:30 PM PDT 24
Peak memory 216888 kb
Host smart-e6c77368-ddd4-4db0-bf5a-327275c9426c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037413609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1037413609
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.742962144
Short name T132
Test name
Test status
Simulation time 3375776485 ps
CPU time 172.28 seconds
Started Jun 13 02:41:14 PM PDT 24
Finished Jun 13 02:44:09 PM PDT 24
Peak memory 214764 kb
Host smart-300ee7c4-c577-41de-b4cd-ddd65deaec21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742962144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.742962144
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2935548871
Short name T49
Test name
Test status
Simulation time 5606299239 ps
CPU time 16.98 seconds
Started Jun 13 02:41:15 PM PDT 24
Finished Jun 13 02:41:35 PM PDT 24
Peak memory 218132 kb
Host smart-eb284d64-8b07-4dab-bb31-ec3441f2c43a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935548871 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2935548871
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1625167323
Short name T452
Test name
Test status
Simulation time 5720612292 ps
CPU time 24.78 seconds
Started Jun 13 02:41:14 PM PDT 24
Finished Jun 13 02:41:42 PM PDT 24
Peak memory 212880 kb
Host smart-6d68a57c-eb20-4150-ac4f-d52ffc9c0981
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625167323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1625167323
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3658347305
Short name T438
Test name
Test status
Simulation time 13963898853 ps
CPU time 80.94 seconds
Started Jun 13 02:41:15 PM PDT 24
Finished Jun 13 02:42:38 PM PDT 24
Peak memory 215824 kb
Host smart-174448a7-1040-4b70-bf72-e05ce616e644
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658347305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3658347305
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3017958559
Short name T115
Test name
Test status
Simulation time 216839240 ps
CPU time 8.28 seconds
Started Jun 13 02:41:15 PM PDT 24
Finished Jun 13 02:41:27 PM PDT 24
Peak memory 211676 kb
Host smart-383d1bf8-99d3-4f47-9582-6be91bc9a661
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017958559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3017958559
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1097348855
Short name T420
Test name
Test status
Simulation time 4674767953 ps
CPU time 37.93 seconds
Started Jun 13 02:41:16 PM PDT 24
Finished Jun 13 02:41:57 PM PDT 24
Peak memory 219668 kb
Host smart-754535e9-c050-459c-8d04-544ac9b2f214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097348855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1097348855
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2850925
Short name T50
Test name
Test status
Simulation time 4195601901 ps
CPU time 87.45 seconds
Started Jun 13 02:41:14 PM PDT 24
Finished Jun 13 02:42:44 PM PDT 24
Peak memory 214212 kb
Host smart-1ddae2aa-7de5-4ee2-bb9c-ea53aa865013
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg
_err.2850925
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.577958944
Short name T385
Test name
Test status
Simulation time 21591245181 ps
CPU time 28.02 seconds
Started Jun 13 02:41:20 PM PDT 24
Finished Jun 13 02:41:51 PM PDT 24
Peak memory 219548 kb
Host smart-50fa2295-a801-4acc-8719-d1a0a5acd042
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577958944 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.577958944
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4294860560
Short name T415
Test name
Test status
Simulation time 13453322717 ps
CPU time 27 seconds
Started Jun 13 02:41:14 PM PDT 24
Finished Jun 13 02:41:44 PM PDT 24
Peak memory 212916 kb
Host smart-25bb6e3d-2281-4fd5-b148-70bd6bc0eecc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294860560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4294860560
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3571381172
Short name T367
Test name
Test status
Simulation time 39781823794 ps
CPU time 92.47 seconds
Started Jun 13 02:41:21 PM PDT 24
Finished Jun 13 02:42:56 PM PDT 24
Peak memory 214804 kb
Host smart-2e2e5e40-b517-4412-945f-e1d31f25c627
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571381172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3571381172
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3030401947
Short name T414
Test name
Test status
Simulation time 860089382 ps
CPU time 17.03 seconds
Started Jun 13 02:41:19 PM PDT 24
Finished Jun 13 02:41:38 PM PDT 24
Peak memory 213144 kb
Host smart-f5fde802-a17e-417b-b525-76e3d1b82103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030401947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3030401947
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2365035804
Short name T381
Test name
Test status
Simulation time 174235773 ps
CPU time 13.69 seconds
Started Jun 13 02:41:20 PM PDT 24
Finished Jun 13 02:41:36 PM PDT 24
Peak memory 218100 kb
Host smart-d62a7fad-aa7b-4969-8837-4f1d81b0d101
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365035804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2365035804
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1015713280
Short name T96
Test name
Test status
Simulation time 460488969 ps
CPU time 8.47 seconds
Started Jun 13 02:40:57 PM PDT 24
Finished Jun 13 02:41:11 PM PDT 24
Peak memory 211656 kb
Host smart-94e228fc-ca6c-4424-a858-0489f37379c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015713280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1015713280
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3627733662
Short name T434
Test name
Test status
Simulation time 9301378921 ps
CPU time 33.21 seconds
Started Jun 13 02:41:05 PM PDT 24
Finished Jun 13 02:41:42 PM PDT 24
Peak memory 212480 kb
Host smart-e8298932-7227-4d69-bc2a-3464a82c1a16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627733662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3627733662
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2106659266
Short name T441
Test name
Test status
Simulation time 176722528 ps
CPU time 15.55 seconds
Started Jun 13 02:40:56 PM PDT 24
Finished Jun 13 02:41:17 PM PDT 24
Peak memory 212336 kb
Host smart-a83e9dbb-db5e-4974-b6f7-98d1ee6aa58c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106659266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2106659266
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1293263034
Short name T400
Test name
Test status
Simulation time 3084589008 ps
CPU time 24.72 seconds
Started Jun 13 02:40:54 PM PDT 24
Finished Jun 13 02:41:25 PM PDT 24
Peak memory 215104 kb
Host smart-ddc5cbe3-15cb-4282-86c8-670baefd818d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293263034 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1293263034
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1836731567
Short name T433
Test name
Test status
Simulation time 1935096003 ps
CPU time 18.34 seconds
Started Jun 13 02:40:55 PM PDT 24
Finished Jun 13 02:41:19 PM PDT 24
Peak memory 212524 kb
Host smart-74226944-d185-4786-9c42-58191668bb9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836731567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1836731567
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1536902374
Short name T393
Test name
Test status
Simulation time 5761744494 ps
CPU time 25.07 seconds
Started Jun 13 02:40:56 PM PDT 24
Finished Jun 13 02:41:27 PM PDT 24
Peak memory 211416 kb
Host smart-4b846403-15e6-46d0-9307-ba148eee67ae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536902374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1536902374
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.578121519
Short name T386
Test name
Test status
Simulation time 25466035447 ps
CPU time 21.89 seconds
Started Jun 13 02:40:56 PM PDT 24
Finished Jun 13 02:41:24 PM PDT 24
Peak memory 211700 kb
Host smart-8d2c08b1-0a44-407c-a399-ceba5e573df9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578121519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
578121519
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1181780818
Short name T439
Test name
Test status
Simulation time 17097274813 ps
CPU time 131.49 seconds
Started Jun 13 02:40:55 PM PDT 24
Finished Jun 13 02:43:13 PM PDT 24
Peak memory 215008 kb
Host smart-0ace0db0-a8e5-404c-8523-b068726851fa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181780818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1181780818
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2615629928
Short name T435
Test name
Test status
Simulation time 9210255590 ps
CPU time 21.91 seconds
Started Jun 13 02:40:59 PM PDT 24
Finished Jun 13 02:41:26 PM PDT 24
Peak memory 213364 kb
Host smart-725bd6f1-806b-4f6f-8d98-f9f5e957c67c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615629928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2615629928
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2103636527
Short name T376
Test name
Test status
Simulation time 10142227934 ps
CPU time 28.31 seconds
Started Jun 13 02:40:59 PM PDT 24
Finished Jun 13 02:41:32 PM PDT 24
Peak memory 219608 kb
Host smart-f3232b1b-1746-4956-8405-45c5a73d39e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103636527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2103636527
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1789079326
Short name T451
Test name
Test status
Simulation time 167386043 ps
CPU time 8.82 seconds
Started Jun 13 02:41:05 PM PDT 24
Finished Jun 13 02:41:17 PM PDT 24
Peak memory 211396 kb
Host smart-02d96593-da7b-4121-8645-6e701e330593
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789079326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1789079326
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1604601210
Short name T402
Test name
Test status
Simulation time 3653077630 ps
CPU time 18.7 seconds
Started Jun 13 02:41:04 PM PDT 24
Finished Jun 13 02:41:26 PM PDT 24
Peak memory 211516 kb
Host smart-c3cef804-2529-4a75-8281-1416f56d0257
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604601210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1604601210
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3451281249
Short name T103
Test name
Test status
Simulation time 20636145439 ps
CPU time 25.85 seconds
Started Jun 13 02:41:01 PM PDT 24
Finished Jun 13 02:41:31 PM PDT 24
Peak memory 213160 kb
Host smart-5ab38a2a-57a9-4597-9f9a-94147de46dca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451281249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3451281249
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3766302193
Short name T380
Test name
Test status
Simulation time 3844323265 ps
CPU time 19.55 seconds
Started Jun 13 02:41:04 PM PDT 24
Finished Jun 13 02:41:28 PM PDT 24
Peak memory 219696 kb
Host smart-1adb928e-1b33-4b1b-8ec2-08c484dcc44a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766302193 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3766302193
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3687276487
Short name T374
Test name
Test status
Simulation time 167650930 ps
CPU time 8.01 seconds
Started Jun 13 02:41:03 PM PDT 24
Finished Jun 13 02:41:14 PM PDT 24
Peak memory 211360 kb
Host smart-afad0978-9d74-4a4c-bdab-f6cd8a1572f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687276487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3687276487
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3192250475
Short name T378
Test name
Test status
Simulation time 9269412980 ps
CPU time 21.37 seconds
Started Jun 13 02:40:58 PM PDT 24
Finished Jun 13 02:41:24 PM PDT 24
Peak memory 211384 kb
Host smart-bb8ab2ba-8c6d-431f-a1e9-b93477bd9fcb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192250475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3192250475
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2493349931
Short name T369
Test name
Test status
Simulation time 2230076575 ps
CPU time 22.15 seconds
Started Jun 13 02:40:55 PM PDT 24
Finished Jun 13 02:41:23 PM PDT 24
Peak memory 211440 kb
Host smart-b68d3a70-7eb6-4029-8546-13692ddfd101
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493349931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2493349931
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.931844447
Short name T454
Test name
Test status
Simulation time 28836300273 ps
CPU time 82.96 seconds
Started Jun 13 02:40:57 PM PDT 24
Finished Jun 13 02:42:25 PM PDT 24
Peak memory 214780 kb
Host smart-cbe2943b-6cd7-4365-825c-4bca67a277bb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931844447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.931844447
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2570772567
Short name T116
Test name
Test status
Simulation time 10666047416 ps
CPU time 25.43 seconds
Started Jun 13 02:41:02 PM PDT 24
Finished Jun 13 02:41:31 PM PDT 24
Peak memory 213500 kb
Host smart-526084f1-5843-4474-b51c-b4892fb3fcf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570772567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2570772567
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.523474822
Short name T51
Test name
Test status
Simulation time 993759350 ps
CPU time 12.89 seconds
Started Jun 13 02:40:56 PM PDT 24
Finished Jun 13 02:41:15 PM PDT 24
Peak memory 217760 kb
Host smart-abd9a55a-5d3d-475a-b0fc-02e1c1bed84a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523474822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.523474822
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4157821474
Short name T135
Test name
Test status
Simulation time 6789148344 ps
CPU time 168.87 seconds
Started Jun 13 02:40:59 PM PDT 24
Finished Jun 13 02:43:53 PM PDT 24
Peak memory 215068 kb
Host smart-29d3e8e3-e4a0-4e35-bc28-212d29a51eae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157821474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4157821474
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1366653986
Short name T392
Test name
Test status
Simulation time 5896252225 ps
CPU time 22.88 seconds
Started Jun 13 02:41:05 PM PDT 24
Finished Jun 13 02:41:31 PM PDT 24
Peak memory 212708 kb
Host smart-7d61d21c-0bc4-488f-b4bd-f352a6be5d8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366653986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1366653986
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3311919780
Short name T359
Test name
Test status
Simulation time 3808129445 ps
CPU time 11.97 seconds
Started Jun 13 02:41:04 PM PDT 24
Finished Jun 13 02:41:19 PM PDT 24
Peak memory 211580 kb
Host smart-6f4d5bda-c7c5-48b8-a274-b5a9a56d1e5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311919780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3311919780
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1017370050
Short name T428
Test name
Test status
Simulation time 8793813595 ps
CPU time 32.67 seconds
Started Jun 13 02:41:08 PM PDT 24
Finished Jun 13 02:41:45 PM PDT 24
Peak memory 212604 kb
Host smart-2c25c3c9-fb60-43ac-a921-5fa4cdce48d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017370050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1017370050
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.989657969
Short name T419
Test name
Test status
Simulation time 15900970854 ps
CPU time 20.35 seconds
Started Jun 13 02:41:04 PM PDT 24
Finished Jun 13 02:41:27 PM PDT 24
Peak memory 219060 kb
Host smart-2196e279-baca-4847-bbab-f16536215e53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989657969 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.989657969
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1738479898
Short name T94
Test name
Test status
Simulation time 2469426432 ps
CPU time 12.29 seconds
Started Jun 13 02:41:06 PM PDT 24
Finished Jun 13 02:41:22 PM PDT 24
Peak memory 211844 kb
Host smart-601f1f9c-7919-4149-ba0f-3cc90169bce9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738479898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1738479898
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1952279722
Short name T417
Test name
Test status
Simulation time 2884307994 ps
CPU time 25.36 seconds
Started Jun 13 02:41:05 PM PDT 24
Finished Jun 13 02:41:34 PM PDT 24
Peak memory 211428 kb
Host smart-73b3d613-d9b9-4ae9-8660-a74330ead6d7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952279722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1952279722
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2581285651
Short name T394
Test name
Test status
Simulation time 174652565 ps
CPU time 8.57 seconds
Started Jun 13 02:41:06 PM PDT 24
Finished Jun 13 02:41:18 PM PDT 24
Peak memory 211296 kb
Host smart-22cc2229-fcbc-4527-baf0-52ab0a1914c2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581285651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2581285651
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3162843576
Short name T410
Test name
Test status
Simulation time 5688224941 ps
CPU time 26.09 seconds
Started Jun 13 02:41:02 PM PDT 24
Finished Jun 13 02:41:32 PM PDT 24
Peak memory 213484 kb
Host smart-0c57404a-b2bf-4d3c-97f9-21ea129ead7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162843576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3162843576
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1320301799
Short name T432
Test name
Test status
Simulation time 661924345 ps
CPU time 13.5 seconds
Started Jun 13 02:41:04 PM PDT 24
Finished Jun 13 02:41:21 PM PDT 24
Peak memory 218000 kb
Host smart-125c5304-8ee0-45c0-82e3-73b46d405aad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320301799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1320301799
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1986374827
Short name T373
Test name
Test status
Simulation time 380373689 ps
CPU time 81.87 seconds
Started Jun 13 02:41:06 PM PDT 24
Finished Jun 13 02:42:31 PM PDT 24
Peak memory 214036 kb
Host smart-dada5061-7a98-4851-8498-cb6a3ea674c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986374827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1986374827
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3309572403
Short name T77
Test name
Test status
Simulation time 4499352601 ps
CPU time 28.44 seconds
Started Jun 13 02:41:04 PM PDT 24
Finished Jun 13 02:41:36 PM PDT 24
Peak memory 217424 kb
Host smart-1537b91d-5d07-44c3-9ab8-dfdad9a5f6de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309572403 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3309572403
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3903206067
Short name T119
Test name
Test status
Simulation time 3109783601 ps
CPU time 25.8 seconds
Started Jun 13 02:41:03 PM PDT 24
Finished Jun 13 02:41:32 PM PDT 24
Peak memory 212468 kb
Host smart-bc610bde-53f9-4e43-919f-b169355c4e5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903206067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3903206067
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.493464610
Short name T84
Test name
Test status
Simulation time 19241595128 ps
CPU time 67.94 seconds
Started Jun 13 02:41:02 PM PDT 24
Finished Jun 13 02:42:14 PM PDT 24
Peak memory 214692 kb
Host smart-250be72d-76e0-4deb-ba90-670e64676aad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493464610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.493464610
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.971694307
Short name T447
Test name
Test status
Simulation time 688873418 ps
CPU time 8.36 seconds
Started Jun 13 02:41:07 PM PDT 24
Finished Jun 13 02:41:19 PM PDT 24
Peak memory 211896 kb
Host smart-933c2040-ad0d-4788-91e0-9291f2aa34d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971694307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.971694307
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1033421728
Short name T377
Test name
Test status
Simulation time 2294658227 ps
CPU time 28.02 seconds
Started Jun 13 02:41:02 PM PDT 24
Finished Jun 13 02:41:34 PM PDT 24
Peak memory 219340 kb
Host smart-0cd19755-1c56-40a3-b150-8f9be40d304e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033421728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1033421728
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2558631967
Short name T127
Test name
Test status
Simulation time 8487869224 ps
CPU time 177.31 seconds
Started Jun 13 02:41:01 PM PDT 24
Finished Jun 13 02:44:02 PM PDT 24
Peak memory 214768 kb
Host smart-8afddfcf-212e-4e83-9f70-03470a9df080
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558631967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2558631967
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3436078778
Short name T399
Test name
Test status
Simulation time 4655351778 ps
CPU time 22.21 seconds
Started Jun 13 02:41:07 PM PDT 24
Finished Jun 13 02:41:33 PM PDT 24
Peak memory 219728 kb
Host smart-da969dff-fb3d-4e19-b386-9fb98856c1fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436078778 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3436078778
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.752525118
Short name T397
Test name
Test status
Simulation time 3717838016 ps
CPU time 10.94 seconds
Started Jun 13 02:41:05 PM PDT 24
Finished Jun 13 02:41:20 PM PDT 24
Peak memory 211604 kb
Host smart-738e50e6-bfed-4aea-814c-e71ca75bf627
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752525118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.752525118
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1417490027
Short name T101
Test name
Test status
Simulation time 12386219558 ps
CPU time 76.29 seconds
Started Jun 13 02:41:02 PM PDT 24
Finished Jun 13 02:42:22 PM PDT 24
Peak memory 214652 kb
Host smart-d672720e-0448-45f4-a939-b2a548fffa91
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417490027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1417490027
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.560188900
Short name T388
Test name
Test status
Simulation time 212191451 ps
CPU time 12.02 seconds
Started Jun 13 02:41:05 PM PDT 24
Finished Jun 13 02:41:21 PM PDT 24
Peak memory 213008 kb
Host smart-fcf4a23c-1e52-4290-b68c-35ef2b4fdf82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560188900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.560188900
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.615860412
Short name T453
Test name
Test status
Simulation time 2832416411 ps
CPU time 28.85 seconds
Started Jun 13 02:41:05 PM PDT 24
Finished Jun 13 02:41:38 PM PDT 24
Peak memory 217936 kb
Host smart-d47aec38-7cf6-472c-8519-41c4110ec5e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615860412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.615860412
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3954862035
Short name T133
Test name
Test status
Simulation time 564657113 ps
CPU time 157.81 seconds
Started Jun 13 02:41:06 PM PDT 24
Finished Jun 13 02:43:47 PM PDT 24
Peak memory 214480 kb
Host smart-defe6f11-1a80-4b4b-943d-e4da1ffa358c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954862035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3954862035
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2610400792
Short name T403
Test name
Test status
Simulation time 8057384894 ps
CPU time 31.38 seconds
Started Jun 13 02:41:02 PM PDT 24
Finished Jun 13 02:41:37 PM PDT 24
Peak memory 218220 kb
Host smart-f339db84-06d1-4f4f-9179-564f3d8c8f36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610400792 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2610400792
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2853788467
Short name T387
Test name
Test status
Simulation time 3300679308 ps
CPU time 27.96 seconds
Started Jun 13 02:41:05 PM PDT 24
Finished Jun 13 02:41:37 PM PDT 24
Peak memory 212608 kb
Host smart-c6cd3728-d5ca-4ed6-8c14-c42d7869eb0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853788467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2853788467
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.16728872
Short name T99
Test name
Test status
Simulation time 36226670765 ps
CPU time 163.34 seconds
Started Jun 13 02:41:06 PM PDT 24
Finished Jun 13 02:43:53 PM PDT 24
Peak memory 219736 kb
Host smart-748cfe28-f44b-4ea1-a7ef-264f7df95839
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16728872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pass
thru_mem_tl_intg_err.16728872
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2219133503
Short name T114
Test name
Test status
Simulation time 2353019882 ps
CPU time 17.96 seconds
Started Jun 13 02:41:05 PM PDT 24
Finished Jun 13 02:41:26 PM PDT 24
Peak memory 213108 kb
Host smart-448cc1fc-ded5-4efc-acbd-e1fe08cccd85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219133503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2219133503
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3377576683
Short name T395
Test name
Test status
Simulation time 414806877 ps
CPU time 12.51 seconds
Started Jun 13 02:41:02 PM PDT 24
Finished Jun 13 02:41:18 PM PDT 24
Peak memory 217888 kb
Host smart-5f0364d2-8da8-4a4c-a15a-3750ee602233
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377576683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3377576683
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3927021602
Short name T437
Test name
Test status
Simulation time 5833406263 ps
CPU time 177 seconds
Started Jun 13 02:41:00 PM PDT 24
Finished Jun 13 02:44:02 PM PDT 24
Peak memory 219696 kb
Host smart-bf110795-f8ea-43db-9cf0-94bf80c10386
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927021602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3927021602
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1744116467
Short name T370
Test name
Test status
Simulation time 18230046746 ps
CPU time 27.55 seconds
Started Jun 13 02:41:12 PM PDT 24
Finished Jun 13 02:41:43 PM PDT 24
Peak memory 218752 kb
Host smart-7fad2d66-d234-4c5b-a06a-7ff7c0fbeafc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744116467 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1744116467
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2455577740
Short name T79
Test name
Test status
Simulation time 7306899774 ps
CPU time 16.22 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:41:30 PM PDT 24
Peak memory 211740 kb
Host smart-96e70dc0-c5b7-434c-a6b2-9004ef078676
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455577740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2455577740
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3287538061
Short name T123
Test name
Test status
Simulation time 9247347405 ps
CPU time 90.84 seconds
Started Jun 13 02:41:06 PM PDT 24
Finished Jun 13 02:42:41 PM PDT 24
Peak memory 214708 kb
Host smart-80ab674e-b9f8-401e-8a51-c5be7a8bd010
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287538061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3287538061
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4038973011
Short name T398
Test name
Test status
Simulation time 11714462598 ps
CPU time 34.16 seconds
Started Jun 13 02:41:12 PM PDT 24
Finished Jun 13 02:41:50 PM PDT 24
Peak memory 213552 kb
Host smart-6849f132-ba40-4b1f-8042-0ab4f23b37ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038973011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4038973011
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2488633945
Short name T409
Test name
Test status
Simulation time 8540179499 ps
CPU time 24.74 seconds
Started Jun 13 02:41:03 PM PDT 24
Finished Jun 13 02:41:31 PM PDT 24
Peak memory 219232 kb
Host smart-837e2c38-bdb7-47d7-9b40-e1da1448da45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488633945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2488633945
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.632463121
Short name T396
Test name
Test status
Simulation time 9805785269 ps
CPU time 91.85 seconds
Started Jun 13 02:41:07 PM PDT 24
Finished Jun 13 02:42:43 PM PDT 24
Peak memory 219748 kb
Host smart-67285e3c-4ae7-4a0f-9d57-89bbc15705b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632463121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.632463121
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.157941845
Short name T455
Test name
Test status
Simulation time 3297715209 ps
CPU time 27.51 seconds
Started Jun 13 02:41:07 PM PDT 24
Finished Jun 13 02:41:39 PM PDT 24
Peak memory 219716 kb
Host smart-195dd9de-2c7f-4af0-b90f-c71725b50c95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157941845 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.157941845
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.899235139
Short name T406
Test name
Test status
Simulation time 8504334132 ps
CPU time 24.62 seconds
Started Jun 13 02:41:10 PM PDT 24
Finished Jun 13 02:41:38 PM PDT 24
Peak memory 212620 kb
Host smart-90f5e39d-8e81-47a9-aa45-92d8ef588169
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899235139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.899235139
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.886744982
Short name T102
Test name
Test status
Simulation time 6604199434 ps
CPU time 57.76 seconds
Started Jun 13 02:41:12 PM PDT 24
Finished Jun 13 02:42:13 PM PDT 24
Peak memory 215292 kb
Host smart-106d60d5-0067-4b2b-8235-7a16605f4377
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886744982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.886744982
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2408324908
Short name T408
Test name
Test status
Simulation time 4276917440 ps
CPU time 33.47 seconds
Started Jun 13 02:41:08 PM PDT 24
Finished Jun 13 02:41:45 PM PDT 24
Peak memory 212688 kb
Host smart-ca7d03a0-0d35-437a-b717-2950be960070
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408324908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2408324908
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.638076756
Short name T424
Test name
Test status
Simulation time 14321400942 ps
CPU time 30.82 seconds
Started Jun 13 02:41:09 PM PDT 24
Finished Jun 13 02:41:44 PM PDT 24
Peak memory 219700 kb
Host smart-61fcb73c-2fa7-47dc-8593-c2ae55140bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638076756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.638076756
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2751228877
Short name T128
Test name
Test status
Simulation time 12944716804 ps
CPU time 169.39 seconds
Started Jun 13 02:41:08 PM PDT 24
Finished Jun 13 02:44:02 PM PDT 24
Peak memory 215008 kb
Host smart-a1429f7d-9f3a-4b19-b11a-5284ef9f1ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751228877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2751228877
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1408683418
Short name T268
Test name
Test status
Simulation time 3882905426 ps
CPU time 31.93 seconds
Started Jun 13 01:11:38 PM PDT 24
Finished Jun 13 01:12:11 PM PDT 24
Peak memory 217096 kb
Host smart-ad67c931-c774-439a-969a-aa2e4b32de92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408683418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1408683418
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4102962205
Short name T186
Test name
Test status
Simulation time 86720979094 ps
CPU time 456.41 seconds
Started Jun 13 01:11:39 PM PDT 24
Finished Jun 13 01:19:17 PM PDT 24
Peak memory 238108 kb
Host smart-7bee83bd-60de-48e5-844c-3108dd643991
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102962205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4102962205
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1660817067
Short name T172
Test name
Test status
Simulation time 6676802375 ps
CPU time 60.71 seconds
Started Jun 13 01:11:40 PM PDT 24
Finished Jun 13 01:12:42 PM PDT 24
Peak memory 219300 kb
Host smart-f63483ea-da57-4b5a-81a5-d8d4c8e7119d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660817067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1660817067
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3386189160
Short name T182
Test name
Test status
Simulation time 15356319001 ps
CPU time 32.75 seconds
Started Jun 13 01:11:30 PM PDT 24
Finished Jun 13 01:12:05 PM PDT 24
Peak memory 211624 kb
Host smart-c112a21d-ca5b-4c30-89ae-8070243a1792
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3386189160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3386189160
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1273255551
Short name T30
Test name
Test status
Simulation time 855585067 ps
CPU time 116.36 seconds
Started Jun 13 01:11:36 PM PDT 24
Finished Jun 13 01:13:33 PM PDT 24
Peak memory 235928 kb
Host smart-0da79302-abb2-4d0e-8c47-26d689e88f8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273255551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1273255551
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3350948820
Short name T323
Test name
Test status
Simulation time 3056813531 ps
CPU time 43.34 seconds
Started Jun 13 01:11:28 PM PDT 24
Finished Jun 13 01:12:13 PM PDT 24
Peak memory 216732 kb
Host smart-f8905e4b-f3ea-4059-b742-21c8d8508ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350948820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3350948820
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.302434528
Short name T107
Test name
Test status
Simulation time 9492133353 ps
CPU time 30.58 seconds
Started Jun 13 01:11:39 PM PDT 24
Finished Jun 13 01:12:10 PM PDT 24
Peak memory 217368 kb
Host smart-4842ab4b-2930-4563-84e4-094cdf917439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302434528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.302434528
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2159160459
Short name T189
Test name
Test status
Simulation time 46711247993 ps
CPU time 575.42 seconds
Started Jun 13 01:11:38 PM PDT 24
Finished Jun 13 01:21:14 PM PDT 24
Peak memory 233628 kb
Host smart-cec0ac5c-23ab-498a-b8a3-bd4ea81795a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159160459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2159160459
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1040143469
Short name T225
Test name
Test status
Simulation time 5170461117 ps
CPU time 51.11 seconds
Started Jun 13 01:11:40 PM PDT 24
Finished Jun 13 01:12:32 PM PDT 24
Peak memory 219160 kb
Host smart-2ff631a8-61ef-4447-aa1d-63180cba7493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040143469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1040143469
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2853068724
Short name T222
Test name
Test status
Simulation time 4100195325 ps
CPU time 22.56 seconds
Started Jun 13 01:11:38 PM PDT 24
Finished Jun 13 01:12:01 PM PDT 24
Peak memory 217728 kb
Host smart-28d9684d-ff51-4ca9-9888-b756de81c616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853068724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2853068724
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.483275219
Short name T23
Test name
Test status
Simulation time 7480943458 ps
CPU time 44.34 seconds
Started Jun 13 01:11:40 PM PDT 24
Finished Jun 13 01:12:25 PM PDT 24
Peak memory 216672 kb
Host smart-b1079440-ea59-43fd-91cf-21cc76fc82cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483275219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.483275219
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4018309424
Short name T336
Test name
Test status
Simulation time 20448278313 ps
CPU time 146.94 seconds
Started Jun 13 01:11:38 PM PDT 24
Finished Jun 13 01:14:05 PM PDT 24
Peak memory 222348 kb
Host smart-14a50811-4519-4997-bbae-578971c4639c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018309424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4018309424
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.864061664
Short name T233
Test name
Test status
Simulation time 2694834556 ps
CPU time 23.65 seconds
Started Jun 13 01:11:57 PM PDT 24
Finished Jun 13 01:12:21 PM PDT 24
Peak memory 217068 kb
Host smart-22f2601d-c16a-4e80-90cd-838819df4b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864061664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.864061664
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1823743067
Short name T173
Test name
Test status
Simulation time 44357686919 ps
CPU time 556.84 seconds
Started Jun 13 01:11:51 PM PDT 24
Finished Jun 13 01:21:08 PM PDT 24
Peak memory 239636 kb
Host smart-0fc659a7-d45e-4f8d-abee-aa59d854b9a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823743067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1823743067
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2305085886
Short name T350
Test name
Test status
Simulation time 24512115167 ps
CPU time 49.04 seconds
Started Jun 13 01:11:53 PM PDT 24
Finished Jun 13 01:12:43 PM PDT 24
Peak memory 219268 kb
Host smart-2a03b3b5-df1c-4d88-8fa1-b1d6a1845b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305085886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2305085886
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1735124887
Short name T195
Test name
Test status
Simulation time 3939283058 ps
CPU time 21.7 seconds
Started Jun 13 01:11:45 PM PDT 24
Finished Jun 13 01:12:08 PM PDT 24
Peak memory 219376 kb
Host smart-ffd76063-b08d-4852-8877-40bdeafeb7a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1735124887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1735124887
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2226286310
Short name T106
Test name
Test status
Simulation time 10544125603 ps
CPU time 36.62 seconds
Started Jun 13 01:11:49 PM PDT 24
Finished Jun 13 01:12:26 PM PDT 24
Peak memory 216492 kb
Host smart-533db56f-8aba-418a-b2cf-93f674cac94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226286310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2226286310
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1045792222
Short name T61
Test name
Test status
Simulation time 6894292156 ps
CPU time 99.58 seconds
Started Jun 13 01:11:51 PM PDT 24
Finished Jun 13 01:13:31 PM PDT 24
Peak memory 221052 kb
Host smart-c3cd5d01-06b7-4d00-8720-db6709415d39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045792222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1045792222
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.357880939
Short name T18
Test name
Test status
Simulation time 91560455490 ps
CPU time 1003.82 seconds
Started Jun 13 01:11:56 PM PDT 24
Finished Jun 13 01:28:40 PM PDT 24
Peak memory 235620 kb
Host smart-2e86d8fb-a820-4da1-a3e4-ccdc0708fd1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357880939 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.357880939
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2205273414
Short name T213
Test name
Test status
Simulation time 8639798561 ps
CPU time 19.88 seconds
Started Jun 13 01:11:52 PM PDT 24
Finished Jun 13 01:12:13 PM PDT 24
Peak memory 217472 kb
Host smart-3b98af47-e42d-4ce2-9091-4490d22f8b9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205273414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2205273414
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3824730155
Short name T3
Test name
Test status
Simulation time 242713123622 ps
CPU time 586.13 seconds
Started Jun 13 01:11:53 PM PDT 24
Finished Jun 13 01:21:40 PM PDT 24
Peak memory 237912 kb
Host smart-dc80a071-e69a-40e9-858a-9f204c3f02fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824730155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3824730155
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.249976009
Short name T341
Test name
Test status
Simulation time 58413415073 ps
CPU time 69.3 seconds
Started Jun 13 01:11:53 PM PDT 24
Finished Jun 13 01:13:03 PM PDT 24
Peak memory 219276 kb
Host smart-5c102716-4055-4852-bf6f-92256b15b4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249976009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.249976009
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1936751755
Short name T36
Test name
Test status
Simulation time 931710966 ps
CPU time 16.65 seconds
Started Jun 13 01:11:53 PM PDT 24
Finished Jun 13 01:12:11 PM PDT 24
Peak memory 219132 kb
Host smart-1b0b8652-a93d-4861-aac5-3853e882e0da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1936751755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1936751755
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2860036201
Short name T279
Test name
Test status
Simulation time 76323935649 ps
CPU time 65.19 seconds
Started Jun 13 01:11:54 PM PDT 24
Finished Jun 13 01:13:00 PM PDT 24
Peak memory 215976 kb
Host smart-8e569911-3738-4e4e-87b1-6bd3949b1a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860036201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2860036201
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.982732592
Short name T295
Test name
Test status
Simulation time 2683360069 ps
CPU time 22.03 seconds
Started Jun 13 01:11:55 PM PDT 24
Finished Jun 13 01:12:18 PM PDT 24
Peak memory 219040 kb
Host smart-248fb0d2-c046-4994-9041-67bee5bc0f17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982732592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.982732592
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1557354755
Short name T216
Test name
Test status
Simulation time 36402515820 ps
CPU time 27.77 seconds
Started Jun 13 01:11:51 PM PDT 24
Finished Jun 13 01:12:20 PM PDT 24
Peak memory 217320 kb
Host smart-f173a2ca-aafe-4c2b-beec-be07bc74d4ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557354755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1557354755
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4144030817
Short name T4
Test name
Test status
Simulation time 215012850396 ps
CPU time 595.29 seconds
Started Jun 13 01:11:53 PM PDT 24
Finished Jun 13 01:21:49 PM PDT 24
Peak memory 235408 kb
Host smart-73046001-c74d-4406-bb84-2d2a6e2ea06f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144030817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.4144030817
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1173418265
Short name T228
Test name
Test status
Simulation time 8461423185 ps
CPU time 69.08 seconds
Started Jun 13 01:11:51 PM PDT 24
Finished Jun 13 01:13:01 PM PDT 24
Peak memory 219316 kb
Host smart-e5674d9a-497c-4c39-b563-fc188c6c2ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173418265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1173418265
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2437874026
Short name T297
Test name
Test status
Simulation time 4117477727 ps
CPU time 22.55 seconds
Started Jun 13 01:11:54 PM PDT 24
Finished Jun 13 01:12:17 PM PDT 24
Peak memory 211468 kb
Host smart-8c02f7ea-74e7-400e-b5db-2f8d72b253ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2437874026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2437874026
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1033492227
Short name T197
Test name
Test status
Simulation time 31453156733 ps
CPU time 63.06 seconds
Started Jun 13 01:11:52 PM PDT 24
Finished Jun 13 01:12:56 PM PDT 24
Peak memory 216604 kb
Host smart-1caa31b3-1710-4b7f-9da0-9436f248f7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033492227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1033492227
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2764093922
Short name T54
Test name
Test status
Simulation time 21200445383 ps
CPU time 94.44 seconds
Started Jun 13 01:11:53 PM PDT 24
Finished Jun 13 01:13:28 PM PDT 24
Peak memory 219348 kb
Host smart-4d2b6f94-1460-4847-9607-30393a50608c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764093922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2764093922
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1113469192
Short name T168
Test name
Test status
Simulation time 4664606042 ps
CPU time 16.76 seconds
Started Jun 13 01:11:57 PM PDT 24
Finished Jun 13 01:12:14 PM PDT 24
Peak memory 217468 kb
Host smart-7de2b311-1bf9-4eae-8579-d4cbe4f87da2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113469192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1113469192
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3334495107
Short name T199
Test name
Test status
Simulation time 163447826106 ps
CPU time 251.46 seconds
Started Jun 13 01:11:55 PM PDT 24
Finished Jun 13 01:16:08 PM PDT 24
Peak memory 234944 kb
Host smart-2faef4d0-8ead-40ff-8bff-acbb2dc19664
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334495107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3334495107
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3145835976
Short name T305
Test name
Test status
Simulation time 5512556925 ps
CPU time 24.46 seconds
Started Jun 13 01:11:53 PM PDT 24
Finished Jun 13 01:12:19 PM PDT 24
Peak memory 218712 kb
Host smart-a0937e6f-fea0-4ffe-86b7-dbcbe795ff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145835976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3145835976
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4110532728
Short name T187
Test name
Test status
Simulation time 1631627055 ps
CPU time 18.63 seconds
Started Jun 13 01:11:53 PM PDT 24
Finished Jun 13 01:12:12 PM PDT 24
Peak memory 219284 kb
Host smart-1eb90e7d-5406-43cf-a932-03c4fdb1ce1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4110532728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4110532728
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1202889842
Short name T105
Test name
Test status
Simulation time 15326331619 ps
CPU time 35.74 seconds
Started Jun 13 01:11:53 PM PDT 24
Finished Jun 13 01:12:30 PM PDT 24
Peak memory 217052 kb
Host smart-78676341-1148-458f-9752-47efb5190133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202889842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1202889842
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3191014560
Short name T109
Test name
Test status
Simulation time 15816607165 ps
CPU time 84.76 seconds
Started Jun 13 01:11:52 PM PDT 24
Finished Jun 13 01:13:18 PM PDT 24
Peak memory 219328 kb
Host smart-b21ad264-d169-4483-928c-7ae87f8e5af2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191014560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3191014560
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1120847531
Short name T204
Test name
Test status
Simulation time 169177473 ps
CPU time 8.59 seconds
Started Jun 13 01:12:02 PM PDT 24
Finished Jun 13 01:12:12 PM PDT 24
Peak memory 216944 kb
Host smart-48f74b60-371f-4abe-aa8d-3398a31c2841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120847531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1120847531
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.537198419
Short name T301
Test name
Test status
Simulation time 48854675096 ps
CPU time 246.58 seconds
Started Jun 13 01:11:56 PM PDT 24
Finished Jun 13 01:16:03 PM PDT 24
Peak memory 239756 kb
Host smart-707ea922-86a7-481e-90f6-b79ebc7ec426
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537198419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.537198419
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2895935231
Short name T325
Test name
Test status
Simulation time 31392727718 ps
CPU time 61.69 seconds
Started Jun 13 01:11:53 PM PDT 24
Finished Jun 13 01:12:55 PM PDT 24
Peak memory 219248 kb
Host smart-8c20be70-292b-4435-9eee-8125f4f42bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895935231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2895935231
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.925919330
Short name T278
Test name
Test status
Simulation time 11197203940 ps
CPU time 18.26 seconds
Started Jun 13 01:11:55 PM PDT 24
Finished Jun 13 01:12:14 PM PDT 24
Peak memory 217636 kb
Host smart-00e3f675-3447-474b-a678-088516b2bb1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=925919330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.925919330
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.823931539
Short name T235
Test name
Test status
Simulation time 4010033775 ps
CPU time 47.54 seconds
Started Jun 13 01:11:57 PM PDT 24
Finished Jun 13 01:12:45 PM PDT 24
Peak memory 215688 kb
Host smart-e61c991b-61b2-4f16-b49c-503b5d42488b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823931539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.823931539
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.64241019
Short name T303
Test name
Test status
Simulation time 4343115114 ps
CPU time 63.29 seconds
Started Jun 13 01:11:53 PM PDT 24
Finished Jun 13 01:12:58 PM PDT 24
Peak memory 220408 kb
Host smart-0bbb7e44-b062-45c7-a859-d50be26bb71a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64241019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 14.rom_ctrl_stress_all.64241019
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1211166762
Short name T27
Test name
Test status
Simulation time 1031146910 ps
CPU time 8.34 seconds
Started Jun 13 01:12:07 PM PDT 24
Finished Jun 13 01:12:16 PM PDT 24
Peak memory 216952 kb
Host smart-e9bcff7b-75ba-4d38-a6f7-fa60ce66f0ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211166762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1211166762
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2872812811
Short name T220
Test name
Test status
Simulation time 36331373512 ps
CPU time 432.47 seconds
Started Jun 13 01:12:03 PM PDT 24
Finished Jun 13 01:19:17 PM PDT 24
Peak memory 239940 kb
Host smart-c63deb94-dd68-49ab-a1f0-465ae67e15c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872812811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2872812811
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.145635790
Short name T348
Test name
Test status
Simulation time 2745726254 ps
CPU time 23.82 seconds
Started Jun 13 01:12:07 PM PDT 24
Finished Jun 13 01:12:32 PM PDT 24
Peak memory 215512 kb
Host smart-e131785a-f482-4a6e-8f01-b3de43c6cccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145635790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.145635790
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4125720759
Short name T358
Test name
Test status
Simulation time 17066004729 ps
CPU time 24.13 seconds
Started Jun 13 01:12:03 PM PDT 24
Finished Jun 13 01:12:28 PM PDT 24
Peak memory 219340 kb
Host smart-a9157019-1589-4dcc-ab70-aafa4f935458
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125720759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4125720759
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3382910318
Short name T287
Test name
Test status
Simulation time 23862479227 ps
CPU time 56.22 seconds
Started Jun 13 01:12:01 PM PDT 24
Finished Jun 13 01:12:58 PM PDT 24
Peak memory 215760 kb
Host smart-4fabe103-fa81-4f7f-8094-e14d24c35d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382910318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3382910318
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2999940653
Short name T89
Test name
Test status
Simulation time 40464522190 ps
CPU time 190.05 seconds
Started Jun 13 01:12:06 PM PDT 24
Finished Jun 13 01:15:17 PM PDT 24
Peak memory 228044 kb
Host smart-24f3f6eb-d9e5-4894-b629-1366522d4965
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999940653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2999940653
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.768725752
Short name T251
Test name
Test status
Simulation time 7208120021 ps
CPU time 29.17 seconds
Started Jun 13 01:12:06 PM PDT 24
Finished Jun 13 01:12:36 PM PDT 24
Peak memory 217464 kb
Host smart-4e58d7d1-4508-4ca3-91d2-82ba3106e58d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768725752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.768725752
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3832876066
Short name T111
Test name
Test status
Simulation time 2686023975 ps
CPU time 193.97 seconds
Started Jun 13 01:12:05 PM PDT 24
Finished Jun 13 01:15:20 PM PDT 24
Peak memory 240460 kb
Host smart-6e150c5a-a119-41af-b392-e8253eab2a3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832876066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3832876066
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.427244697
Short name T357
Test name
Test status
Simulation time 55728389173 ps
CPU time 27.92 seconds
Started Jun 13 01:12:02 PM PDT 24
Finished Jun 13 01:12:31 PM PDT 24
Peak memory 217628 kb
Host smart-c7f8901b-d043-4da4-8270-acdb06403524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=427244697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.427244697
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2935670730
Short name T212
Test name
Test status
Simulation time 7846467315 ps
CPU time 47.09 seconds
Started Jun 13 01:12:02 PM PDT 24
Finished Jun 13 01:12:51 PM PDT 24
Peak memory 217864 kb
Host smart-65531c30-d81c-41ac-b056-2c8cb1aae2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935670730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2935670730
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3492618366
Short name T190
Test name
Test status
Simulation time 1420994237 ps
CPU time 20.82 seconds
Started Jun 13 01:12:05 PM PDT 24
Finished Jun 13 01:12:27 PM PDT 24
Peak memory 218564 kb
Host smart-3cd3720c-3af9-4701-aa00-fa4015203771
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492618366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3492618366
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.668044441
Short name T252
Test name
Test status
Simulation time 688377003 ps
CPU time 8.41 seconds
Started Jun 13 01:12:10 PM PDT 24
Finished Jun 13 01:12:20 PM PDT 24
Peak memory 217076 kb
Host smart-5f8444d6-ace8-4304-ba9a-6a5c436a2455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668044441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.668044441
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1088486703
Short name T346
Test name
Test status
Simulation time 16388973010 ps
CPU time 296.79 seconds
Started Jun 13 01:12:08 PM PDT 24
Finished Jun 13 01:17:06 PM PDT 24
Peak memory 234052 kb
Host smart-64259acf-03e1-4ad4-84b3-f29caf3e7498
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088486703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1088486703
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1334663518
Short name T169
Test name
Test status
Simulation time 10164382578 ps
CPU time 25.08 seconds
Started Jun 13 01:12:01 PM PDT 24
Finished Jun 13 01:12:27 PM PDT 24
Peak memory 219348 kb
Host smart-ba87f1bd-2297-4cbd-8894-faa8c00bef86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334663518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1334663518
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1486785507
Short name T335
Test name
Test status
Simulation time 1442328530 ps
CPU time 20.2 seconds
Started Jun 13 01:12:02 PM PDT 24
Finished Jun 13 01:12:24 PM PDT 24
Peak memory 216452 kb
Host smart-044fadbd-37ca-4ca1-874c-a5570446cb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486785507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1486785507
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1347761371
Short name T230
Test name
Test status
Simulation time 23887395566 ps
CPU time 69.07 seconds
Started Jun 13 01:12:01 PM PDT 24
Finished Jun 13 01:13:11 PM PDT 24
Peak memory 219296 kb
Host smart-968f065d-783c-4d70-9fcb-10f2778ebb44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347761371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1347761371
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1955326577
Short name T324
Test name
Test status
Simulation time 3593844863 ps
CPU time 14.74 seconds
Started Jun 13 01:12:10 PM PDT 24
Finished Jun 13 01:12:26 PM PDT 24
Peak memory 217136 kb
Host smart-18459081-e7e4-468f-a240-af00239c8730
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955326577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1955326577
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4187015679
Short name T266
Test name
Test status
Simulation time 157124932070 ps
CPU time 688.78 seconds
Started Jun 13 01:12:13 PM PDT 24
Finished Jun 13 01:23:43 PM PDT 24
Peak memory 242840 kb
Host smart-e79c8899-2cba-4d08-b63a-e0b7d698fb94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187015679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4187015679
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3007636484
Short name T226
Test name
Test status
Simulation time 2741934324 ps
CPU time 27.75 seconds
Started Jun 13 01:12:08 PM PDT 24
Finished Jun 13 01:12:37 PM PDT 24
Peak memory 218364 kb
Host smart-321fa6bc-0761-4403-acae-97655ee969e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007636484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3007636484
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3789401169
Short name T258
Test name
Test status
Simulation time 179203287 ps
CPU time 10.23 seconds
Started Jun 13 01:12:11 PM PDT 24
Finished Jun 13 01:12:22 PM PDT 24
Peak memory 219248 kb
Host smart-caca730e-c208-4b9d-8f9d-facbdfacd573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3789401169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3789401169
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4107650092
Short name T275
Test name
Test status
Simulation time 25632485490 ps
CPU time 79.17 seconds
Started Jun 13 01:12:12 PM PDT 24
Finished Jun 13 01:13:32 PM PDT 24
Peak memory 216664 kb
Host smart-ec1e5405-785e-4d83-885e-853d3e36332f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107650092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4107650092
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.778992470
Short name T167
Test name
Test status
Simulation time 2520792029 ps
CPU time 50.96 seconds
Started Jun 13 01:12:12 PM PDT 24
Finished Jun 13 01:13:04 PM PDT 24
Peak memory 219324 kb
Host smart-1784be57-82b6-41b4-9785-29024b32af4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778992470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.778992470
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3445196502
Short name T353
Test name
Test status
Simulation time 174321467 ps
CPU time 8.48 seconds
Started Jun 13 01:12:10 PM PDT 24
Finished Jun 13 01:12:19 PM PDT 24
Peak memory 216784 kb
Host smart-bbf3b253-cf64-4ad1-a832-46be95b46973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445196502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3445196502
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2336715031
Short name T153
Test name
Test status
Simulation time 43279700977 ps
CPU time 524.64 seconds
Started Jun 13 01:12:11 PM PDT 24
Finished Jun 13 01:20:57 PM PDT 24
Peak memory 234680 kb
Host smart-6b2e10eb-c8d1-4280-91f2-9fe70daeeb83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336715031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2336715031
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.186899
Short name T255
Test name
Test status
Simulation time 11978851217 ps
CPU time 56.42 seconds
Started Jun 13 01:12:11 PM PDT 24
Finished Jun 13 01:13:08 PM PDT 24
Peak memory 219252 kb
Host smart-b04e02a3-21fa-4be5-b1f0-a4cfa052c165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.186899
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3321009821
Short name T247
Test name
Test status
Simulation time 11613652608 ps
CPU time 26.8 seconds
Started Jun 13 01:12:10 PM PDT 24
Finished Jun 13 01:12:37 PM PDT 24
Peak memory 217728 kb
Host smart-e0e4b145-c991-42ad-b388-5a159e5546f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3321009821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3321009821
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3164614081
Short name T239
Test name
Test status
Simulation time 15158914297 ps
CPU time 51.58 seconds
Started Jun 13 01:12:11 PM PDT 24
Finished Jun 13 01:13:03 PM PDT 24
Peak memory 216112 kb
Host smart-f81eb798-f2fb-4833-8058-ddd3a6421d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164614081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3164614081
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2515099636
Short name T327
Test name
Test status
Simulation time 854448639 ps
CPU time 25.88 seconds
Started Jun 13 01:12:11 PM PDT 24
Finished Jun 13 01:12:38 PM PDT 24
Peak memory 219280 kb
Host smart-40740519-67e0-4f8b-a567-bafdd874e88d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515099636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2515099636
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1192921750
Short name T313
Test name
Test status
Simulation time 2634801048 ps
CPU time 24.81 seconds
Started Jun 13 01:11:39 PM PDT 24
Finished Jun 13 01:12:05 PM PDT 24
Peak memory 217092 kb
Host smart-ca27912e-7d92-4ce7-b180-c9dbecf28f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192921750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1192921750
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.531400836
Short name T352
Test name
Test status
Simulation time 18342551313 ps
CPU time 170.14 seconds
Started Jun 13 01:11:38 PM PDT 24
Finished Jun 13 01:14:30 PM PDT 24
Peak memory 224780 kb
Host smart-d0d96b86-6823-47d2-8b84-773fe786adc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531400836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.531400836
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.968376565
Short name T349
Test name
Test status
Simulation time 7299509271 ps
CPU time 65.53 seconds
Started Jun 13 01:11:39 PM PDT 24
Finished Jun 13 01:12:46 PM PDT 24
Peak memory 219300 kb
Host smart-8bdc18b2-bfcd-446c-913a-e0b0b573b116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968376565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.968376565
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3914164150
Short name T181
Test name
Test status
Simulation time 341276493 ps
CPU time 10.48 seconds
Started Jun 13 01:11:39 PM PDT 24
Finished Jun 13 01:11:51 PM PDT 24
Peak memory 219284 kb
Host smart-ac1713d0-c746-4cb3-ad8e-57587a96b0f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3914164150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3914164150
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1043730187
Short name T26
Test name
Test status
Simulation time 2536346980 ps
CPU time 129.54 seconds
Started Jun 13 01:11:39 PM PDT 24
Finished Jun 13 01:13:50 PM PDT 24
Peak memory 237648 kb
Host smart-4b0e6bd8-ad6b-461a-b5a1-b75e84d5e6be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043730187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1043730187
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1617214159
Short name T240
Test name
Test status
Simulation time 21462710173 ps
CPU time 47.14 seconds
Started Jun 13 01:11:40 PM PDT 24
Finished Jun 13 01:12:28 PM PDT 24
Peak memory 218148 kb
Host smart-2ed7bf13-2d15-4ec2-b7e0-d705d84bb679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617214159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1617214159
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4277936776
Short name T139
Test name
Test status
Simulation time 71085548214 ps
CPU time 96.87 seconds
Started Jun 13 01:11:39 PM PDT 24
Finished Jun 13 01:13:18 PM PDT 24
Peak memory 219320 kb
Host smart-1eefe42f-2d69-4212-85e9-52b0c6f423ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277936776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4277936776
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1489571084
Short name T292
Test name
Test status
Simulation time 5631831167 ps
CPU time 19.13 seconds
Started Jun 13 01:12:19 PM PDT 24
Finished Jun 13 01:12:39 PM PDT 24
Peak memory 217360 kb
Host smart-424106d3-41ec-4d08-a9b7-b7c4ff32f4f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489571084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1489571084
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.77453649
Short name T242
Test name
Test status
Simulation time 4496801740 ps
CPU time 297.05 seconds
Started Jun 13 01:12:13 PM PDT 24
Finished Jun 13 01:17:10 PM PDT 24
Peak memory 234636 kb
Host smart-2798e471-e17b-43fb-b5ad-ee464e2304ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77453649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_co
rrupt_sig_fatal_chk.77453649
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2385532613
Short name T180
Test name
Test status
Simulation time 25355322281 ps
CPU time 55.96 seconds
Started Jun 13 01:12:10 PM PDT 24
Finished Jun 13 01:13:06 PM PDT 24
Peak memory 219304 kb
Host smart-cc3fc133-c6c4-4256-b2d3-e8ac8818b5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385532613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2385532613
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1993655532
Short name T141
Test name
Test status
Simulation time 17751610777 ps
CPU time 33.84 seconds
Started Jun 13 01:12:09 PM PDT 24
Finished Jun 13 01:12:44 PM PDT 24
Peak memory 217720 kb
Host smart-6045d70d-0f88-40cc-b891-3d6178420bbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1993655532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1993655532
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1621079827
Short name T333
Test name
Test status
Simulation time 41227602210 ps
CPU time 55.04 seconds
Started Jun 13 01:12:10 PM PDT 24
Finished Jun 13 01:13:06 PM PDT 24
Peak memory 216228 kb
Host smart-1f1f7902-9c21-4a9e-9526-63d756cc7b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621079827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1621079827
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.884793010
Short name T248
Test name
Test status
Simulation time 37142384679 ps
CPU time 158.52 seconds
Started Jun 13 01:12:12 PM PDT 24
Finished Jun 13 01:14:51 PM PDT 24
Peak memory 220888 kb
Host smart-b1fe1292-ba8c-4ef3-b6e3-4dab90c8949b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884793010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.884793010
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4182936775
Short name T154
Test name
Test status
Simulation time 3836243917 ps
CPU time 21.19 seconds
Started Jun 13 01:12:16 PM PDT 24
Finished Jun 13 01:12:38 PM PDT 24
Peak memory 217176 kb
Host smart-dfdbef9a-b1b3-41f9-bc12-45f128f560f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182936775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4182936775
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1707767413
Short name T14
Test name
Test status
Simulation time 55108575409 ps
CPU time 523.97 seconds
Started Jun 13 01:12:17 PM PDT 24
Finished Jun 13 01:21:01 PM PDT 24
Peak memory 242364 kb
Host smart-66d6f77a-35f2-4e10-a8ab-f0022dc4d5ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707767413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1707767413
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2958631940
Short name T37
Test name
Test status
Simulation time 8535361275 ps
CPU time 46.55 seconds
Started Jun 13 01:12:17 PM PDT 24
Finished Jun 13 01:13:04 PM PDT 24
Peak memory 219280 kb
Host smart-3238a79d-a69a-4051-958f-3b6415c537cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958631940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2958631940
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.857900913
Short name T221
Test name
Test status
Simulation time 1038599573 ps
CPU time 14.11 seconds
Started Jun 13 01:12:15 PM PDT 24
Finished Jun 13 01:12:29 PM PDT 24
Peak memory 219504 kb
Host smart-ad1ee8c7-3ff5-4cf8-a404-429a42bd8a15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=857900913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.857900913
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.690898783
Short name T138
Test name
Test status
Simulation time 18203809149 ps
CPU time 68.97 seconds
Started Jun 13 01:12:19 PM PDT 24
Finished Jun 13 01:13:29 PM PDT 24
Peak memory 218724 kb
Host smart-36d291fc-babe-4a03-8e26-9aa1607cf50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690898783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.690898783
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.353107671
Short name T217
Test name
Test status
Simulation time 104713267933 ps
CPU time 247.62 seconds
Started Jun 13 01:12:15 PM PDT 24
Finished Jun 13 01:16:23 PM PDT 24
Peak memory 219468 kb
Host smart-81f032c2-f36c-4915-b7c0-412ebf119e6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353107671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.353107671
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3112430617
Short name T166
Test name
Test status
Simulation time 49183769474 ps
CPU time 23.04 seconds
Started Jun 13 01:12:25 PM PDT 24
Finished Jun 13 01:12:48 PM PDT 24
Peak memory 217456 kb
Host smart-205ea502-5ca1-42c1-bf0a-f6e995c7f866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112430617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3112430617
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3807929216
Short name T271
Test name
Test status
Simulation time 23505754176 ps
CPU time 380.74 seconds
Started Jun 13 01:12:16 PM PDT 24
Finished Jun 13 01:18:37 PM PDT 24
Peak memory 225508 kb
Host smart-2e9cc738-b902-45a4-8b96-7b012220ee4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807929216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3807929216
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.954119432
Short name T1
Test name
Test status
Simulation time 1374274881 ps
CPU time 18.81 seconds
Started Jun 13 01:12:25 PM PDT 24
Finished Jun 13 01:12:44 PM PDT 24
Peak memory 219220 kb
Host smart-0548307e-774a-4627-bb2d-df551e2b4061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954119432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.954119432
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3444806459
Short name T254
Test name
Test status
Simulation time 4032082169 ps
CPU time 33.44 seconds
Started Jun 13 01:12:18 PM PDT 24
Finished Jun 13 01:12:52 PM PDT 24
Peak memory 219348 kb
Host smart-dde68314-e15c-4f98-8ebc-cc8e5c33fbe3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3444806459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3444806459
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2231475332
Short name T294
Test name
Test status
Simulation time 22483028403 ps
CPU time 59.29 seconds
Started Jun 13 01:12:17 PM PDT 24
Finished Jun 13 01:13:17 PM PDT 24
Peak memory 215576 kb
Host smart-c4364093-7f8a-4910-b505-9f853ae1a091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231475332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2231475332
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2595549459
Short name T337
Test name
Test status
Simulation time 1762093551 ps
CPU time 23.66 seconds
Started Jun 13 01:12:17 PM PDT 24
Finished Jun 13 01:12:41 PM PDT 24
Peak memory 214448 kb
Host smart-403d2692-e20b-48f5-87c6-d128c8c9714c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595549459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2595549459
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1929306747
Short name T178
Test name
Test status
Simulation time 14420266450 ps
CPU time 29.71 seconds
Started Jun 13 01:12:22 PM PDT 24
Finished Jun 13 01:12:52 PM PDT 24
Peak memory 217368 kb
Host smart-1969de26-b0dd-49b4-bfa8-6fdc7e10b0ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929306747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1929306747
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3416772614
Short name T42
Test name
Test status
Simulation time 86323493162 ps
CPU time 756.3 seconds
Started Jun 13 01:12:25 PM PDT 24
Finished Jun 13 01:25:02 PM PDT 24
Peak memory 216676 kb
Host smart-1d2ed06f-3d65-4ed1-9fac-9506affbc427
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416772614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3416772614
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3111056338
Short name T288
Test name
Test status
Simulation time 15416949406 ps
CPU time 64.27 seconds
Started Jun 13 01:12:26 PM PDT 24
Finished Jun 13 01:13:30 PM PDT 24
Peak memory 219220 kb
Host smart-aad6faf9-50e1-43d7-897f-2de672f2de39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111056338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3111056338
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2303094962
Short name T308
Test name
Test status
Simulation time 10040063934 ps
CPU time 23.52 seconds
Started Jun 13 01:12:25 PM PDT 24
Finished Jun 13 01:12:49 PM PDT 24
Peak memory 219348 kb
Host smart-a118d8b8-f05e-4ef4-abef-5d8a2a1b138d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2303094962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2303094962
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1242230139
Short name T146
Test name
Test status
Simulation time 60282108235 ps
CPU time 52.21 seconds
Started Jun 13 01:12:24 PM PDT 24
Finished Jun 13 01:13:17 PM PDT 24
Peak memory 216376 kb
Host smart-42251171-820a-4e9e-80d2-f6bbfa2b6752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242230139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1242230139
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3693830443
Short name T88
Test name
Test status
Simulation time 1989915914 ps
CPU time 18.65 seconds
Started Jun 13 01:12:23 PM PDT 24
Finished Jun 13 01:12:42 PM PDT 24
Peak memory 214444 kb
Host smart-abefc65c-97e0-4a97-96ff-e1498dbe7efe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693830443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3693830443
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1751378910
Short name T302
Test name
Test status
Simulation time 12590470370 ps
CPU time 30.3 seconds
Started Jun 13 01:12:42 PM PDT 24
Finished Jun 13 01:13:14 PM PDT 24
Peak memory 217260 kb
Host smart-83c03b16-9a1c-4eb3-9a06-a5cd5dd3aa1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751378910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1751378910
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1446337912
Short name T194
Test name
Test status
Simulation time 16852618275 ps
CPU time 216.34 seconds
Started Jun 13 01:12:34 PM PDT 24
Finished Jun 13 01:16:10 PM PDT 24
Peak memory 224240 kb
Host smart-e8903817-5a6a-497d-9305-82ca030d000c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446337912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1446337912
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3348808204
Short name T184
Test name
Test status
Simulation time 5297180541 ps
CPU time 49.49 seconds
Started Jun 13 01:12:30 PM PDT 24
Finished Jun 13 01:13:19 PM PDT 24
Peak memory 219284 kb
Host smart-23e2a0e3-3816-4d49-b56b-85ca84b893a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348808204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3348808204
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3148781979
Short name T208
Test name
Test status
Simulation time 1324256668 ps
CPU time 18.75 seconds
Started Jun 13 01:12:31 PM PDT 24
Finished Jun 13 01:12:50 PM PDT 24
Peak memory 219172 kb
Host smart-9853c963-2c3c-4b52-a17d-6ebc34ffc4c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148781979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3148781979
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1558449419
Short name T206
Test name
Test status
Simulation time 7815554210 ps
CPU time 66.88 seconds
Started Jun 13 01:12:24 PM PDT 24
Finished Jun 13 01:13:31 PM PDT 24
Peak memory 216964 kb
Host smart-d62ef6fc-7ece-475e-97b9-4ed7f211b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558449419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1558449419
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3341492762
Short name T311
Test name
Test status
Simulation time 61684501031 ps
CPU time 144.38 seconds
Started Jun 13 01:12:26 PM PDT 24
Finished Jun 13 01:14:51 PM PDT 24
Peak memory 219504 kb
Host smart-ce98b86c-a4f4-4828-a6ae-c494d16f3e12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341492762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3341492762
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1857779926
Short name T160
Test name
Test status
Simulation time 3907211413 ps
CPU time 30.95 seconds
Started Jun 13 01:12:31 PM PDT 24
Finished Jun 13 01:13:03 PM PDT 24
Peak memory 217232 kb
Host smart-bd5ba6b7-37e7-44d3-b54c-2ee8ad914f49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857779926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1857779926
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1944783458
Short name T267
Test name
Test status
Simulation time 49319879311 ps
CPU time 554.23 seconds
Started Jun 13 01:12:43 PM PDT 24
Finished Jun 13 01:21:59 PM PDT 24
Peak memory 234660 kb
Host smart-c2680fca-f2a3-47f5-8dc5-c6b17e568f54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944783458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1944783458
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3652321393
Short name T273
Test name
Test status
Simulation time 346484454 ps
CPU time 19.61 seconds
Started Jun 13 01:12:32 PM PDT 24
Finished Jun 13 01:12:52 PM PDT 24
Peak memory 219208 kb
Host smart-e27b57aa-6c7e-4e24-bc4e-3879d671de96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652321393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3652321393
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3571187422
Short name T177
Test name
Test status
Simulation time 415027406 ps
CPU time 10.09 seconds
Started Jun 13 01:12:31 PM PDT 24
Finished Jun 13 01:12:42 PM PDT 24
Peak memory 219256 kb
Host smart-7141f255-9ac4-4505-ac27-0a6165324f1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3571187422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3571187422
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3267861883
Short name T229
Test name
Test status
Simulation time 8626371113 ps
CPU time 40.33 seconds
Started Jun 13 01:12:35 PM PDT 24
Finished Jun 13 01:13:15 PM PDT 24
Peak memory 216240 kb
Host smart-c8e2a31e-f690-4f64-b0b0-222368d2593f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267861883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3267861883
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1740911742
Short name T207
Test name
Test status
Simulation time 35885427628 ps
CPU time 150.56 seconds
Started Jun 13 01:12:31 PM PDT 24
Finished Jun 13 01:15:03 PM PDT 24
Peak memory 222244 kb
Host smart-df8c13e5-e779-4fe4-b629-e79b9cf4b5c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740911742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1740911742
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.93464162
Short name T156
Test name
Test status
Simulation time 4770742629 ps
CPU time 16.76 seconds
Started Jun 13 01:12:31 PM PDT 24
Finished Jun 13 01:12:49 PM PDT 24
Peak memory 217296 kb
Host smart-39ec220c-65b1-42a6-b32f-7ee3eb150ed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93464162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.93464162
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.151208690
Short name T39
Test name
Test status
Simulation time 308955454006 ps
CPU time 665.05 seconds
Started Jun 13 01:12:43 PM PDT 24
Finished Jun 13 01:23:49 PM PDT 24
Peak memory 234196 kb
Host smart-390d55b8-f318-4d20-b333-642e8bb5d60e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151208690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.151208690
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.277351469
Short name T330
Test name
Test status
Simulation time 38408199972 ps
CPU time 64.07 seconds
Started Jun 13 01:12:35 PM PDT 24
Finished Jun 13 01:13:40 PM PDT 24
Peak memory 219220 kb
Host smart-2dcaec72-a115-4935-ad43-7b1cfe268046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277351469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.277351469
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1699522564
Short name T284
Test name
Test status
Simulation time 19689452058 ps
CPU time 28.82 seconds
Started Jun 13 01:12:41 PM PDT 24
Finished Jun 13 01:13:11 PM PDT 24
Peak memory 219284 kb
Host smart-9cacf1df-2716-49fb-8124-cf82bbb45e68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699522564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1699522564
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.4049924924
Short name T76
Test name
Test status
Simulation time 12446332340 ps
CPU time 65.13 seconds
Started Jun 13 01:12:36 PM PDT 24
Finished Jun 13 01:13:42 PM PDT 24
Peak memory 216852 kb
Host smart-6a43f43a-efe2-43d3-9e98-48cadb5f2860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049924924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.4049924924
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2296118717
Short name T147
Test name
Test status
Simulation time 5648681541 ps
CPU time 57.78 seconds
Started Jun 13 01:12:33 PM PDT 24
Finished Jun 13 01:13:31 PM PDT 24
Peak memory 219308 kb
Host smart-4943a45e-f644-4969-82fa-79a0bdb742e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296118717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2296118717
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3495043995
Short name T47
Test name
Test status
Simulation time 5692843345 ps
CPU time 113.78 seconds
Started Jun 13 01:12:36 PM PDT 24
Finished Jun 13 01:14:30 PM PDT 24
Peak memory 222780 kb
Host smart-b1db6793-24a5-46b8-a969-3ae6b01eecd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495043995 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3495043995
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2853877286
Short name T60
Test name
Test status
Simulation time 4138375608 ps
CPU time 32.92 seconds
Started Jun 13 01:12:39 PM PDT 24
Finished Jun 13 01:13:13 PM PDT 24
Peak memory 217072 kb
Host smart-9c3db784-2a4c-432c-838f-e3a8a6532c23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853877286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2853877286
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1430341223
Short name T300
Test name
Test status
Simulation time 2219435842 ps
CPU time 145.5 seconds
Started Jun 13 01:12:37 PM PDT 24
Finished Jun 13 01:15:03 PM PDT 24
Peak memory 242624 kb
Host smart-239d9c31-ad30-4951-9963-c4aa039f347e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430341223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1430341223
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3016323686
Short name T34
Test name
Test status
Simulation time 5874193936 ps
CPU time 51.03 seconds
Started Jun 13 01:12:38 PM PDT 24
Finished Jun 13 01:13:30 PM PDT 24
Peak memory 219256 kb
Host smart-52a5c54b-6056-45a0-8dd9-94d101fbab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016323686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3016323686
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1373562530
Short name T354
Test name
Test status
Simulation time 606554997 ps
CPU time 10.64 seconds
Started Jun 13 01:12:38 PM PDT 24
Finished Jun 13 01:12:50 PM PDT 24
Peak memory 219312 kb
Host smart-b34e7dd8-26a1-4010-a297-17794f40f448
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373562530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1373562530
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3173019051
Short name T261
Test name
Test status
Simulation time 6140743045 ps
CPU time 37.87 seconds
Started Jun 13 01:12:43 PM PDT 24
Finished Jun 13 01:13:22 PM PDT 24
Peak memory 216448 kb
Host smart-04bea5d6-f821-4d4a-bb9c-d9d0c802537d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173019051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3173019051
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3504084430
Short name T64
Test name
Test status
Simulation time 6246017210 ps
CPU time 47.92 seconds
Started Jun 13 01:12:43 PM PDT 24
Finished Jun 13 01:13:32 PM PDT 24
Peak memory 216828 kb
Host smart-cf255734-1043-4390-a9d9-08224dd321a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504084430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3504084430
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2902972206
Short name T316
Test name
Test status
Simulation time 5591495964 ps
CPU time 26.01 seconds
Started Jun 13 01:12:40 PM PDT 24
Finished Jun 13 01:13:07 PM PDT 24
Peak memory 217380 kb
Host smart-aa8f4431-1805-49f8-9527-8b7b608b7af3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902972206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2902972206
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3870042991
Short name T338
Test name
Test status
Simulation time 539403359916 ps
CPU time 710.34 seconds
Started Jun 13 01:12:41 PM PDT 24
Finished Jun 13 01:24:33 PM PDT 24
Peak memory 239208 kb
Host smart-ad34ae1f-48c8-47d1-92cb-07bff336733f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870042991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3870042991
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3410866764
Short name T45
Test name
Test status
Simulation time 7895892839 ps
CPU time 33.29 seconds
Started Jun 13 01:12:40 PM PDT 24
Finished Jun 13 01:13:14 PM PDT 24
Peak memory 219264 kb
Host smart-634cdb57-394a-41d8-89d4-6e5bd9305f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410866764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3410866764
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4084108604
Short name T137
Test name
Test status
Simulation time 2144079700 ps
CPU time 17.85 seconds
Started Jun 13 01:12:44 PM PDT 24
Finished Jun 13 01:13:03 PM PDT 24
Peak memory 219292 kb
Host smart-6bf564a4-8d18-4bd3-9b99-3f96118fec5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084108604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4084108604
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3498607467
Short name T307
Test name
Test status
Simulation time 835013426 ps
CPU time 26.04 seconds
Started Jun 13 01:12:43 PM PDT 24
Finished Jun 13 01:13:10 PM PDT 24
Peak memory 216088 kb
Host smart-8b915e13-5480-4fcc-a29a-8ee2199ea41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498607467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3498607467
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3115191464
Short name T304
Test name
Test status
Simulation time 9413667483 ps
CPU time 99.16 seconds
Started Jun 13 01:12:41 PM PDT 24
Finished Jun 13 01:14:21 PM PDT 24
Peak memory 220396 kb
Host smart-3147e155-44d8-4ddd-9f52-4c4107f1f245
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115191464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3115191464
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2590545210
Short name T259
Test name
Test status
Simulation time 170901707 ps
CPU time 8.45 seconds
Started Jun 13 01:12:43 PM PDT 24
Finished Jun 13 01:12:53 PM PDT 24
Peak memory 217072 kb
Host smart-997285d9-866a-431d-a087-f580cf9ea253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590545210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2590545210
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2570819229
Short name T10
Test name
Test status
Simulation time 11238244028 ps
CPU time 202.41 seconds
Started Jun 13 01:12:38 PM PDT 24
Finished Jun 13 01:16:01 PM PDT 24
Peak memory 239040 kb
Host smart-144e9940-c5f2-47a0-bd0b-3ff32c6b7583
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570819229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2570819229
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2453850801
Short name T205
Test name
Test status
Simulation time 4226308828 ps
CPU time 45.99 seconds
Started Jun 13 01:12:39 PM PDT 24
Finished Jun 13 01:13:26 PM PDT 24
Peak memory 218892 kb
Host smart-c9e2ea11-ee35-4780-a26e-24dfa4aa4e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453850801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2453850801
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1749858853
Short name T144
Test name
Test status
Simulation time 2392626356 ps
CPU time 24.25 seconds
Started Jun 13 01:12:41 PM PDT 24
Finished Jun 13 01:13:06 PM PDT 24
Peak memory 211612 kb
Host smart-91de2bf4-bb39-4f51-913d-75a927a315b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1749858853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1749858853
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2166759123
Short name T351
Test name
Test status
Simulation time 33474506575 ps
CPU time 79.45 seconds
Started Jun 13 01:12:41 PM PDT 24
Finished Jun 13 01:14:02 PM PDT 24
Peak memory 216548 kb
Host smart-59959721-e526-4f1d-9af1-3e618e63419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166759123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2166759123
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3401541544
Short name T93
Test name
Test status
Simulation time 26288490008 ps
CPU time 38.95 seconds
Started Jun 13 01:12:39 PM PDT 24
Finished Jun 13 01:13:19 PM PDT 24
Peak memory 219328 kb
Host smart-b031b39d-6ae9-4839-8871-d66bb77a77c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401541544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3401541544
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2870384810
Short name T237
Test name
Test status
Simulation time 174455517 ps
CPU time 8.32 seconds
Started Jun 13 01:11:39 PM PDT 24
Finished Jun 13 01:11:49 PM PDT 24
Peak memory 218148 kb
Host smart-662277d2-635f-4fb1-947f-c4bab218faea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870384810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2870384810
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3653284224
Short name T41
Test name
Test status
Simulation time 168713902932 ps
CPU time 937.97 seconds
Started Jun 13 01:11:40 PM PDT 24
Finished Jun 13 01:27:19 PM PDT 24
Peak memory 233356 kb
Host smart-04764a9a-19b1-4fd2-91c6-8edecba51147
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653284224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3653284224
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4260291586
Short name T282
Test name
Test status
Simulation time 11953090033 ps
CPU time 55.78 seconds
Started Jun 13 01:11:38 PM PDT 24
Finished Jun 13 01:12:35 PM PDT 24
Peak memory 219328 kb
Host smart-441a0087-79e2-4d8c-a9fc-02797d7015cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260291586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4260291586
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4145215393
Short name T117
Test name
Test status
Simulation time 183634797 ps
CPU time 11.15 seconds
Started Jun 13 01:11:39 PM PDT 24
Finished Jun 13 01:11:51 PM PDT 24
Peak memory 219200 kb
Host smart-1eddda50-949c-4e43-a148-dc0b5ad7af62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145215393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4145215393
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1307780940
Short name T25
Test name
Test status
Simulation time 5722702900 ps
CPU time 140.86 seconds
Started Jun 13 01:11:37 PM PDT 24
Finished Jun 13 01:13:58 PM PDT 24
Peak memory 238152 kb
Host smart-e0c9383b-e28e-422b-b1e5-cf017ccb9dba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307780940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1307780940
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3987152550
Short name T334
Test name
Test status
Simulation time 1685271635 ps
CPU time 35.65 seconds
Started Jun 13 01:11:39 PM PDT 24
Finished Jun 13 01:12:15 PM PDT 24
Peak memory 216592 kb
Host smart-ad7f42b9-481a-420e-8bd6-fdc5a48466a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987152550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3987152550
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1612358398
Short name T202
Test name
Test status
Simulation time 8986675241 ps
CPU time 34.61 seconds
Started Jun 13 01:11:37 PM PDT 24
Finished Jun 13 01:12:12 PM PDT 24
Peak memory 219188 kb
Host smart-296e5bad-0f2c-4517-bc4c-1a84056311c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612358398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1612358398
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1306556736
Short name T276
Test name
Test status
Simulation time 17040259655 ps
CPU time 34.04 seconds
Started Jun 13 01:12:39 PM PDT 24
Finished Jun 13 01:13:14 PM PDT 24
Peak memory 217404 kb
Host smart-b07ca11f-e507-4aa1-843e-9b758f552e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306556736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1306556736
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2158110570
Short name T149
Test name
Test status
Simulation time 190715180864 ps
CPU time 533.45 seconds
Started Jun 13 01:12:38 PM PDT 24
Finished Jun 13 01:21:33 PM PDT 24
Peak memory 216720 kb
Host smart-333a1023-c4df-4f16-93ea-12e449038f88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158110570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2158110570
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3719414629
Short name T164
Test name
Test status
Simulation time 12812933071 ps
CPU time 56.95 seconds
Started Jun 13 01:12:40 PM PDT 24
Finished Jun 13 01:13:38 PM PDT 24
Peak memory 219296 kb
Host smart-a63ee6a9-39e4-4ddd-b18d-e825e5a4f958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719414629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3719414629
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3497320877
Short name T209
Test name
Test status
Simulation time 7868669975 ps
CPU time 32.89 seconds
Started Jun 13 01:12:41 PM PDT 24
Finished Jun 13 01:13:16 PM PDT 24
Peak memory 219348 kb
Host smart-95d14879-f105-49c9-8548-b2fe47982ab0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3497320877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3497320877
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.517877897
Short name T12
Test name
Test status
Simulation time 6474418751 ps
CPU time 79.13 seconds
Started Jun 13 01:12:39 PM PDT 24
Finished Jun 13 01:13:59 PM PDT 24
Peak memory 216720 kb
Host smart-071605cb-4779-4d51-98b9-c4d211056a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517877897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.517877897
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.83377233
Short name T57
Test name
Test status
Simulation time 227349519642 ps
CPU time 147.33 seconds
Started Jun 13 01:12:38 PM PDT 24
Finished Jun 13 01:15:07 PM PDT 24
Peak memory 221984 kb
Host smart-e80c32f2-835a-4371-abc1-d2906a40386c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83377233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 30.rom_ctrl_stress_all.83377233
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2588057061
Short name T69
Test name
Test status
Simulation time 2234524107 ps
CPU time 22.1 seconds
Started Jun 13 01:12:46 PM PDT 24
Finished Jun 13 01:13:09 PM PDT 24
Peak memory 217048 kb
Host smart-4dc3264e-a458-4470-86c0-fd924856cc2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588057061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2588057061
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2769260992
Short name T314
Test name
Test status
Simulation time 16558869812 ps
CPU time 191.72 seconds
Started Jun 13 01:12:46 PM PDT 24
Finished Jun 13 01:15:59 PM PDT 24
Peak memory 218920 kb
Host smart-cc41940c-04aa-42b3-b191-8c73cc47cb1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769260992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2769260992
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1858406002
Short name T108
Test name
Test status
Simulation time 7213966781 ps
CPU time 42.35 seconds
Started Jun 13 01:12:46 PM PDT 24
Finished Jun 13 01:13:30 PM PDT 24
Peak memory 219292 kb
Host smart-65ca3e2f-0783-4490-a477-f525eb8000d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858406002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1858406002
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3140702872
Short name T281
Test name
Test status
Simulation time 345271196 ps
CPU time 10.21 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:13:07 PM PDT 24
Peak memory 219332 kb
Host smart-8620b2ed-207c-41eb-b31a-664f63235eb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3140702872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3140702872
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3657530662
Short name T326
Test name
Test status
Simulation time 4956290984 ps
CPU time 37.01 seconds
Started Jun 13 01:12:47 PM PDT 24
Finished Jun 13 01:13:25 PM PDT 24
Peak memory 216004 kb
Host smart-8065b9bf-60f5-448b-ba8e-913eb318907d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657530662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3657530662
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3426881554
Short name T91
Test name
Test status
Simulation time 10740274217 ps
CPU time 32.01 seconds
Started Jun 13 01:12:47 PM PDT 24
Finished Jun 13 01:13:20 PM PDT 24
Peak memory 219328 kb
Host smart-918e1bfc-a2e2-4e0b-b720-0c3b57bad464
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426881554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3426881554
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3149317734
Short name T291
Test name
Test status
Simulation time 2059270391 ps
CPU time 8.48 seconds
Started Jun 13 01:12:45 PM PDT 24
Finished Jun 13 01:12:54 PM PDT 24
Peak memory 216944 kb
Host smart-506d15ac-8406-400b-8e0f-d6d384de5024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149317734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3149317734
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.435384800
Short name T318
Test name
Test status
Simulation time 54729202850 ps
CPU time 274.56 seconds
Started Jun 13 01:12:46 PM PDT 24
Finished Jun 13 01:17:22 PM PDT 24
Peak memory 238776 kb
Host smart-7d48fd0d-008e-48c6-9332-35f82e643747
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435384800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.435384800
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1622485876
Short name T306
Test name
Test status
Simulation time 47067434200 ps
CPU time 61.51 seconds
Started Jun 13 01:12:51 PM PDT 24
Finished Jun 13 01:13:53 PM PDT 24
Peak memory 219280 kb
Host smart-e0030076-c02e-4526-b024-de69c16d1586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622485876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1622485876
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4010691844
Short name T253
Test name
Test status
Simulation time 4111649864 ps
CPU time 33.5 seconds
Started Jun 13 01:12:47 PM PDT 24
Finished Jun 13 01:13:21 PM PDT 24
Peak memory 219356 kb
Host smart-3eb336fa-7f37-4249-8a4c-58ec4766ad52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010691844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.4010691844
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1197282380
Short name T92
Test name
Test status
Simulation time 1578979908 ps
CPU time 32.13 seconds
Started Jun 13 01:12:45 PM PDT 24
Finished Jun 13 01:13:18 PM PDT 24
Peak memory 216360 kb
Host smart-bb37febe-e4d9-4b53-9f2a-78d7e803be84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197282380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1197282380
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.546560813
Short name T75
Test name
Test status
Simulation time 193523586 ps
CPU time 17.85 seconds
Started Jun 13 01:12:52 PM PDT 24
Finished Jun 13 01:13:10 PM PDT 24
Peak memory 218636 kb
Host smart-21f0044e-5426-48b6-a35a-0c192f41de6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546560813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.546560813
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1283681314
Short name T148
Test name
Test status
Simulation time 4724041448 ps
CPU time 309.86 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:18:07 PM PDT 24
Peak memory 235676 kb
Host smart-e764e70c-659a-4e5e-9fa6-ae1adbc15866
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283681314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1283681314
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3748727520
Short name T224
Test name
Test status
Simulation time 15310227390 ps
CPU time 64.69 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:14:02 PM PDT 24
Peak memory 219304 kb
Host smart-40e62c60-344d-492f-9cde-6f4c5c3ba7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748727520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3748727520
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.624733186
Short name T296
Test name
Test status
Simulation time 4192939197 ps
CPU time 34.65 seconds
Started Jun 13 01:12:53 PM PDT 24
Finished Jun 13 01:13:28 PM PDT 24
Peak memory 211324 kb
Host smart-5c777c34-1dab-46dd-86b9-2371e379473a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=624733186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.624733186
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2684068568
Short name T241
Test name
Test status
Simulation time 20515496009 ps
CPU time 49.24 seconds
Started Jun 13 01:12:47 PM PDT 24
Finished Jun 13 01:13:37 PM PDT 24
Peak memory 216900 kb
Host smart-3d70fff2-d21a-4a0d-9d15-03bc75eb1f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684068568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2684068568
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2455800155
Short name T5
Test name
Test status
Simulation time 12236170930 ps
CPU time 37.93 seconds
Started Jun 13 01:12:46 PM PDT 24
Finished Jun 13 01:13:25 PM PDT 24
Peak memory 219212 kb
Host smart-97532404-17ba-46d4-93d4-9833836c5532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455800155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2455800155
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.794894707
Short name T151
Test name
Test status
Simulation time 14313906283 ps
CPU time 30.75 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:13:28 PM PDT 24
Peak memory 217428 kb
Host smart-0e79d264-751d-45af-87b3-910973349148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794894707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.794894707
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3198414412
Short name T322
Test name
Test status
Simulation time 404083817718 ps
CPU time 786.46 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:26:04 PM PDT 24
Peak memory 226520 kb
Host smart-d3ea8865-7edc-48cc-88a9-939643ce99d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198414412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3198414412
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2954828393
Short name T347
Test name
Test status
Simulation time 12661776975 ps
CPU time 38.1 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:13:35 PM PDT 24
Peak memory 219156 kb
Host smart-6f6ffb39-4a45-4aaa-b65e-70bdf3266c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954828393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2954828393
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3218875928
Short name T175
Test name
Test status
Simulation time 6877294208 ps
CPU time 18.03 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:13:15 PM PDT 24
Peak memory 217632 kb
Host smart-9296e054-172f-46a1-8851-5eabf688ef83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218875928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3218875928
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.4207988980
Short name T262
Test name
Test status
Simulation time 1042070018 ps
CPU time 22.67 seconds
Started Jun 13 01:12:56 PM PDT 24
Finished Jun 13 01:13:20 PM PDT 24
Peak memory 215900 kb
Host smart-65787893-78e3-4664-b531-4f4d21a6dcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207988980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.4207988980
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.186777487
Short name T90
Test name
Test status
Simulation time 42278574526 ps
CPU time 163.59 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:15:40 PM PDT 24
Peak memory 227516 kb
Host smart-fdbd776b-6085-4d2f-a998-1863b0a8639f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186777487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.186777487
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3123327384
Short name T28
Test name
Test status
Simulation time 6890333227 ps
CPU time 29.12 seconds
Started Jun 13 01:12:58 PM PDT 24
Finished Jun 13 01:13:28 PM PDT 24
Peak memory 217372 kb
Host smart-911c85bc-adf9-48e3-9ab7-996427161049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123327384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3123327384
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2604086408
Short name T290
Test name
Test status
Simulation time 59362573001 ps
CPU time 664.43 seconds
Started Jun 13 01:12:56 PM PDT 24
Finished Jun 13 01:24:02 PM PDT 24
Peak memory 234268 kb
Host smart-4348e5f1-1b60-4d5c-a46d-080decff553a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604086408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2604086408
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1365365057
Short name T176
Test name
Test status
Simulation time 11130613967 ps
CPU time 39.01 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:13:36 PM PDT 24
Peak memory 219300 kb
Host smart-646757c3-50d7-471e-9e84-ffefec474337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365365057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1365365057
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1148718016
Short name T140
Test name
Test status
Simulation time 183868942 ps
CPU time 10.19 seconds
Started Jun 13 01:13:02 PM PDT 24
Finished Jun 13 01:13:14 PM PDT 24
Peak memory 219224 kb
Host smart-ed970ec9-4c11-41c8-8f06-28562d545aec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1148718016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1148718016
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.303503337
Short name T298
Test name
Test status
Simulation time 58262979992 ps
CPU time 50.5 seconds
Started Jun 13 01:12:54 PM PDT 24
Finished Jun 13 01:13:45 PM PDT 24
Peak memory 216448 kb
Host smart-41d3ff8b-ddb6-476b-b8b3-292f36beefa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303503337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.303503337
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2415542928
Short name T320
Test name
Test status
Simulation time 4131619119 ps
CPU time 18.31 seconds
Started Jun 13 01:12:54 PM PDT 24
Finished Jun 13 01:13:13 PM PDT 24
Peak memory 219184 kb
Host smart-450fbc8f-b9c5-45bb-af05-5af70dcfc56d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415542928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2415542928
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1460854306
Short name T257
Test name
Test status
Simulation time 167713846 ps
CPU time 8.3 seconds
Started Jun 13 01:12:59 PM PDT 24
Finished Jun 13 01:13:10 PM PDT 24
Peak memory 216784 kb
Host smart-04a7757d-3d90-4048-ab63-ef971cf9158d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460854306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1460854306
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2973381015
Short name T249
Test name
Test status
Simulation time 72930745255 ps
CPU time 452.78 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:20:29 PM PDT 24
Peak memory 236380 kb
Host smart-3e17fa1b-5a48-418e-9d48-b28422eb36c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973381015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2973381015
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3411575620
Short name T171
Test name
Test status
Simulation time 4794557836 ps
CPU time 27.59 seconds
Started Jun 13 01:12:53 PM PDT 24
Finished Jun 13 01:13:21 PM PDT 24
Peak memory 215564 kb
Host smart-8ed281c9-1251-4bde-a711-fe62f20592e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411575620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3411575620
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3557929862
Short name T219
Test name
Test status
Simulation time 3865611449 ps
CPU time 33.46 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:13:30 PM PDT 24
Peak memory 219356 kb
Host smart-0e7d23cc-0c82-41cb-b010-e86ab1688837
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557929862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3557929862
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2085407811
Short name T310
Test name
Test status
Simulation time 7650410833 ps
CPU time 47.02 seconds
Started Jun 13 01:12:54 PM PDT 24
Finished Jun 13 01:13:43 PM PDT 24
Peak memory 216736 kb
Host smart-4f13165e-3c93-4c75-8915-65ebc9bb9647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085407811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2085407811
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3245085877
Short name T263
Test name
Test status
Simulation time 8405105953 ps
CPU time 38.2 seconds
Started Jun 13 01:12:54 PM PDT 24
Finished Jun 13 01:13:34 PM PDT 24
Peak memory 214500 kb
Host smart-e0edf0d2-8b5d-4ce4-88bd-435be045f2e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245085877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3245085877
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.353010232
Short name T72
Test name
Test status
Simulation time 6586512124 ps
CPU time 18.54 seconds
Started Jun 13 01:13:04 PM PDT 24
Finished Jun 13 01:13:24 PM PDT 24
Peak memory 217412 kb
Host smart-1e826d64-88a3-4b6a-9be3-24de1673a28e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353010232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.353010232
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1458746799
Short name T35
Test name
Test status
Simulation time 205689885941 ps
CPU time 691.39 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:24:28 PM PDT 24
Peak memory 217852 kb
Host smart-f4e23d36-ec80-4267-9dc6-94604ca31344
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458746799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1458746799
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2089609080
Short name T328
Test name
Test status
Simulation time 23967661965 ps
CPU time 54.88 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:13:51 PM PDT 24
Peak memory 219296 kb
Host smart-4e710bec-8a72-4fa7-9998-c4e8424d2b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089609080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2089609080
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1252830385
Short name T264
Test name
Test status
Simulation time 186752103 ps
CPU time 10.54 seconds
Started Jun 13 01:13:02 PM PDT 24
Finished Jun 13 01:13:15 PM PDT 24
Peak memory 219220 kb
Host smart-89eabbff-ffa6-4a79-8831-fc33000f285f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252830385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1252830385
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3056624798
Short name T332
Test name
Test status
Simulation time 16430746547 ps
CPU time 48.1 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:13:45 PM PDT 24
Peak memory 217284 kb
Host smart-151cb7c3-9108-4a25-9203-2b485acb309f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056624798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3056624798
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2047618393
Short name T344
Test name
Test status
Simulation time 4356202125 ps
CPU time 72.36 seconds
Started Jun 13 01:12:55 PM PDT 24
Finished Jun 13 01:14:10 PM PDT 24
Peak memory 220296 kb
Host smart-a4ea65ee-04be-4099-a2d7-fbd024774f26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047618393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2047618393
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1942597218
Short name T236
Test name
Test status
Simulation time 16139934823 ps
CPU time 32.85 seconds
Started Jun 13 01:13:02 PM PDT 24
Finished Jun 13 01:13:37 PM PDT 24
Peak memory 217472 kb
Host smart-53b2ede3-19f0-41e3-a196-152c1519960a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942597218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1942597218
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3556340458
Short name T74
Test name
Test status
Simulation time 18423620095 ps
CPU time 198.64 seconds
Started Jun 13 01:13:05 PM PDT 24
Finished Jun 13 01:16:25 PM PDT 24
Peak memory 234624 kb
Host smart-470da158-1ef2-460b-a233-7cb5df627c68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556340458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3556340458
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1021481336
Short name T342
Test name
Test status
Simulation time 1310942675 ps
CPU time 27.73 seconds
Started Jun 13 01:13:02 PM PDT 24
Finished Jun 13 01:13:32 PM PDT 24
Peak memory 218392 kb
Host smart-19aa7f49-04d2-47d2-949f-a6a3e91e830f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021481336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1021481336
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1859289279
Short name T201
Test name
Test status
Simulation time 9120800071 ps
CPU time 35.62 seconds
Started Jun 13 01:13:00 PM PDT 24
Finished Jun 13 01:13:38 PM PDT 24
Peak memory 219348 kb
Host smart-077a0987-1648-4c7c-8865-73545232751c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859289279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1859289279
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.634663321
Short name T250
Test name
Test status
Simulation time 33541485474 ps
CPU time 78.89 seconds
Started Jun 13 01:13:00 PM PDT 24
Finished Jun 13 01:14:22 PM PDT 24
Peak memory 216664 kb
Host smart-8a96ac96-18a7-40d7-973b-b964ef7ca9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634663321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.634663321
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3333892407
Short name T142
Test name
Test status
Simulation time 13255744372 ps
CPU time 87.73 seconds
Started Jun 13 01:13:05 PM PDT 24
Finished Jun 13 01:14:34 PM PDT 24
Peak memory 218136 kb
Host smart-6c903cbb-1b96-4853-8cad-587dbd53f128
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333892407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3333892407
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.41758275
Short name T270
Test name
Test status
Simulation time 825608458 ps
CPU time 8.58 seconds
Started Jun 13 01:13:00 PM PDT 24
Finished Jun 13 01:13:11 PM PDT 24
Peak memory 217056 kb
Host smart-0d2e0b06-4858-4c61-894f-99bbebe8f61d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41758275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.41758275
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.594283269
Short name T16
Test name
Test status
Simulation time 5121676676 ps
CPU time 35.57 seconds
Started Jun 13 01:12:59 PM PDT 24
Finished Jun 13 01:13:37 PM PDT 24
Peak memory 219128 kb
Host smart-c35abaf5-9e4a-4a0a-969d-78d72c9a380f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594283269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.594283269
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.616836673
Short name T179
Test name
Test status
Simulation time 3340668505 ps
CPU time 28.94 seconds
Started Jun 13 01:13:02 PM PDT 24
Finished Jun 13 01:13:33 PM PDT 24
Peak memory 219412 kb
Host smart-d7f3e4ee-0cc9-46d5-969b-cb754fa719e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616836673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.616836673
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1543541828
Short name T152
Test name
Test status
Simulation time 18027372527 ps
CPU time 33.91 seconds
Started Jun 13 01:13:04 PM PDT 24
Finished Jun 13 01:13:40 PM PDT 24
Peak memory 217288 kb
Host smart-5fec87bb-e876-4e30-ac32-47633f1e3916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543541828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1543541828
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3644899134
Short name T317
Test name
Test status
Simulation time 11868228635 ps
CPU time 76.29 seconds
Started Jun 13 01:13:02 PM PDT 24
Finished Jun 13 01:14:21 PM PDT 24
Peak memory 219320 kb
Host smart-e8d72374-c388-40c6-944b-acadc3cd996d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644899134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3644899134
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3617199992
Short name T15
Test name
Test status
Simulation time 296747462 ps
CPU time 8.4 seconds
Started Jun 13 01:11:48 PM PDT 24
Finished Jun 13 01:11:57 PM PDT 24
Peak memory 216944 kb
Host smart-8040fafc-58a8-4f80-8915-8d5270684253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617199992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3617199992
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3056696415
Short name T312
Test name
Test status
Simulation time 86516959013 ps
CPU time 673.32 seconds
Started Jun 13 01:11:39 PM PDT 24
Finished Jun 13 01:22:53 PM PDT 24
Peak memory 230104 kb
Host smart-f11bdae9-66a6-4f3d-b50a-bbc025c058f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056696415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3056696415
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3153239122
Short name T232
Test name
Test status
Simulation time 978690158 ps
CPU time 22.59 seconds
Started Jun 13 01:11:48 PM PDT 24
Finished Jun 13 01:12:11 PM PDT 24
Peak memory 219264 kb
Host smart-bba587c8-8611-49a5-92a6-d9712957072f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153239122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3153239122
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1206088898
Short name T218
Test name
Test status
Simulation time 730908559 ps
CPU time 10.95 seconds
Started Jun 13 01:11:39 PM PDT 24
Finished Jun 13 01:11:52 PM PDT 24
Peak memory 219320 kb
Host smart-44a4ee84-f4f7-4889-87de-d0d0f0656d9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1206088898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1206088898
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1971375657
Short name T29
Test name
Test status
Simulation time 15204877037 ps
CPU time 239.04 seconds
Started Jun 13 01:11:44 PM PDT 24
Finished Jun 13 01:15:44 PM PDT 24
Peak memory 237956 kb
Host smart-f94774bd-67a2-44a3-9ab5-028fcbbb858e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971375657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1971375657
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1543525748
Short name T22
Test name
Test status
Simulation time 533730519 ps
CPU time 23.37 seconds
Started Jun 13 01:11:44 PM PDT 24
Finished Jun 13 01:12:08 PM PDT 24
Peak memory 215216 kb
Host smart-9f9fa01c-7515-4e6c-9b16-bf472f5fabfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543525748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1543525748
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2421982684
Short name T150
Test name
Test status
Simulation time 19727684695 ps
CPU time 60.7 seconds
Started Jun 13 01:11:40 PM PDT 24
Finished Jun 13 01:12:42 PM PDT 24
Peak memory 219328 kb
Host smart-13def4c2-a6e1-4351-9b88-4a1d8ef9a5a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421982684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2421982684
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1752741206
Short name T345
Test name
Test status
Simulation time 3692623927 ps
CPU time 30.67 seconds
Started Jun 13 01:13:12 PM PDT 24
Finished Jun 13 01:13:44 PM PDT 24
Peak memory 217088 kb
Host smart-c6ae00bc-d252-493e-bc55-2ce7592b4f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752741206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1752741206
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3546693462
Short name T113
Test name
Test status
Simulation time 384936118412 ps
CPU time 476.43 seconds
Started Jun 13 01:13:04 PM PDT 24
Finished Jun 13 01:21:02 PM PDT 24
Peak memory 236968 kb
Host smart-15d944e8-08ae-4427-b410-6679d90c1604
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546693462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3546693462
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1040196299
Short name T38
Test name
Test status
Simulation time 58455209483 ps
CPU time 45.06 seconds
Started Jun 13 01:13:08 PM PDT 24
Finished Jun 13 01:13:54 PM PDT 24
Peak memory 219304 kb
Host smart-e163e88f-4011-45af-b798-4051a4fae902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040196299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1040196299
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.246611802
Short name T183
Test name
Test status
Simulation time 10906527393 ps
CPU time 25.53 seconds
Started Jun 13 01:13:00 PM PDT 24
Finished Jun 13 01:13:28 PM PDT 24
Peak memory 217624 kb
Host smart-b243ca49-5aca-4094-b6d3-1fefd381f823
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246611802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.246611802
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2358964999
Short name T211
Test name
Test status
Simulation time 15453238534 ps
CPU time 73.22 seconds
Started Jun 13 01:13:01 PM PDT 24
Finished Jun 13 01:14:17 PM PDT 24
Peak memory 216672 kb
Host smart-caefdfde-c071-4735-8c3b-2480a26afbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358964999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2358964999
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1442028807
Short name T272
Test name
Test status
Simulation time 10805313518 ps
CPU time 46.49 seconds
Started Jun 13 01:13:00 PM PDT 24
Finished Jun 13 01:13:49 PM PDT 24
Peak memory 219304 kb
Host smart-9bf6642b-7b06-497d-badf-37126215ac7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442028807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1442028807
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2002737170
Short name T58
Test name
Test status
Simulation time 3030926717 ps
CPU time 26.98 seconds
Started Jun 13 01:13:08 PM PDT 24
Finished Jun 13 01:13:36 PM PDT 24
Peak memory 217024 kb
Host smart-7603a2d6-2570-4d34-b302-662e3369844d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002737170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2002737170
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1008634704
Short name T161
Test name
Test status
Simulation time 27298974278 ps
CPU time 316.02 seconds
Started Jun 13 01:13:09 PM PDT 24
Finished Jun 13 01:18:26 PM PDT 24
Peak memory 239536 kb
Host smart-c17dc0aa-97cd-4408-a01b-81bc3002c415
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008634704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1008634704
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4213468629
Short name T33
Test name
Test status
Simulation time 27567955245 ps
CPU time 61.37 seconds
Started Jun 13 01:13:09 PM PDT 24
Finished Jun 13 01:14:12 PM PDT 24
Peak memory 219180 kb
Host smart-24e0698b-c6ec-406c-a455-08fd0fa2e901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213468629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4213468629
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3507086611
Short name T293
Test name
Test status
Simulation time 668471413 ps
CPU time 15.25 seconds
Started Jun 13 01:13:11 PM PDT 24
Finished Jun 13 01:13:28 PM PDT 24
Peak memory 218396 kb
Host smart-26f6eb1e-cbdd-43b9-a4c6-a0db453d94dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3507086611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3507086611
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4180953548
Short name T192
Test name
Test status
Simulation time 5688087752 ps
CPU time 37.69 seconds
Started Jun 13 01:13:08 PM PDT 24
Finished Jun 13 01:13:47 PM PDT 24
Peak memory 216544 kb
Host smart-7d2f1fa8-d82c-43d6-b27e-bfeb0cebb8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180953548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4180953548
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1143498632
Short name T31
Test name
Test status
Simulation time 325523101 ps
CPU time 8.27 seconds
Started Jun 13 01:13:08 PM PDT 24
Finished Jun 13 01:13:17 PM PDT 24
Peak memory 217940 kb
Host smart-ae2d631a-d278-49dd-accd-1e9749c74b55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143498632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1143498632
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1320221917
Short name T136
Test name
Test status
Simulation time 394788697118 ps
CPU time 520.57 seconds
Started Jun 13 01:13:08 PM PDT 24
Finished Jun 13 01:21:49 PM PDT 24
Peak memory 237488 kb
Host smart-1e5e409f-4693-41b2-949f-ab9e77cc8261
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320221917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1320221917
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3147685991
Short name T244
Test name
Test status
Simulation time 11739914481 ps
CPU time 55.57 seconds
Started Jun 13 01:13:11 PM PDT 24
Finished Jun 13 01:14:08 PM PDT 24
Peak memory 219220 kb
Host smart-45ae6b45-8e99-4e17-81ef-fba78fd91b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147685991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3147685991
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2903339277
Short name T223
Test name
Test status
Simulation time 7252793050 ps
CPU time 21.88 seconds
Started Jun 13 01:13:14 PM PDT 24
Finished Jun 13 01:13:37 PM PDT 24
Peak memory 217668 kb
Host smart-18ad4b49-7eb8-4265-bd11-11b8490d933d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903339277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2903339277
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3921492958
Short name T112
Test name
Test status
Simulation time 7459235207 ps
CPU time 62.45 seconds
Started Jun 13 01:13:13 PM PDT 24
Finished Jun 13 01:14:17 PM PDT 24
Peak memory 217104 kb
Host smart-1b31c212-8342-41ee-ad81-4a93ddc27178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921492958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3921492958
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.805904619
Short name T274
Test name
Test status
Simulation time 7326752534 ps
CPU time 68.43 seconds
Started Jun 13 01:13:08 PM PDT 24
Finished Jun 13 01:14:18 PM PDT 24
Peak memory 219300 kb
Host smart-5aa0959e-79ae-4383-9a49-39401f484deb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805904619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.805904619
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.4282488260
Short name T46
Test name
Test status
Simulation time 53451255367 ps
CPU time 1246.3 seconds
Started Jun 13 01:13:09 PM PDT 24
Finished Jun 13 01:33:56 PM PDT 24
Peak memory 236964 kb
Host smart-def877f3-b68c-43ef-aa35-8687c760999f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282488260 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.4282488260
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4240871346
Short name T203
Test name
Test status
Simulation time 174449174 ps
CPU time 8.6 seconds
Started Jun 13 01:13:12 PM PDT 24
Finished Jun 13 01:13:22 PM PDT 24
Peak memory 217112 kb
Host smart-b6b5703d-afd8-4770-b010-c6f502ecee21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240871346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4240871346
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2534917243
Short name T256
Test name
Test status
Simulation time 305454766181 ps
CPU time 649.96 seconds
Started Jun 13 01:13:10 PM PDT 24
Finished Jun 13 01:24:01 PM PDT 24
Peak memory 227452 kb
Host smart-8bf745e5-9b70-4194-9218-1595149d6587
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534917243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2534917243
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3356321413
Short name T170
Test name
Test status
Simulation time 28328773490 ps
CPU time 71.15 seconds
Started Jun 13 01:13:08 PM PDT 24
Finished Jun 13 01:14:20 PM PDT 24
Peak memory 219276 kb
Host smart-9ed027ff-9a21-4cb6-a110-3263ec48f61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356321413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3356321413
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2215312310
Short name T143
Test name
Test status
Simulation time 6491797960 ps
CPU time 28.11 seconds
Started Jun 13 01:13:11 PM PDT 24
Finished Jun 13 01:13:40 PM PDT 24
Peak memory 211668 kb
Host smart-e5747ee7-bd09-41b2-aa54-dcec804b29d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215312310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2215312310
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2709553768
Short name T315
Test name
Test status
Simulation time 15314990918 ps
CPU time 84.17 seconds
Started Jun 13 01:13:09 PM PDT 24
Finished Jun 13 01:14:34 PM PDT 24
Peak memory 219296 kb
Host smart-d788f915-c7a1-4cc4-bf68-bb771a52984f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709553768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2709553768
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3755292149
Short name T68
Test name
Test status
Simulation time 8477620471 ps
CPU time 33.64 seconds
Started Jun 13 01:13:16 PM PDT 24
Finished Jun 13 01:13:51 PM PDT 24
Peak memory 217328 kb
Host smart-46191c39-ec66-4226-9c58-2817b2510507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755292149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3755292149
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1374036041
Short name T286
Test name
Test status
Simulation time 44694013404 ps
CPU time 543.14 seconds
Started Jun 13 01:13:10 PM PDT 24
Finished Jun 13 01:22:15 PM PDT 24
Peak memory 233844 kb
Host smart-0225f7ec-9b53-4f3f-ae3b-70517908ce48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374036041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1374036041
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.218238129
Short name T44
Test name
Test status
Simulation time 480316905 ps
CPU time 18.92 seconds
Started Jun 13 01:13:30 PM PDT 24
Finished Jun 13 01:13:50 PM PDT 24
Peak memory 219164 kb
Host smart-2a371847-8508-48e9-8a59-4cf4e649ba49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218238129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.218238129
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.4181053297
Short name T55
Test name
Test status
Simulation time 8242133710 ps
CPU time 24.02 seconds
Started Jun 13 01:13:09 PM PDT 24
Finished Jun 13 01:13:34 PM PDT 24
Peak memory 219348 kb
Host smart-25d75c96-ab50-4ad1-ba21-0bae6ef4bfb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181053297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.4181053297
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2497984788
Short name T56
Test name
Test status
Simulation time 345001127 ps
CPU time 19.91 seconds
Started Jun 13 01:13:09 PM PDT 24
Finished Jun 13 01:13:31 PM PDT 24
Peak memory 215832 kb
Host smart-02c80509-a663-4074-bc45-9cad91946a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497984788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2497984788
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4123154456
Short name T2
Test name
Test status
Simulation time 8197129767 ps
CPU time 66.96 seconds
Started Jun 13 01:13:09 PM PDT 24
Finished Jun 13 01:14:18 PM PDT 24
Peak memory 218504 kb
Host smart-36a04509-e632-4a9e-9506-8876c803a273
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123154456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4123154456
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1485070105
Short name T66
Test name
Test status
Simulation time 167545719 ps
CPU time 8.33 seconds
Started Jun 13 01:13:29 PM PDT 24
Finished Jun 13 01:13:38 PM PDT 24
Peak memory 217028 kb
Host smart-18200d4e-d71c-4d08-8c12-9455ff6a9c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485070105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1485070105
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1027301489
Short name T59
Test name
Test status
Simulation time 3880514651 ps
CPU time 309.97 seconds
Started Jun 13 01:13:16 PM PDT 24
Finished Jun 13 01:18:26 PM PDT 24
Peak memory 240016 kb
Host smart-4406e1b8-ea27-44b0-9854-48ea77c22492
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027301489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1027301489
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.190539581
Short name T191
Test name
Test status
Simulation time 6610873486 ps
CPU time 59.21 seconds
Started Jun 13 01:13:15 PM PDT 24
Finished Jun 13 01:14:15 PM PDT 24
Peak memory 219280 kb
Host smart-7090cc1b-c1a9-4938-aa9f-948eb16b105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190539581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.190539581
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.64089280
Short name T145
Test name
Test status
Simulation time 5874810957 ps
CPU time 32.4 seconds
Started Jun 13 01:13:30 PM PDT 24
Finished Jun 13 01:14:03 PM PDT 24
Peak memory 219276 kb
Host smart-c8064766-9134-4210-a88f-03f215255b5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64089280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.64089280
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.936846969
Short name T245
Test name
Test status
Simulation time 21482742637 ps
CPU time 57.48 seconds
Started Jun 13 01:13:16 PM PDT 24
Finished Jun 13 01:14:14 PM PDT 24
Peak memory 217040 kb
Host smart-1a3e0096-161f-48dd-a53d-247d75f634f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936846969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.936846969
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2353249368
Short name T343
Test name
Test status
Simulation time 7079675595 ps
CPU time 41.29 seconds
Started Jun 13 01:13:15 PM PDT 24
Finished Jun 13 01:13:56 PM PDT 24
Peak memory 219316 kb
Host smart-83194637-a907-4575-a0de-3b2031ff86ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353249368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2353249368
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.580988269
Short name T71
Test name
Test status
Simulation time 7130502787 ps
CPU time 23.14 seconds
Started Jun 13 01:13:17 PM PDT 24
Finished Jun 13 01:13:41 PM PDT 24
Peak memory 217384 kb
Host smart-6ea5023e-88d4-4aeb-9430-9bff9240f0bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580988269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.580988269
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1204466174
Short name T196
Test name
Test status
Simulation time 195755760124 ps
CPU time 468.6 seconds
Started Jun 13 01:13:15 PM PDT 24
Finished Jun 13 01:21:04 PM PDT 24
Peak memory 233520 kb
Host smart-b1436977-6e2a-42b1-96f7-cba764bc536e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204466174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1204466174
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2629746592
Short name T339
Test name
Test status
Simulation time 690184698 ps
CPU time 23.84 seconds
Started Jun 13 01:13:26 PM PDT 24
Finished Jun 13 01:13:52 PM PDT 24
Peak memory 218580 kb
Host smart-41e6c224-93a6-45a1-898a-8569e529ddda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629746592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2629746592
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1205536867
Short name T309
Test name
Test status
Simulation time 184989982 ps
CPU time 10.24 seconds
Started Jun 13 01:13:26 PM PDT 24
Finished Jun 13 01:13:38 PM PDT 24
Peak memory 218876 kb
Host smart-e48b3f9d-1697-49f4-8805-1303304e1abb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1205536867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1205536867
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.896678467
Short name T188
Test name
Test status
Simulation time 2975223125 ps
CPU time 31.21 seconds
Started Jun 13 01:13:17 PM PDT 24
Finished Jun 13 01:13:48 PM PDT 24
Peak memory 216280 kb
Host smart-1cfb60c9-e1cc-4e98-8278-739bd0b53202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896678467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.896678467
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3954025633
Short name T246
Test name
Test status
Simulation time 10719127802 ps
CPU time 41.64 seconds
Started Jun 13 01:13:17 PM PDT 24
Finished Jun 13 01:13:59 PM PDT 24
Peak memory 219116 kb
Host smart-cf1a8b43-9727-4a4c-ae8d-c62d839d08c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954025633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3954025633
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.73873050
Short name T158
Test name
Test status
Simulation time 1066371807 ps
CPU time 15.87 seconds
Started Jun 13 01:13:21 PM PDT 24
Finished Jun 13 01:13:37 PM PDT 24
Peak memory 217016 kb
Host smart-0b78a1a3-3342-4743-b22c-040983930fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73873050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.73873050
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2947536822
Short name T215
Test name
Test status
Simulation time 9903858882 ps
CPU time 346.38 seconds
Started Jun 13 01:13:23 PM PDT 24
Finished Jun 13 01:19:10 PM PDT 24
Peak memory 237672 kb
Host smart-e9ec761c-ab0f-4da3-9512-605784c93e07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947536822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2947536822
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1499623670
Short name T329
Test name
Test status
Simulation time 7980117646 ps
CPU time 66.04 seconds
Started Jun 13 01:13:26 PM PDT 24
Finished Jun 13 01:14:34 PM PDT 24
Peak memory 219280 kb
Host smart-b4d974d5-d2a7-444f-8f58-963bdf34feca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499623670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1499623670
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1614335403
Short name T299
Test name
Test status
Simulation time 4453395348 ps
CPU time 23.08 seconds
Started Jun 13 01:13:26 PM PDT 24
Finished Jun 13 01:13:51 PM PDT 24
Peak memory 218984 kb
Host smart-4b929444-d276-4d00-804e-7f03657b054d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1614335403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1614335403
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1599868706
Short name T122
Test name
Test status
Simulation time 6839220580 ps
CPU time 57.58 seconds
Started Jun 13 01:13:30 PM PDT 24
Finished Jun 13 01:14:29 PM PDT 24
Peak memory 217064 kb
Host smart-e98ed449-3b18-4456-ad16-c3037b40beec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599868706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1599868706
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1237318949
Short name T210
Test name
Test status
Simulation time 358545015 ps
CPU time 24.05 seconds
Started Jun 13 01:13:16 PM PDT 24
Finished Jun 13 01:13:41 PM PDT 24
Peak memory 219196 kb
Host smart-712f6d73-72ae-48a7-96a1-57160c49aa2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237318949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1237318949
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.542142270
Short name T174
Test name
Test status
Simulation time 57633510037 ps
CPU time 31.79 seconds
Started Jun 13 01:13:25 PM PDT 24
Finished Jun 13 01:13:58 PM PDT 24
Peak memory 217328 kb
Host smart-6398701e-077e-4e5c-a4a7-62b682b942fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542142270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.542142270
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.491120265
Short name T7
Test name
Test status
Simulation time 23467398888 ps
CPU time 226.06 seconds
Started Jun 13 01:13:22 PM PDT 24
Finished Jun 13 01:17:09 PM PDT 24
Peak memory 234864 kb
Host smart-abb3b907-da78-45c3-81ce-69b49471444a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491120265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.491120265
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2119895705
Short name T238
Test name
Test status
Simulation time 8020872081 ps
CPU time 68.43 seconds
Started Jun 13 01:13:24 PM PDT 24
Finished Jun 13 01:14:34 PM PDT 24
Peak memory 219188 kb
Host smart-7b0a5b14-5166-44c6-83f1-57708f8d6ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119895705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2119895705
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.462461620
Short name T340
Test name
Test status
Simulation time 17804870527 ps
CPU time 34.05 seconds
Started Jun 13 01:13:24 PM PDT 24
Finished Jun 13 01:14:00 PM PDT 24
Peak memory 219316 kb
Host smart-e8032876-1aef-46a4-9fb1-4a6bf537ba92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=462461620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.462461620
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.49592215
Short name T243
Test name
Test status
Simulation time 5315952170 ps
CPU time 49.13 seconds
Started Jun 13 01:13:25 PM PDT 24
Finished Jun 13 01:14:15 PM PDT 24
Peak memory 216528 kb
Host smart-0ba1c366-4ee6-40be-b8d6-2ab26d2d39b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49592215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.49592215
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2752482252
Short name T331
Test name
Test status
Simulation time 373875037 ps
CPU time 20.11 seconds
Started Jun 13 01:13:24 PM PDT 24
Finished Jun 13 01:13:46 PM PDT 24
Peak memory 217980 kb
Host smart-985d122a-5ab3-4ae0-aa6d-090851d6e436
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752482252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2752482252
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.784891150
Short name T110
Test name
Test status
Simulation time 1546017455 ps
CPU time 13.83 seconds
Started Jun 13 01:13:30 PM PDT 24
Finished Jun 13 01:13:45 PM PDT 24
Peak memory 217040 kb
Host smart-c410d489-39cb-4d8e-828c-bc7b631697da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784891150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.784891150
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3299377443
Short name T185
Test name
Test status
Simulation time 3877126581 ps
CPU time 32.41 seconds
Started Jun 13 01:13:23 PM PDT 24
Finished Jun 13 01:13:57 PM PDT 24
Peak memory 219316 kb
Host smart-e252974f-0335-429f-96bb-15dc228a6111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299377443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3299377443
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.838667324
Short name T32
Test name
Test status
Simulation time 2350779960 ps
CPU time 22.66 seconds
Started Jun 13 01:13:23 PM PDT 24
Finished Jun 13 01:13:47 PM PDT 24
Peak memory 219316 kb
Host smart-15108b79-1b8c-4228-b5fc-02774c0c150d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838667324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.838667324
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3669655434
Short name T20
Test name
Test status
Simulation time 676194384 ps
CPU time 19.78 seconds
Started Jun 13 01:13:25 PM PDT 24
Finished Jun 13 01:13:46 PM PDT 24
Peak memory 215780 kb
Host smart-79831e68-536f-4080-b820-7bb92bb0df0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669655434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3669655434
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2616805426
Short name T65
Test name
Test status
Simulation time 17558624166 ps
CPU time 63.84 seconds
Started Jun 13 01:13:26 PM PDT 24
Finished Jun 13 01:14:32 PM PDT 24
Peak memory 219344 kb
Host smart-f2e4da0a-0eaf-450f-8516-29e72473bab0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616805426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2616805426
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.679850148
Short name T165
Test name
Test status
Simulation time 502737254 ps
CPU time 11.5 seconds
Started Jun 13 01:11:44 PM PDT 24
Finished Jun 13 01:11:57 PM PDT 24
Peak memory 216928 kb
Host smart-1e055adf-d5b6-4ccd-ad72-33a2ab74b18c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679850148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.679850148
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2270382898
Short name T155
Test name
Test status
Simulation time 8545523887 ps
CPU time 153.7 seconds
Started Jun 13 01:11:46 PM PDT 24
Finished Jun 13 01:14:21 PM PDT 24
Peak memory 237800 kb
Host smart-f1c656ff-3d1b-4a40-9b0c-47dd1003bbf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270382898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2270382898
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2151594423
Short name T269
Test name
Test status
Simulation time 10060559065 ps
CPU time 45.22 seconds
Started Jun 13 01:11:45 PM PDT 24
Finished Jun 13 01:12:31 PM PDT 24
Peak memory 219284 kb
Host smart-d037be00-d5f6-4abf-850e-15f4398ca41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151594423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2151594423
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1561999282
Short name T231
Test name
Test status
Simulation time 9600514498 ps
CPU time 34.18 seconds
Started Jun 13 01:11:46 PM PDT 24
Finished Jun 13 01:12:21 PM PDT 24
Peak memory 216720 kb
Host smart-6cccc743-2d68-4280-8b73-0bc93c88ae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561999282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1561999282
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1621424149
Short name T227
Test name
Test status
Simulation time 3957584969 ps
CPU time 32.9 seconds
Started Jun 13 01:11:44 PM PDT 24
Finished Jun 13 01:12:18 PM PDT 24
Peak memory 214500 kb
Host smart-d191ab7f-a757-4a44-8d9a-8967e5090757
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621424149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1621424149
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1013996655
Short name T234
Test name
Test status
Simulation time 3518500729 ps
CPU time 31.24 seconds
Started Jun 13 01:11:44 PM PDT 24
Finished Jun 13 01:12:17 PM PDT 24
Peak memory 217104 kb
Host smart-acf2793a-bca3-4ac2-a419-2bc5a558b992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013996655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1013996655
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.58429034
Short name T356
Test name
Test status
Simulation time 3293078846 ps
CPU time 26.29 seconds
Started Jun 13 01:11:54 PM PDT 24
Finished Jun 13 01:12:21 PM PDT 24
Peak memory 218584 kb
Host smart-7abbc22d-17e3-42ef-8087-8c01fd2cdc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58429034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.58429034
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3698810676
Short name T280
Test name
Test status
Simulation time 1658361711 ps
CPU time 20.48 seconds
Started Jun 13 01:11:51 PM PDT 24
Finished Jun 13 01:12:12 PM PDT 24
Peak memory 219276 kb
Host smart-715be247-1ab1-4a8b-932b-41366fee7b36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3698810676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3698810676
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.675903557
Short name T355
Test name
Test status
Simulation time 15003992313 ps
CPU time 71.08 seconds
Started Jun 13 01:11:45 PM PDT 24
Finished Jun 13 01:12:57 PM PDT 24
Peak memory 216300 kb
Host smart-42edd694-8715-4bd3-b24b-dc5c70d77421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675903557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.675903557
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4104597770
Short name T200
Test name
Test status
Simulation time 17053924718 ps
CPU time 89.65 seconds
Started Jun 13 01:11:47 PM PDT 24
Finished Jun 13 01:13:18 PM PDT 24
Peak memory 219304 kb
Host smart-b6ce5dea-b5dc-4295-8371-e62589259e08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104597770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4104597770
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3713810441
Short name T265
Test name
Test status
Simulation time 4398071219 ps
CPU time 21.07 seconds
Started Jun 13 01:11:48 PM PDT 24
Finished Jun 13 01:12:10 PM PDT 24
Peak memory 217416 kb
Host smart-63d99d2d-f047-4810-accf-7e68ddd8e006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713810441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3713810441
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1004480363
Short name T193
Test name
Test status
Simulation time 20545850841 ps
CPU time 335.64 seconds
Started Jun 13 01:11:47 PM PDT 24
Finished Jun 13 01:17:24 PM PDT 24
Peak memory 239308 kb
Host smart-8ccf41a4-6536-4471-ac10-4fd68b35b130
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004480363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1004480363
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1638901359
Short name T289
Test name
Test status
Simulation time 688796274 ps
CPU time 19.58 seconds
Started Jun 13 01:11:46 PM PDT 24
Finished Jun 13 01:12:06 PM PDT 24
Peak memory 219232 kb
Host smart-20d46997-5267-44ea-bce3-daf5e7e99632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638901359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1638901359
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.804084317
Short name T198
Test name
Test status
Simulation time 13947823374 ps
CPU time 33.95 seconds
Started Jun 13 01:11:47 PM PDT 24
Finished Jun 13 01:12:22 PM PDT 24
Peak memory 217540 kb
Host smart-0b602e86-fdd9-4577-96c8-4662cf963354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=804084317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.804084317
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.340478718
Short name T319
Test name
Test status
Simulation time 8140402766 ps
CPU time 67.13 seconds
Started Jun 13 01:11:47 PM PDT 24
Finished Jun 13 01:12:55 PM PDT 24
Peak memory 217416 kb
Host smart-15938a46-f314-41e8-bab6-0cbeffcb7537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340478718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.340478718
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3447789794
Short name T157
Test name
Test status
Simulation time 18898162426 ps
CPU time 175.29 seconds
Started Jun 13 01:11:44 PM PDT 24
Finished Jun 13 01:14:41 PM PDT 24
Peak memory 219432 kb
Host smart-6605b0aa-f431-440f-9d17-4a38bca070fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447789794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3447789794
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3649499830
Short name T277
Test name
Test status
Simulation time 1026846294 ps
CPU time 11.81 seconds
Started Jun 13 01:11:50 PM PDT 24
Finished Jun 13 01:12:02 PM PDT 24
Peak memory 217028 kb
Host smart-77ea6cd7-39e9-4ebf-a6b5-310a6c2093b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649499830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3649499830
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3087218686
Short name T159
Test name
Test status
Simulation time 2990423383 ps
CPU time 205.45 seconds
Started Jun 13 01:11:45 PM PDT 24
Finished Jun 13 01:15:11 PM PDT 24
Peak memory 239696 kb
Host smart-43d8031b-243c-4e30-8400-dc5667e800eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087218686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3087218686
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.4076417827
Short name T11
Test name
Test status
Simulation time 27874586611 ps
CPU time 56.8 seconds
Started Jun 13 01:11:45 PM PDT 24
Finished Jun 13 01:12:43 PM PDT 24
Peak memory 219348 kb
Host smart-1bf7cac0-e92e-4932-8ed9-dca66ede60ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076417827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.4076417827
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3166721785
Short name T73
Test name
Test status
Simulation time 2861495223 ps
CPU time 27.24 seconds
Started Jun 13 01:11:54 PM PDT 24
Finished Jun 13 01:12:22 PM PDT 24
Peak memory 219340 kb
Host smart-d30be370-1beb-4aa7-a0b4-96d783cdfe2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166721785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3166721785
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.964081952
Short name T283
Test name
Test status
Simulation time 13466465513 ps
CPU time 57.55 seconds
Started Jun 13 01:11:46 PM PDT 24
Finished Jun 13 01:12:44 PM PDT 24
Peak memory 217132 kb
Host smart-1898ab4a-3396-462e-bcc5-d5e1b3d91a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964081952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.964081952
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3772521016
Short name T285
Test name
Test status
Simulation time 12630700996 ps
CPU time 63.87 seconds
Started Jun 13 01:11:44 PM PDT 24
Finished Jun 13 01:12:48 PM PDT 24
Peak memory 217188 kb
Host smart-8176ace1-7486-4bb3-8a49-3cde4a38888a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772521016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3772521016
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1573711590
Short name T67
Test name
Test status
Simulation time 331853224 ps
CPU time 8.43 seconds
Started Jun 13 01:11:45 PM PDT 24
Finished Jun 13 01:11:54 PM PDT 24
Peak memory 216996 kb
Host smart-d2cda735-75e9-43b7-9c19-8b117204bf3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573711590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1573711590
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1171601634
Short name T53
Test name
Test status
Simulation time 36792627588 ps
CPU time 193.28 seconds
Started Jun 13 01:11:45 PM PDT 24
Finished Jun 13 01:14:59 PM PDT 24
Peak memory 238340 kb
Host smart-cf7b9b71-fcc9-4a43-b72e-943f7400c9db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171601634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1171601634
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2053548016
Short name T321
Test name
Test status
Simulation time 6018870677 ps
CPU time 24.89 seconds
Started Jun 13 01:11:52 PM PDT 24
Finished Jun 13 01:12:17 PM PDT 24
Peak memory 215584 kb
Host smart-74874790-b700-4125-8c2c-dde9c0911572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053548016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2053548016
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.224639236
Short name T260
Test name
Test status
Simulation time 4136928524 ps
CPU time 29.7 seconds
Started Jun 13 01:11:46 PM PDT 24
Finished Jun 13 01:12:17 PM PDT 24
Peak memory 211616 kb
Host smart-827fd037-6be7-40a6-a1a2-58e91c126865
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224639236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.224639236
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1359630138
Short name T21
Test name
Test status
Simulation time 1372407517 ps
CPU time 20.51 seconds
Started Jun 13 01:11:46 PM PDT 24
Finished Jun 13 01:12:08 PM PDT 24
Peak memory 214772 kb
Host smart-8e2fcfe9-8284-4da4-b0d6-8de55e676449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359630138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1359630138
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3555718371
Short name T214
Test name
Test status
Simulation time 30151510530 ps
CPU time 158.67 seconds
Started Jun 13 01:11:46 PM PDT 24
Finished Jun 13 01:14:26 PM PDT 24
Peak memory 221032 kb
Host smart-631ababd-90f3-40f3-b203-6f2e1dbaad47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555718371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3555718371
Directory /workspace/9.rom_ctrl_stress_all/latest
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