Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1338264

1

T1

72

T5

67

T8

52

full_word

853727

1

T1

15

T2

2

T5

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2191701	1			T1	87		T2	2		T5	76
auto[TlIntgErrCmd]	106	1			T51	4		T52	4		T53	3
auto[TlIntgErrData]	95	1			T51	1		T52	4		T53	4
auto[TlIntgErrBoth]	89	1			T51	5		T52	2		T53	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

364822

1

T1

87

T2

2

T5

76

auto[1]

1827169

1

T12

348924

T13

85523

T14

8921

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161246	1			T1	72		T5	67		T8	52
auto[TlIntgErrNone]	partial	auto[1]	1176743	1			T12	224754		T13	55913		T14	5823
auto[TlIntgErrNone]	full_word	auto[0]	203453	1			T1	15		T2	2		T5	9
auto[TlIntgErrNone]	full_word	auto[1]	650259	1			T12	124170		T13	29610		T14	3098
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T51	1		T52	1		T53	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T51	3		T52	2		T53	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T104	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T52	1		T101	1		T102	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T52	3		T53	3		T98	1
auto[TlIntgErrData]	partial	auto[1]	49	1			T51	1		T52	1		T53	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T98	1		T105	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	1	1			T106	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T52	1		T53	3		T98	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T51	3		T52	1		T98	7
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T51	2		T106	1		T102	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T98	1		T107	1		-	-