Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1342350

1

T2

129

T4

119

T6

49

full_word

855536

1

T2

11

T4

15

T6

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2197536	1			T2	140		T4	134		T6	53
auto[TlIntgErrCmd]	122	1			T52	5		T64	8		T65	10
auto[TlIntgErrData]	117	1			T52	3		T64	5		T65	6
auto[TlIntgErrBoth]	111	1			T52	2		T64	7		T65	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

358070

1

T2

140

T4

134

T6

53

auto[1]

1839816

1

T14

359246

T15

167980

T16

436227

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	155013	1			T2	129		T4	119		T6	49
auto[TlIntgErrNone]	partial	auto[1]	1187020	1			T14	228702		T15	108165		T16	281035
auto[TlIntgErrNone]	full_word	auto[0]	202897	1			T2	11		T4	15		T6	4
auto[TlIntgErrNone]	full_word	auto[1]	652606	1			T14	130544		T15	59815		T16	155192
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T52	1		T65	4		T104	1
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T52	3		T64	6		T65	6
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T64	1		T104	1		T108	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T52	1		T64	1		T104	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T52	1		T64	3		T65	4
auto[TlIntgErrData]	partial	auto[1]	60	1			T52	1		T64	2		T65	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T105	1		T109	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T52	1		T104	1		T105	2
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T64	4		T65	1		T104	4
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T52	2		T64	2		T65	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T64	1		T106	1		T111	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T104	1		T112	1		T109	1