Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39111	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

532562

1

T1

9

T3

5

T4

75508

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	163277	1			T1	9		T3	62		T4	20636
values[0x0]	200755	1			T4	28239		T10	38529		T13	17583
values[0x1]	207641	1			T4	29647		T10	39471		T13	18430

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19077	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

552596

1

T1

9

T3

25

T4

76948

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1742	1			T4	319		T10	368		T16	1
valid_sources[0x01]	1628	1			T4	339		T10	397		T16	1
valid_sources[0x02]	2978	1			T4	304		T10	395		T16	2
valid_sources[0x03]	1684	1			T4	299		T10	366		T16	1
valid_sources[0x04]	3393	1			T4	305		T10	402		T16	1
valid_sources[0x05]	2054	1			T4	312		T10	400		T113	3
valid_sources[0x06]	1976	1			T1	2		T4	311		T10	428
valid_sources[0x07]	1927	1			T4	308		T10	400		T16	1
valid_sources[0x08]	1689	1			T3	1		T4	304		T7	37
valid_sources[0x09]	1974	1			T4	312		T10	400		T46	1
valid_sources[0x0a]	2775	1			T4	306		T10	414		T16	3
valid_sources[0x0b]	2331	1			T4	315		T10	462		T14	3
valid_sources[0x0c]	2623	1			T4	298		T10	427		T46	8
valid_sources[0x0d]	2722	1			T4	319		T10	437		T16	3
valid_sources[0x0e]	2036	1			T4	317		T10	401		T46	1
valid_sources[0x0f]	1704	1			T4	295		T10	407		T113	2
valid_sources[0x10]	1872	1			T4	334		T10	383		T16	1
valid_sources[0x11]	1968	1			T4	303		T10	406		T14	6
valid_sources[0x12]	2696	1			T4	341		T10	382		T16	2
valid_sources[0x13]	1738	1			T3	2		T4	288		T10	415
valid_sources[0x14]	1958	1			T3	1		T4	284		T10	393
valid_sources[0x15]	1849	1			T4	321		T10	389		T16	1
valid_sources[0x16]	1784	1			T4	303		T10	389		T16	2
valid_sources[0x17]	1828	1			T4	317		T10	408		T16	1
valid_sources[0x18]	1575	1			T4	349		T10	403		T16	1
valid_sources[0x19]	1902	1			T4	325		T10	392		T16	1
valid_sources[0x1a]	2370	1			T4	297		T10	432		T14	1
valid_sources[0x1b]	2035	1			T4	285		T10	428		T16	1
valid_sources[0x1c]	1644	1			T4	302		T10	428		T15	3
valid_sources[0x1d]	1689	1			T4	287		T10	400		T16	1
valid_sources[0x1e]	1803	1			T4	326		T10	431		T46	1
valid_sources[0x1f]	2084	1			T4	334		T10	389		T16	1
valid_sources[0x20]	2556	1			T3	1		T4	279		T10	419
valid_sources[0x21]	1678	1			T4	308		T10	377		T113	1
valid_sources[0x22]	1625	1			T4	296		T7	34		T10	401
valid_sources[0x23]	2211	1			T4	292		T7	20		T10	406
valid_sources[0x24]	1780	1			T4	302		T10	406		T13	24
valid_sources[0x25]	2643	1			T1	1		T4	303		T10	428
valid_sources[0x26]	2514	1			T4	299		T10	389		T16	2
valid_sources[0x27]	2846	1			T4	342		T10	393		T16	5
valid_sources[0x28]	2244	1			T3	2		T4	315		T10	423
valid_sources[0x29]	2649	1			T4	338		T10	432		T16	2
valid_sources[0x2a]	2157	1			T3	1		T4	300		T10	370
valid_sources[0x2b]	1878	1			T4	299		T10	379		T16	1
valid_sources[0x2c]	2131	1			T3	1		T4	307		T10	443
valid_sources[0x2d]	2383	1			T4	284		T10	415		T113	1
valid_sources[0x2e]	1992	1			T4	276		T10	451		T46	2
valid_sources[0x2f]	3109	1			T4	321		T10	459		T14	8
valid_sources[0x30]	1836	1			T4	301		T10	397		T46	2
valid_sources[0x31]	1936	1			T4	337		T10	424		T16	1
valid_sources[0x32]	4610	1			T3	1		T4	291		T10	445
valid_sources[0x33]	1773	1			T3	1		T4	290		T10	381
valid_sources[0x34]	2146	1			T4	309		T10	453		T46	4
valid_sources[0x35]	1679	1			T4	295		T10	395		T14	1
valid_sources[0x36]	1853	1			T4	309		T10	414		T16	2
valid_sources[0x37]	2921	1			T4	284		T10	384		T16	1
valid_sources[0x38]	2094	1			T4	286		T10	384		T15	8
valid_sources[0x39]	2064	1			T4	286		T10	387		T16	1
valid_sources[0x3a]	1839	1			T4	314		T10	383		T16	2
valid_sources[0x3b]	1915	1			T3	1		T4	308		T10	422
valid_sources[0x3c]	2552	1			T4	316		T10	408		T129	2
valid_sources[0x3d]	2072	1			T4	359		T10	406		T16	3
valid_sources[0x3e]	2018	1			T3	1		T4	323		T10	408
valid_sources[0x3f]	2159	1			T4	296		T10	393		T16	1
valid_sources[0x40]	2108	1			T4	332		T10	405		T17	1
valid_sources[0x41]	1913	1			T4	319		T10	421		T16	2
valid_sources[0x42]	2461	1			T3	1		T4	333		T10	417
valid_sources[0x43]	2488	1			T4	307		T10	380		T13	613
valid_sources[0x44]	1804	1			T3	1		T4	303		T10	432
valid_sources[0x45]	2310	1			T4	317		T7	23		T10	432
valid_sources[0x46]	2016	1			T4	304		T10	402		T16	1
valid_sources[0x47]	1812	1			T4	343		T10	415		T129	2
valid_sources[0x48]	3478	1			T3	1		T4	324		T10	434
valid_sources[0x49]	2377	1			T4	282		T10	415		T15	3
valid_sources[0x4a]	1905	1			T3	1		T4	334		T10	419
valid_sources[0x4b]	1668	1			T3	1		T4	291		T10	406
valid_sources[0x4c]	1964	1			T3	3		T4	291		T10	401
valid_sources[0x4d]	1748	1			T4	310		T10	441		T14	1
valid_sources[0x4e]	2337	1			T3	1		T4	309		T10	429
valid_sources[0x4f]	2854	1			T4	313		T10	407		T16	3
valid_sources[0x50]	1919	1			T4	315		T10	424		T13	136
valid_sources[0x51]	2704	1			T4	332		T10	396		T11	2
valid_sources[0x52]	2438	1			T4	301		T10	376		T11	3
valid_sources[0x53]	3286	1			T4	310		T10	404		T16	1
valid_sources[0x54]	2269	1			T4	298		T10	429		T14	2
valid_sources[0x55]	2221	1			T3	2		T4	313		T10	407
valid_sources[0x56]	2222	1			T3	1		T4	337		T10	442
valid_sources[0x57]	2195	1			T4	316		T10	412		T15	1
valid_sources[0x58]	2552	1			T4	309		T10	418		T16	2
valid_sources[0x59]	2610	1			T4	284		T10	404		T16	3
valid_sources[0x5a]	2409	1			T4	295		T10	422		T15	3
valid_sources[0x5b]	1689	1			T4	295		T10	414		T16	1
valid_sources[0x5c]	1781	1			T4	289		T10	404		T16	3
valid_sources[0x5d]	1761	1			T3	2		T4	300		T10	391
valid_sources[0x5e]	2043	1			T4	344		T10	364		T16	2
valid_sources[0x5f]	1832	1			T4	333		T10	415		T12	10
valid_sources[0x60]	1979	1			T3	1		T4	315		T10	416
valid_sources[0x61]	2362	1			T4	295		T10	403		T13	130
valid_sources[0x62]	2367	1			T4	317		T10	414		T15	2
valid_sources[0x63]	2964	1			T4	293		T10	423		T113	3
valid_sources[0x64]	2314	1			T4	327		T10	435		T15	1
valid_sources[0x65]	2114	1			T4	304		T10	396		T16	1
valid_sources[0x66]	2237	1			T4	276		T10	434		T16	2
valid_sources[0x67]	1736	1			T4	274		T10	436		T76	1
valid_sources[0x68]	2712	1			T4	295		T10	387		T13	328
valid_sources[0x69]	2479	1			T4	300		T10	410		T16	1
valid_sources[0x6a]	2070	1			T4	308		T10	413		T13	200
valid_sources[0x6b]	2468	1			T4	330		T10	398		T16	1
valid_sources[0x6c]	1963	1			T4	298		T10	367		T16	1
valid_sources[0x6d]	2224	1			T4	311		T10	427		T16	2
valid_sources[0x6e]	1961	1			T4	328		T7	33		T10	384
valid_sources[0x6f]	2521	1			T4	313		T10	403		T16	1
valid_sources[0x70]	1677	1			T3	1		T4	316		T10	411
valid_sources[0x71]	2967	1			T4	296		T10	450		T46	1
valid_sources[0x72]	2397	1			T4	309		T10	434		T15	3
valid_sources[0x73]	2600	1			T3	1		T4	298		T10	427
valid_sources[0x74]	2241	1			T4	340		T10	387		T13	259
valid_sources[0x75]	1650	1			T4	268		T10	379		T16	1
valid_sources[0x76]	1584	1			T3	1		T4	305		T10	398
valid_sources[0x77]	1815	1			T4	315		T10	434		T13	74
valid_sources[0x78]	2375	1			T3	2		T4	297		T10	413
valid_sources[0x79]	2020	1			T4	293		T10	425		T113	2
valid_sources[0x7a]	2524	1			T4	261		T10	421		T16	3
valid_sources[0x7b]	1733	1			T4	336		T10	408		T16	1
valid_sources[0x7c]	2615	1			T4	342		T10	396		T16	1
valid_sources[0x7d]	3091	1			T4	329		T10	438		T15	9
valid_sources[0x7e]	1956	1			T4	314		T10	386		T16	5
valid_sources[0x7f]	3120	1			T3	1		T4	363		T10	407
valid_sources[0x80]	2773	1			T4	290		T10	404		T16	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

135340

1

T1

9

T3

5

T4

19158

values[0x0]

all_enables

biggest_size

198906

1

T4

27995

T10

38188

T13

17437

values[0x1]

all_enables

biggest_size

198316

1

T4

28355

T10

37808

T13

17614

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45686	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

420670

1

T1

8

T2

1

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	120759	1			T1	16		T2	1		T3	32
values[0x0]	160379	1			T4	23283		T6	5		T8	4
values[0x1]	185218	1			T4	27465		T6	3		T8	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	22671	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

443685

1

T1

9

T2

1

T3

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1526	1			T1	3		T4	281		T10	332
valid_sources[0x01]	2157	1			T4	285		T10	326		T16	4
valid_sources[0x02]	2699	1			T4	271		T10	325		T16	1
valid_sources[0x03]	1662	1			T4	236		T10	261		T16	1
valid_sources[0x04]	1668	1			T4	262		T10	278		T113	2
valid_sources[0x05]	1454	1			T4	254		T6	1		T10	324
valid_sources[0x06]	1823	1			T4	258		T10	294		T13	164
valid_sources[0x07]	1833	1			T4	274		T10	366		T16	1
valid_sources[0x08]	1663	1			T4	279		T10	325		T22	1
valid_sources[0x09]	2079	1			T4	291		T10	348		T13	177
valid_sources[0x0a]	1977	1			T3	32		T4	285		T10	346
valid_sources[0x0b]	1970	1			T4	281		T10	334		T13	154
valid_sources[0x0c]	1523	1			T4	243		T10	324		T16	2
valid_sources[0x0d]	2169	1			T4	283		T10	347		T13	187
valid_sources[0x0e]	1700	1			T4	269		T10	347		T16	1
valid_sources[0x0f]	1405	1			T4	260		T10	353		T11	4
valid_sources[0x10]	1688	1			T4	261		T5	1		T10	320
valid_sources[0x11]	1425	1			T4	250		T10	349		T13	172
valid_sources[0x12]	1775	1			T4	272		T10	328		T12	3
valid_sources[0x13]	2087	1			T4	276		T10	293		T11	3
valid_sources[0x14]	1856	1			T4	247		T10	312		T42	1
valid_sources[0x15]	1652	1			T4	236		T10	318		T16	1
valid_sources[0x16]	1585	1			T4	240		T10	343		T13	173
valid_sources[0x17]	1692	1			T4	255		T10	372		T15	1
valid_sources[0x18]	1945	1			T4	289		T10	280		T15	3
valid_sources[0x19]	1452	1			T4	271		T10	319		T75	5
valid_sources[0x1a]	1781	1			T4	280		T10	323		T16	1
valid_sources[0x1b]	1968	1			T4	285		T10	318		T13	159
valid_sources[0x1c]	1428	1			T4	269		T10	308		T13	146
valid_sources[0x1d]	2097	1			T1	6		T4	249		T10	392
valid_sources[0x1e]	2357	1			T4	276		T10	346		T16	2
valid_sources[0x1f]	1832	1			T4	282		T10	329		T13	164
valid_sources[0x20]	1807	1			T4	285		T10	321		T113	3
valid_sources[0x21]	1447	1			T4	262		T10	315		T14	1
valid_sources[0x22]	2115	1			T4	242		T10	280		T15	1
valid_sources[0x23]	1948	1			T4	272		T10	295		T13	170
valid_sources[0x24]	1454	1			T4	260		T10	304		T16	2
valid_sources[0x25]	1727	1			T4	284		T10	296		T16	2
valid_sources[0x26]	1529	1			T4	296		T10	294		T13	183
valid_sources[0x27]	1848	1			T4	282		T10	300		T113	1
valid_sources[0x28]	2306	1			T4	254		T10	318		T13	165
valid_sources[0x29]	1857	1			T4	260		T10	334		T13	151
valid_sources[0x2a]	2032	1			T4	254		T10	303		T13	187
valid_sources[0x2b]	1917	1			T4	267		T10	328		T34	11
valid_sources[0x2c]	2317	1			T4	287		T10	331		T12	3
valid_sources[0x2d]	1396	1			T4	244		T10	340		T13	164
valid_sources[0x2e]	1791	1			T4	260		T10	313		T16	1
valid_sources[0x2f]	1477	1			T4	256		T10	320		T13	153
valid_sources[0x30]	1803	1			T4	289		T10	295		T16	2
valid_sources[0x31]	1750	1			T4	251		T10	307		T16	2
valid_sources[0x32]	1812	1			T4	250		T10	309		T14	1
valid_sources[0x33]	2055	1			T4	246		T10	352		T14	2
valid_sources[0x34]	3093	1			T4	257		T10	329		T16	1
valid_sources[0x35]	1813	1			T4	241		T10	336		T129	4
valid_sources[0x36]	1711	1			T4	271		T10	366		T13	207
valid_sources[0x37]	1863	1			T4	265		T10	287		T16	1
valid_sources[0x38]	1808	1			T4	260		T10	311		T13	134
valid_sources[0x39]	1869	1			T4	274		T10	303		T113	4
valid_sources[0x3a]	1602	1			T4	252		T10	341		T14	1
valid_sources[0x3b]	1658	1			T4	272		T10	280		T18	1
valid_sources[0x3c]	2001	1			T4	266		T10	337		T14	1
valid_sources[0x3d]	1708	1			T4	245		T10	318		T16	2
valid_sources[0x3e]	1398	1			T4	279		T10	333		T15	1
valid_sources[0x3f]	1535	1			T4	274		T10	318		T13	161
valid_sources[0x40]	1560	1			T4	256		T10	314		T13	132
valid_sources[0x41]	1859	1			T4	250		T10	383		T14	1
valid_sources[0x42]	1640	1			T4	265		T10	264		T14	1
valid_sources[0x43]	2415	1			T4	300		T10	313		T18	1
valid_sources[0x44]	1627	1			T4	260		T10	338		T13	155
valid_sources[0x45]	1895	1			T4	289		T10	323		T16	2
valid_sources[0x46]	1892	1			T4	289		T10	312		T16	2
valid_sources[0x47]	1798	1			T4	252		T10	248		T13	165
valid_sources[0x48]	1700	1			T4	220		T10	338		T12	3
valid_sources[0x49]	2130	1			T4	261		T10	345		T113	4
valid_sources[0x4a]	1809	1			T4	272		T10	318		T15	2
valid_sources[0x4b]	1971	1			T4	273		T10	303		T16	3
valid_sources[0x4c]	1943	1			T4	270		T10	318		T75	2
valid_sources[0x4d]	1816	1			T4	273		T10	265		T113	1
valid_sources[0x4e]	1702	1			T4	248		T10	290		T13	154
valid_sources[0x4f]	2133	1			T4	254		T10	302		T113	3
valid_sources[0x50]	1406	1			T4	248		T10	282		T16	1
valid_sources[0x51]	1509	1			T4	268		T10	285		T16	1
valid_sources[0x52]	1544	1			T4	251		T10	307		T16	1
valid_sources[0x53]	2233	1			T4	254		T10	302		T18	1
valid_sources[0x54]	2096	1			T4	284		T10	336		T15	1
valid_sources[0x55]	2202	1			T4	265		T10	310		T13	134
valid_sources[0x56]	2256	1			T4	249		T10	333		T16	1
valid_sources[0x57]	1852	1			T4	251		T10	300		T129	2
valid_sources[0x58]	1479	1			T4	252		T10	314		T75	3
valid_sources[0x59]	1875	1			T4	253		T10	312		T13	161
valid_sources[0x5a]	1974	1			T4	268		T10	338		T18	1
valid_sources[0x5b]	1738	1			T4	284		T10	300		T13	173
valid_sources[0x5c]	1771	1			T4	279		T10	331		T16	2
valid_sources[0x5d]	2244	1			T4	259		T10	372		T16	2
valid_sources[0x5e]	1552	1			T4	259		T10	293		T16	1
valid_sources[0x5f]	1930	1			T4	261		T10	339		T13	153
valid_sources[0x60]	1782	1			T4	271		T10	293		T47	1
valid_sources[0x61]	1839	1			T4	264		T10	326		T13	182
valid_sources[0x62]	1828	1			T4	237		T10	300		T15	1
valid_sources[0x63]	2412	1			T4	266		T10	333		T16	1
valid_sources[0x64]	1710	1			T4	310		T10	367		T13	156
valid_sources[0x65]	1830	1			T4	241		T10	338		T14	2
valid_sources[0x66]	1720	1			T4	248		T10	342		T16	2
valid_sources[0x67]	1261	1			T4	264		T10	339		T11	1
valid_sources[0x68]	1432	1			T4	265		T10	289		T11	2
valid_sources[0x69]	1807	1			T4	275		T10	309		T14	1
valid_sources[0x6a]	1818	1			T4	243		T10	320		T18	1
valid_sources[0x6b]	2219	1			T4	300		T10	260		T13	160
valid_sources[0x6c]	1356	1			T4	250		T9	2		T10	315
valid_sources[0x6d]	2060	1			T4	296		T10	294		T13	171
valid_sources[0x6e]	1511	1			T4	250		T10	320		T16	2
valid_sources[0x6f]	2002	1			T4	268		T10	329		T129	2
valid_sources[0x70]	1581	1			T4	293		T10	284		T16	1
valid_sources[0x71]	1495	1			T4	265		T10	322		T13	159
valid_sources[0x72]	2115	1			T1	2		T4	279		T10	339
valid_sources[0x73]	1803	1			T4	273		T10	285		T12	3
valid_sources[0x74]	1694	1			T4	275		T10	306		T13	151
valid_sources[0x75]	1407	1			T4	250		T10	339		T16	1
valid_sources[0x76]	1949	1			T4	269		T10	302		T35	2
valid_sources[0x77]	1698	1			T4	284		T10	280		T15	2
valid_sources[0x78]	1571	1			T4	248		T10	327		T13	162
valid_sources[0x79]	1663	1			T4	280		T10	349		T13	148
valid_sources[0x7a]	1763	1			T4	259		T10	286		T11	1
valid_sources[0x7b]	1504	1			T4	310		T10	293		T129	1
valid_sources[0x7c]	1595	1			T4	223		T10	309		T13	158
valid_sources[0x7d]	1817	1			T4	263		T10	246		T13	159
valid_sources[0x7e]	1744	1			T4	251		T10	280		T13	169
valid_sources[0x7f]	1730	1			T4	243		T10	306		T13	153
valid_sources[0x80]	1635	1			T4	248		T10	316		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

107142

1

T1

8

T2

1

T3

20

values[0x0]

all_enables

biggest_size

156604

1

T4

22825

T6

2

T8

3

values[0x1]

all_enables

biggest_size

156924

1

T4

23112

T10

27697

T63

1