Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1011676

1

T3

57

T4

142645

T7

249

full_word

623287

1

T1

6

T3

5

T4

88488

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1634683	1			T1	6		T3	62		T4	231133
auto[TlIntgErrCmd]	90	1			T57	5		T59	4		T60	8
auto[TlIntgErrData]	100	1			T57	3		T59	10		T60	4
auto[TlIntgErrBoth]	90	1			T57	2		T59	6		T60	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

275300

1

T1

6

T3

62

T4

37008

auto[1]

1359663

1

T4

194125

T10

254106

T13

121244

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	126607	1			T3	57		T4	15911		T7	249
auto[TlIntgErrNone]	partial	auto[1]	884812	1			T4	126734		T10	163614		T13	79243
auto[TlIntgErrNone]	full_word	auto[0]	148560	1			T1	6		T3	5		T4	21097
auto[TlIntgErrNone]	full_word	auto[1]	474704	1			T4	67391		T10	90492		T13	42001
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T57	2		T59	1		T60	1
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T57	2		T59	3		T60	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T57	1		T60	1		T124	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T125	1		T118	1		T126	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T57	1		T59	5		T60	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T57	1		T59	4		T60	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T57	1		T124	2		T127	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T59	1		T125	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T57	2		T59	1		T60	4
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T59	5		T60	4		T116	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T128	1		T123	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T124	1		T118	2		-	-