Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 46682 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 783644 1 T1 6 T2 15 T3 12



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 230059 1 T1 68 T2 15 T3 12
values[0x0] 294863 1 T11 12774 T12 10532 T13 38182
values[0x1] 305404 1 T11 13159 T12 11127 T13 39806



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 23049 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 807277 1 T1 45 T2 15 T3 12



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3523 1 T5 2 T6 4 T7 1
valid_sources[0x01] 2843 1 T4 9 T6 2 T10 2
valid_sources[0x02] 3572 1 T7 3 T118 1 T103 1
valid_sources[0x03] 2681 1 T70 2 T119 1 T11 139
valid_sources[0x04] 2805 1 T6 1 T7 1 T10 2
valid_sources[0x05] 3497 1 T7 2 T10 2 T120 2
valid_sources[0x06] 2789 1 T4 1 T7 1 T11 146
valid_sources[0x07] 4321 1 T1 1 T7 2 T10 4
valid_sources[0x08] 3173 1 T4 5 T7 2 T70 1
valid_sources[0x09] 3686 1 T1 1 T7 2 T10 3
valid_sources[0x0a] 3167 1 T7 1 T10 4 T120 1
valid_sources[0x0b] 2760 1 T4 3 T7 1 T70 1
valid_sources[0x0c] 3225 1 T10 2 T32 1 T36 1
valid_sources[0x0d] 2839 1 T1 1 T6 4 T7 1
valid_sources[0x0e] 3435 1 T1 1 T7 1 T9 1
valid_sources[0x0f] 2853 1 T1 1 T3 1 T5 2
valid_sources[0x10] 2814 1 T10 1 T120 1 T11 148
valid_sources[0x11] 2698 1 T6 1 T7 1 T10 1
valid_sources[0x12] 3510 1 T5 3 T71 1 T72 1
valid_sources[0x13] 2899 1 T6 2 T7 1 T10 2
valid_sources[0x14] 3974 1 T6 4 T7 2 T10 1
valid_sources[0x15] 4470 1 T4 2 T11 144 T57 3
valid_sources[0x16] 2736 1 T4 2 T6 1 T10 1
valid_sources[0x17] 3114 1 T10 3 T71 1 T119 2
valid_sources[0x18] 3592 1 T1 2 T6 1 T7 1
valid_sources[0x19] 3121 1 T7 1 T10 2 T71 1
valid_sources[0x1a] 3228 1 T1 1 T7 1 T10 2
valid_sources[0x1b] 3714 1 T6 3 T7 1 T10 4
valid_sources[0x1c] 3739 1 T4 5 T7 2 T10 2
valid_sources[0x1d] 2855 1 T1 1 T7 1 T36 9
valid_sources[0x1e] 2731 1 T6 4 T9 3 T10 1
valid_sources[0x1f] 4187 1 T7 2 T15 10 T71 1
valid_sources[0x20] 3461 1 T7 1 T10 1 T120 1
valid_sources[0x21] 3506 1 T9 1 T10 1 T118 1
valid_sources[0x22] 3083 1 T10 3 T120 1 T32 1
valid_sources[0x23] 2895 1 T4 1 T7 1 T70 1
valid_sources[0x24] 3448 1 T7 1 T10 2 T83 3
valid_sources[0x25] 4493 1 T5 3 T10 3 T72 1
valid_sources[0x26] 2773 1 T3 1 T4 1 T6 1
valid_sources[0x27] 3410 1 T9 2 T10 1 T118 1
valid_sources[0x28] 3153 1 T4 1 T7 2 T10 1
valid_sources[0x29] 3000 1 T7 1 T10 1 T71 2
valid_sources[0x2a] 3647 1 T6 1 T10 3 T70 2
valid_sources[0x2b] 3330 1 T6 3 T7 3 T9 4
valid_sources[0x2c] 2723 1 T5 1 T6 3 T7 1
valid_sources[0x2d] 2647 1 T10 1 T119 1 T32 1
valid_sources[0x2e] 3095 1 T10 1 T72 1 T119 1
valid_sources[0x2f] 3375 1 T7 1 T10 4 T71 1
valid_sources[0x30] 4646 1 T7 2 T10 1 T120 1
valid_sources[0x31] 2882 1 T7 1 T70 1 T103 1
valid_sources[0x32] 2770 1 T1 1 T4 1 T7 2
valid_sources[0x33] 2979 1 T7 3 T10 1 T28 1
valid_sources[0x34] 2878 1 T6 1 T7 1 T10 1
valid_sources[0x35] 3825 1 T1 1 T6 1 T7 2
valid_sources[0x36] 3481 1 T3 1 T7 1 T10 3
valid_sources[0x37] 4151 1 T4 2 T5 1 T7 1
valid_sources[0x38] 3048 1 T5 2 T6 2 T7 4
valid_sources[0x39] 2964 1 T7 1 T10 2 T71 1
valid_sources[0x3a] 2744 1 T6 2 T10 1 T70 1
valid_sources[0x3b] 3065 1 T7 1 T10 2 T83 1
valid_sources[0x3c] 3294 1 T7 1 T10 1 T70 1
valid_sources[0x3d] 2851 1 T7 2 T10 2 T71 1
valid_sources[0x3e] 4244 1 T4 1 T7 1 T10 1
valid_sources[0x3f] 2818 1 T7 2 T10 1 T15 36
valid_sources[0x40] 3854 1 T10 2 T103 2 T36 1
valid_sources[0x41] 2846 1 T7 5 T10 1 T83 3
valid_sources[0x42] 3502 1 T4 1 T7 1 T10 1
valid_sources[0x43] 2867 1 T7 2 T10 1 T71 2
valid_sources[0x44] 2762 1 T10 3 T72 1 T32 3
valid_sources[0x45] 3371 1 T4 1 T7 1 T10 2
valid_sources[0x46] 3644 1 T7 3 T10 2 T32 3
valid_sources[0x47] 3710 1 T1 2 T6 8 T7 2
valid_sources[0x48] 2863 1 T7 1 T10 1 T72 1
valid_sources[0x49] 2658 1 T7 3 T10 5 T72 4
valid_sources[0x4a] 3319 1 T32 1 T34 3 T11 156
valid_sources[0x4b] 2782 1 T10 2 T119 1 T32 1
valid_sources[0x4c] 2980 1 T6 2 T7 3 T71 1
valid_sources[0x4d] 2894 1 T7 6 T10 5 T120 3
valid_sources[0x4e] 3131 1 T6 3 T7 2 T103 2
valid_sources[0x4f] 3273 1 T1 2 T7 4 T10 1
valid_sources[0x50] 3537 1 T10 2 T103 2 T120 1
valid_sources[0x51] 2653 1 T1 1 T10 1 T70 1
valid_sources[0x52] 3435 1 T6 1 T7 1 T10 2
valid_sources[0x53] 4115 1 T1 1 T7 1 T10 1
valid_sources[0x54] 3740 1 T10 1 T15 16 T71 1
valid_sources[0x55] 3274 1 T6 1 T7 4 T10 1
valid_sources[0x56] 2751 1 T7 1 T70 1 T72 1
valid_sources[0x57] 2807 1 T10 1 T72 2 T36 2
valid_sources[0x58] 3222 1 T1 1 T7 2 T10 1
valid_sources[0x59] 4183 1 T7 1 T118 1 T11 137
valid_sources[0x5a] 3141 1 T7 1 T10 3 T118 1
valid_sources[0x5b] 2954 1 T4 2 T6 2 T7 1
valid_sources[0x5c] 4564 1 T1 1 T4 3 T7 1
valid_sources[0x5d] 2871 1 T5 1 T7 1 T118 1
valid_sources[0x5e] 3436 1 T4 5 T7 4 T10 1
valid_sources[0x5f] 3817 1 T10 1 T28 1 T32 2
valid_sources[0x60] 4854 1 T10 1 T71 1 T121 3
valid_sources[0x61] 3332 1 T7 1 T10 2 T119 1
valid_sources[0x62] 3036 1 T4 2 T7 1 T10 1
valid_sources[0x63] 3531 1 T10 2 T71 2 T119 2
valid_sources[0x64] 2748 1 T5 2 T119 1 T11 125
valid_sources[0x65] 2955 1 T7 2 T32 3 T11 120
valid_sources[0x66] 4357 1 T1 2 T3 1 T7 1
valid_sources[0x67] 3044 1 T1 1 T6 1 T7 1
valid_sources[0x68] 2873 1 T10 1 T71 1 T72 2
valid_sources[0x69] 2842 1 T6 1 T7 2 T10 3
valid_sources[0x6a] 2691 1 T7 5 T83 14 T32 1
valid_sources[0x6b] 2875 1 T1 1 T4 6 T6 3
valid_sources[0x6c] 5164 1 T7 1 T83 8 T32 1
valid_sources[0x6d] 2878 1 T1 2 T72 1 T34 2
valid_sources[0x6e] 2955 1 T1 1 T4 1 T7 2
valid_sources[0x6f] 2945 1 T6 1 T7 2 T70 1
valid_sources[0x70] 2971 1 T7 2 T10 3 T71 1
valid_sources[0x71] 3457 1 T3 1 T7 2 T10 2
valid_sources[0x72] 3369 1 T5 1 T10 2 T118 2
valid_sources[0x73] 3206 1 T10 1 T71 1 T83 4
valid_sources[0x74] 2977 1 T10 4 T103 1 T28 1
valid_sources[0x75] 3037 1 T70 2 T71 1 T72 1
valid_sources[0x76] 2956 1 T4 1 T5 1 T7 1
valid_sources[0x77] 3477 1 T7 1 T10 5 T70 2
valid_sources[0x78] 2968 1 T5 2 T7 1 T10 1
valid_sources[0x79] 3223 1 T71 1 T118 1 T120 3
valid_sources[0x7a] 2762 1 T1 1 T103 2 T32 1
valid_sources[0x7b] 3860 1 T1 1 T9 7 T71 1
valid_sources[0x7c] 2924 1 T6 4 T7 1 T10 1
valid_sources[0x7d] 2984 1 T7 1 T10 1 T119 1
valid_sources[0x7e] 3352 1 T6 2 T7 1 T10 1
valid_sources[0x7f] 2887 1 T7 4 T10 2 T119 2
valid_sources[0x80] 3831 1 T5 1 T6 2 T7 5



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 199140 1 T1 6 T2 15 T3 12
values[0x0] all_enables biggest_size 292235 1 T11 12661 T12 10430 T13 37852
values[0x1] all_enables biggest_size 292269 1 T11 12586 T12 10598 T13 38090


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 63967 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 598021 1 T1 15 T2 18 T3 13



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 168974 1 T1 32 T2 32 T3 30
values[0x0] 228545 1 T8 3 T21 2 T22 3
values[0x1] 264469 1 T8 2 T21 8 T22 3



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 30482 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 631506 1 T1 20 T2 21 T3 13



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2385 1 T70 2 T39 1 T11 1
valid_sources[0x01] 2351 1 T7 2 T83 1 T11 5
valid_sources[0x02] 2829 1 T10 1 T11 32 T56 1
valid_sources[0x03] 2690 1 T5 1 T11 82 T58 1
valid_sources[0x04] 2933 1 T1 2 T7 1 T10 2
valid_sources[0x05] 2335 1 T7 1 T9 3 T10 1
valid_sources[0x06] 2876 1 T23 2 T11 33 T12 26
valid_sources[0x07] 3111 1 T4 1 T72 1 T11 125
valid_sources[0x08] 2680 1 T72 1 T17 1 T18 1
valid_sources[0x09] 2435 1 T4 1 T83 2 T11 174
valid_sources[0x0a] 2199 1 T72 1 T32 2 T11 8
valid_sources[0x0b] 2289 1 T10 2 T23 1 T120 1
valid_sources[0x0c] 2465 1 T83 1 T11 193 T58 1
valid_sources[0x0d] 2258 1 T120 3 T11 56 T12 22
valid_sources[0x0e] 3323 1 T7 1 T39 1 T11 11
valid_sources[0x0f] 2321 1 T10 1 T11 9 T12 580
valid_sources[0x10] 2308 1 T71 8 T11 69 T84 1
valid_sources[0x11] 3441 1 T3 1 T10 1 T121 7
valid_sources[0x12] 2478 1 T10 2 T70 1 T11 11
valid_sources[0x13] 2079 1 T70 1 T11 16 T54 1
valid_sources[0x14] 2847 1 T10 2 T23 1 T72 1
valid_sources[0x15] 2424 1 T7 16 T9 2 T23 1
valid_sources[0x16] 2808 1 T17 2 T11 257 T12 88
valid_sources[0x17] 2254 1 T3 2 T10 2 T70 1
valid_sources[0x18] 2904 1 T4 1 T10 1 T37 3
valid_sources[0x19] 2205 1 T4 2 T5 1 T7 2
valid_sources[0x1a] 2249 1 T2 32 T3 3 T10 1
valid_sources[0x1b] 3509 1 T1 2 T10 1 T11 305
valid_sources[0x1c] 2595 1 T10 1 T83 1 T11 18
valid_sources[0x1d] 1942 1 T11 4 T12 9 T13 110
valid_sources[0x1e] 2843 1 T5 1 T10 1 T47 2
valid_sources[0x1f] 3648 1 T10 3 T23 1 T11 147
valid_sources[0x20] 2975 1 T20 1 T70 1 T11 15
valid_sources[0x21] 2103 1 T3 1 T37 1 T11 145
valid_sources[0x22] 2857 1 T3 1 T72 1 T122 1
valid_sources[0x23] 3011 1 T67 1 T39 1 T11 7
valid_sources[0x24] 2566 1 T7 6 T10 1 T120 1
valid_sources[0x25] 2462 1 T10 1 T72 1 T40 1
valid_sources[0x26] 2175 1 T8 1 T9 2 T83 1
valid_sources[0x27] 2121 1 T11 12 T12 157 T13 131
valid_sources[0x28] 2270 1 T5 1 T7 1 T23 1
valid_sources[0x29] 2790 1 T7 1 T11 16 T12 59
valid_sources[0x2a] 2238 1 T10 1 T11 79 T12 310
valid_sources[0x2b] 2998 1 T103 10 T120 1 T11 179
valid_sources[0x2c] 2668 1 T10 4 T11 34 T69 1
valid_sources[0x2d] 2302 1 T1 2 T7 1 T23 1
valid_sources[0x2e] 2418 1 T7 1 T23 1 T70 1
valid_sources[0x2f] 2214 1 T7 3 T10 1 T11 8
valid_sources[0x30] 3278 1 T10 1 T71 2 T22 1
valid_sources[0x31] 2597 1 T7 4 T10 1 T11 220
valid_sources[0x32] 1915 1 T7 2 T70 1 T38 2
valid_sources[0x33] 1979 1 T11 7 T123 1 T12 4
valid_sources[0x34] 1856 1 T11 4 T123 1 T12 1
valid_sources[0x35] 2400 1 T10 1 T37 1 T32 10
valid_sources[0x36] 2491 1 T1 3 T10 1 T11 163
valid_sources[0x37] 2377 1 T5 2 T47 1 T11 143
valid_sources[0x38] 2102 1 T10 1 T11 4 T55 1
valid_sources[0x39] 2284 1 T9 1 T40 1 T11 4
valid_sources[0x3a] 2395 1 T1 3 T10 2 T37 1
valid_sources[0x3b] 2953 1 T5 1 T10 2 T11 185
valid_sources[0x3c] 2242 1 T40 1 T11 165 T12 8
valid_sources[0x3d] 2092 1 T5 1 T83 1 T38 1
valid_sources[0x3e] 3406 1 T4 1 T70 1 T72 1
valid_sources[0x3f] 2795 1 T39 1 T11 197 T12 3
valid_sources[0x40] 2916 1 T5 1 T7 1 T10 1
valid_sources[0x41] 2313 1 T11 298 T123 1 T12 9
valid_sources[0x42] 2457 1 T10 1 T11 61 T12 39
valid_sources[0x43] 2039 1 T10 1 T38 1 T11 157
valid_sources[0x44] 2538 1 T10 2 T11 103 T12 35
valid_sources[0x45] 2179 1 T11 231 T12 6 T124 3
valid_sources[0x46] 3992 1 T11 79 T12 131 T124 3
valid_sources[0x47] 2310 1 T7 1 T11 13 T43 3
valid_sources[0x48] 2469 1 T11 73 T43 2 T123 1
valid_sources[0x49] 2871 1 T4 1 T70 1 T67 1
valid_sources[0x4a] 2231 1 T5 1 T11 14 T12 3
valid_sources[0x4b] 2270 1 T39 1 T11 262 T12 14
valid_sources[0x4c] 2472 1 T11 144 T84 2 T12 294
valid_sources[0x4d] 2963 1 T5 1 T11 193 T12 108
valid_sources[0x4e] 2552 1 T7 2 T9 1 T24 1
valid_sources[0x4f] 2617 1 T7 3 T9 1 T10 1
valid_sources[0x50] 2593 1 T83 2 T39 1 T11 89
valid_sources[0x51] 2166 1 T5 1 T10 1 T37 1
valid_sources[0x52] 3145 1 T10 2 T23 1 T11 201
valid_sources[0x53] 2341 1 T4 2 T7 3 T10 2
valid_sources[0x54] 2879 1 T10 2 T21 10 T11 7
valid_sources[0x55] 2006 1 T3 1 T72 1 T120 1
valid_sources[0x56] 1894 1 T71 6 T11 192 T123 2
valid_sources[0x57] 3426 1 T11 7 T12 41 T13 274
valid_sources[0x58] 2658 1 T7 5 T10 4 T11 131
valid_sources[0x59] 2513 1 T10 1 T37 1 T120 1
valid_sources[0x5a] 3263 1 T10 3 T83 1 T11 195
valid_sources[0x5b] 2736 1 T4 1 T11 3 T123 1
valid_sources[0x5c] 2899 1 T4 1 T7 4 T10 1
valid_sources[0x5d] 1930 1 T70 1 T83 2 T11 110
valid_sources[0x5e] 2064 1 T7 1 T83 2 T11 25
valid_sources[0x5f] 2176 1 T37 3 T120 1 T11 143
valid_sources[0x60] 2577 1 T1 1 T4 1 T7 5
valid_sources[0x61] 2480 1 T22 1 T11 87 T12 3
valid_sources[0x62] 2432 1 T3 1 T10 1 T83 1
valid_sources[0x63] 3114 1 T4 1 T72 1 T39 1
valid_sources[0x64] 1957 1 T10 1 T83 2 T11 217
valid_sources[0x65] 2796 1 T10 2 T11 415 T125 1
valid_sources[0x66] 2719 1 T7 6 T121 4 T32 2
valid_sources[0x67] 3238 1 T4 1 T10 1 T23 1
valid_sources[0x68] 2616 1 T83 2 T11 3 T12 310
valid_sources[0x69] 1827 1 T10 1 T83 8 T120 1
valid_sources[0x6a] 2308 1 T10 1 T68 2 T11 278
valid_sources[0x6b] 2458 1 T72 1 T47 1 T11 42
valid_sources[0x6c] 3131 1 T4 1 T70 1 T11 66
valid_sources[0x6d] 2864 1 T1 1 T7 3 T39 1
valid_sources[0x6e] 2289 1 T10 1 T72 1 T18 2
valid_sources[0x6f] 2618 1 T10 2 T37 1 T11 82
valid_sources[0x70] 2250 1 T3 1 T47 1 T11 119
valid_sources[0x71] 2915 1 T5 2 T10 2 T70 1
valid_sources[0x72] 2834 1 T10 2 T11 2 T58 1
valid_sources[0x73] 2547 1 T103 2 T11 75 T84 1
valid_sources[0x74] 3099 1 T5 2 T11 10 T41 1
valid_sources[0x75] 1914 1 T9 2 T83 1 T11 190
valid_sources[0x76] 2634 1 T38 1 T11 115 T12 10
valid_sources[0x77] 2571 1 T4 1 T23 1 T67 1
valid_sources[0x78] 3403 1 T47 1 T38 1 T11 375
valid_sources[0x79] 3291 1 T71 9 T17 3 T11 2
valid_sources[0x7a] 2541 1 T8 1 T11 59 T12 28
valid_sources[0x7b] 3055 1 T7 3 T23 1 T120 1
valid_sources[0x7c] 3032 1 T7 2 T72 1 T18 2
valid_sources[0x7d] 2066 1 T83 1 T11 41 T41 1
valid_sources[0x7e] 2401 1 T7 3 T11 73 T123 1
valid_sources[0x7f] 2398 1 T11 279 T12 106 T13 98
valid_sources[0x80] 3093 1 T9 1 T10 1 T121 11



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 151623 1 T1 15 T2 18 T3 13
values[0x0] all_enables biggest_size 223455 1 T8 2 T22 1 T30 3
values[0x1] all_enables biggest_size 222943 1 T21 2 T67 3 T30 1

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