Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1420609

1

T1

62

T4

62

T5

65

full_word

912786

1

T1

6

T2

10

T3

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2333075	1			T1	68		T2	10		T3	8
auto[TlIntgErrCmd]	97	1			T61	8		T62	3		T63	3
auto[TlIntgErrData]	106	1			T61	6		T62	8		T63	5
auto[TlIntgErrBoth]	117	1			T61	6		T62	9		T63	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

385172

1

T1

68

T2

10

T3

8

auto[1]

1948223

1

T11

84551

T12

74912

T13

252181

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	167059	1			T1	62		T4	62		T5	65
auto[TlIntgErrNone]	partial	auto[1]	1253256	1			T11	54533		T12	49521		T13	162019
auto[TlIntgErrNone]	full_word	auto[0]	217953	1			T1	6		T2	10		T3	8
auto[TlIntgErrNone]	full_word	auto[1]	694807	1			T11	30018		T12	25391		T13	90162
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T61	6		T62	1		T63	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T61	2		T62	2		T63	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T113	1		T114	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T113	1		T111	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T61	3		T62	3		T63	1
auto[TlIntgErrData]	partial	auto[1]	46	1			T61	3		T62	5		T63	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T106	1		T116	1		T117	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T63	1		T108	1		T106	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T61	3		T62	5		T63	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T61	3		T62	2		T63	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T62	1		T108	1		T110	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T62	1		T107	1		T111	1