Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2155766

1

T1

99

T4

362

T5

106

full_word

1371403

1

T1

9

T2

4

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3526849	1			T1	108		T2	4		T3	6
auto[TlIntgErrCmd]	121	1			T61	11		T62	4		T63	9
auto[TlIntgErrData]	99	1			T61	7		T62	3		T63	8
auto[TlIntgErrBoth]	100	1			T61	2		T62	3		T63	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

568848

1

T1

108

T2

4

T3

6

auto[1]

2958321

1

T11

132407

T12

138860

T13

40043

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	243745	1			T1	99		T4	362		T5	106
auto[TlIntgErrNone]	partial	auto[1]	1911727	1			T11	86568		T12	88586		T13	26187
auto[TlIntgErrNone]	full_word	auto[0]	324951	1			T1	9		T2	4		T3	6
auto[TlIntgErrNone]	full_word	auto[1]	1046426	1			T11	45839		T12	50274		T13	13856
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T61	6		T63	4		T112	3
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T61	5		T62	4		T63	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T112	1		T114	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T63	2		T117	1		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1			T61	2		T62	1		T63	4
auto[TlIntgErrData]	partial	auto[1]	44	1			T61	3		T62	2		T63	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T61	1		T110	1		T118	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T61	1		T112	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T61	1		T62	1		T63	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T61	1		T62	1		T63	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T62	1		T63	1		T119	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T116	1		T119	1		T120	1