Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36843	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

491853

1

T2

6

T4

18

T5

34

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	152752	1			T2	6		T4	18		T5	281
values[0x0]	184333	1			T13	7651		T14	21265		T15	12379
values[0x1]	191611	1			T13	7974		T14	22275		T15	12760

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17757	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

510939

1

T2

6

T4

18

T5

172

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2164	1			T16	6		T13	72		T14	280
valid_sources[0x01]	1742	1			T8	4		T13	102		T14	218
valid_sources[0x02]	2213	1			T8	4		T13	68		T14	219
valid_sources[0x03]	1878	1			T20	2		T13	86		T14	297
valid_sources[0x04]	2152	1			T13	68		T17	1		T14	257
valid_sources[0x05]	2041	1			T13	87		T14	159		T102	4
valid_sources[0x06]	2568	1			T20	1		T13	87		T14	229
valid_sources[0x07]	2316	1			T8	1		T13	67		T17	1
valid_sources[0x08]	1691	1			T16	8		T13	75		T17	4
valid_sources[0x09]	1726	1			T12	30		T16	4		T13	85
valid_sources[0x0a]	2765	1			T20	1		T16	6		T13	103
valid_sources[0x0b]	3629	1			T11	49		T20	6		T16	1
valid_sources[0x0c]	2025	1			T6	1		T12	16		T13	83
valid_sources[0x0d]	1811	1			T13	74		T14	266		T19	2
valid_sources[0x0e]	1685	1			T13	101		T14	250		T70	1
valid_sources[0x0f]	1620	1			T20	1		T13	86		T17	4
valid_sources[0x10]	1540	1			T13	74		T14	229		T102	1
valid_sources[0x11]	2110	1			T5	12		T20	6		T13	97
valid_sources[0x12]	2469	1			T20	2		T13	84		T17	1
valid_sources[0x13]	1587	1			T13	63		T14	250		T51	4
valid_sources[0x14]	1623	1			T20	5		T13	72		T17	3
valid_sources[0x15]	1607	1			T16	3		T13	83		T14	258
valid_sources[0x16]	1838	1			T13	83		T14	272		T102	1
valid_sources[0x17]	2382	1			T13	81		T17	1		T14	198
valid_sources[0x18]	1983	1			T20	3		T16	3		T13	82
valid_sources[0x19]	2881	1			T8	5		T13	81		T14	273
valid_sources[0x1a]	2142	1			T8	2		T20	1		T13	80
valid_sources[0x1b]	1776	1			T8	7		T16	1		T13	71
valid_sources[0x1c]	2392	1			T16	9		T13	95		T14	208
valid_sources[0x1d]	1988	1			T20	1		T13	76		T30	3
valid_sources[0x1e]	1516	1			T8	1		T12	17		T13	90
valid_sources[0x1f]	2377	1			T13	92		T14	225		T102	2
valid_sources[0x20]	2083	1			T20	3		T13	87		T14	207
valid_sources[0x21]	1630	1			T16	11		T13	43		T14	236
valid_sources[0x22]	1983	1			T8	4		T20	3		T13	77
valid_sources[0x23]	2210	1			T8	1		T13	84		T14	222
valid_sources[0x24]	2482	1			T16	3		T13	95		T14	263
valid_sources[0x25]	2107	1			T13	78		T14	253		T102	1
valid_sources[0x26]	2838	1			T13	80		T14	223		T72	9
valid_sources[0x27]	1497	1			T13	61		T17	1		T14	251
valid_sources[0x28]	2039	1			T13	69		T14	210		T51	1
valid_sources[0x29]	2495	1			T6	1		T20	1		T13	91
valid_sources[0x2a]	1697	1			T13	73		T14	230		T69	1
valid_sources[0x2b]	2008	1			T20	1		T16	4		T13	74
valid_sources[0x2c]	1758	1			T13	74		T14	207		T50	1
valid_sources[0x2d]	2060	1			T6	1		T8	19		T13	86
valid_sources[0x2e]	2896	1			T13	74		T14	249		T102	1
valid_sources[0x2f]	1872	1			T20	6		T13	108		T14	244
valid_sources[0x30]	1841	1			T20	1		T13	90		T14	200
valid_sources[0x31]	2648	1			T13	93		T14	254		T68	1
valid_sources[0x32]	2344	1			T20	3		T13	84		T14	312
valid_sources[0x33]	1879	1			T20	4		T13	101		T14	188
valid_sources[0x34]	1587	1			T8	3		T20	1		T13	76
valid_sources[0x35]	2421	1			T8	2		T13	82		T17	2
valid_sources[0x36]	1949	1			T20	1		T13	91		T14	293
valid_sources[0x37]	1807	1			T20	1		T13	112		T17	1
valid_sources[0x38]	2428	1			T8	4		T20	1		T13	88
valid_sources[0x39]	2185	1			T13	88		T14	222		T19	1
valid_sources[0x3a]	2293	1			T13	80		T17	11		T14	250
valid_sources[0x3b]	2193	1			T13	98		T14	223		T103	1
valid_sources[0x3c]	1805	1			T20	1		T13	80		T14	200
valid_sources[0x3d]	1944	1			T20	1		T13	64		T14	246
valid_sources[0x3e]	2214	1			T20	2		T13	56		T14	211
valid_sources[0x3f]	3890	1			T11	13		T20	4		T13	84
valid_sources[0x40]	1920	1			T13	91		T14	202		T68	2
valid_sources[0x41]	1930	1			T13	96		T14	279		T68	3
valid_sources[0x42]	2154	1			T13	103		T14	206		T102	2
valid_sources[0x43]	1795	1			T13	100		T14	197		T70	2
valid_sources[0x44]	1830	1			T8	3		T20	5		T13	85
valid_sources[0x45]	1948	1			T13	87		T14	247		T51	1
valid_sources[0x46]	1654	1			T8	22		T20	1		T13	84
valid_sources[0x47]	2258	1			T13	92		T14	234		T102	1
valid_sources[0x48]	1907	1			T20	1		T13	88		T17	1
valid_sources[0x49]	1945	1			T20	2		T13	79		T14	259
valid_sources[0x4a]	1613	1			T13	85		T14	222		T69	2
valid_sources[0x4b]	1536	1			T20	4		T13	84		T14	272
valid_sources[0x4c]	2015	1			T8	3		T13	104		T14	206
valid_sources[0x4d]	2421	1			T11	19		T16	1		T13	86
valid_sources[0x4e]	2897	1			T20	12		T13	66		T14	264
valid_sources[0x4f]	1855	1			T13	74		T14	217		T102	2
valid_sources[0x50]	1736	1			T13	87		T14	253		T69	1
valid_sources[0x51]	3032	1			T13	106		T17	10		T14	258
valid_sources[0x52]	1762	1			T16	1		T13	104		T14	226
valid_sources[0x53]	2440	1			T16	2		T13	55		T17	1
valid_sources[0x54]	2431	1			T20	1		T13	94		T14	253
valid_sources[0x55]	1689	1			T20	4		T13	105		T14	216
valid_sources[0x56]	1546	1			T20	7		T13	85		T14	227
valid_sources[0x57]	1568	1			T20	8		T13	69		T14	195
valid_sources[0x58]	1532	1			T13	76		T14	192		T102	2
valid_sources[0x59]	1769	1			T20	2		T13	65		T17	3
valid_sources[0x5a]	1729	1			T20	6		T16	2		T13	68
valid_sources[0x5b]	2063	1			T13	105		T14	227		T102	3
valid_sources[0x5c]	1618	1			T8	2		T12	27		T13	108
valid_sources[0x5d]	1596	1			T5	22		T20	6		T16	2
valid_sources[0x5e]	1483	1			T13	85		T14	225		T102	2
valid_sources[0x5f]	1562	1			T20	2		T16	2		T13	73
valid_sources[0x60]	3244	1			T20	9		T16	9		T13	70
valid_sources[0x61]	2141	1			T20	2		T13	85		T14	225
valid_sources[0x62]	3049	1			T13	86		T17	1		T14	204
valid_sources[0x63]	1736	1			T20	1		T13	73		T14	254
valid_sources[0x64]	2144	1			T13	84		T14	205		T19	7
valid_sources[0x65]	1819	1			T20	1		T13	60		T17	1
valid_sources[0x66]	1895	1			T13	64		T14	231		T102	1
valid_sources[0x67]	2937	1			T20	3		T13	79		T14	246
valid_sources[0x68]	2929	1			T13	90		T17	1		T14	185
valid_sources[0x69]	1952	1			T13	93		T14	227		T72	5
valid_sources[0x6a]	2231	1			T5	11		T13	83		T14	186
valid_sources[0x6b]	2333	1			T20	6		T13	78		T14	219
valid_sources[0x6c]	2221	1			T20	2		T16	1		T13	84
valid_sources[0x6d]	1590	1			T11	25		T20	6		T13	70
valid_sources[0x6e]	1590	1			T13	77		T14	253		T73	2
valid_sources[0x6f]	1584	1			T20	3		T13	82		T14	206
valid_sources[0x70]	1816	1			T20	5		T13	64		T14	238
valid_sources[0x71]	1640	1			T8	5		T13	85		T14	236
valid_sources[0x72]	2408	1			T8	1		T16	7		T13	70
valid_sources[0x73]	1938	1			T13	84		T17	2		T14	209
valid_sources[0x74]	1750	1			T8	1		T20	6		T13	82
valid_sources[0x75]	2223	1			T20	16		T16	2		T13	81
valid_sources[0x76]	2772	1			T16	3		T13	79		T14	207
valid_sources[0x77]	1547	1			T16	14		T13	74		T14	193
valid_sources[0x78]	2686	1			T11	12		T13	77		T14	232
valid_sources[0x79]	1788	1			T13	67		T14	189		T69	1
valid_sources[0x7a]	2233	1			T8	2		T11	37		T13	73
valid_sources[0x7b]	1592	1			T13	72		T17	6		T14	237
valid_sources[0x7c]	1551	1			T13	77		T17	10		T14	254
valid_sources[0x7d]	2309	1			T20	4		T13	79		T14	198
valid_sources[0x7e]	1610	1			T20	2		T13	95		T14	246
valid_sources[0x7f]	1774	1			T8	2		T13	79		T14	207
valid_sources[0x80]	1603	1			T20	2		T13	68		T14	221

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

125943

1

T2

6

T4

18

T5

34

values[0x0]

all_enables

biggest_size

182714

1

T13

7570

T14

21126

T15

12271

values[0x1]

all_enables

biggest_size

183196

1

T13

7547

T14

21412

T15

12153

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41161	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

388228

1

T1

1

T2

9

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	111140	1			T1	1		T2	18		T3	1
values[0x0]	147892	1			T7	3		T24	6		T25	3
values[0x1]	170357	1			T7	7		T24	3		T25	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20208	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

409181

1

T1

1

T2

9

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1498	1			T13	69		T14	158		T104	1
valid_sources[0x01]	1650	1			T16	1		T13	58		T14	166
valid_sources[0x02]	1639	1			T13	66		T14	147		T104	2
valid_sources[0x03]	1794	1			T24	1		T13	56		T14	174
valid_sources[0x04]	1534	1			T6	1		T29	1		T13	54
valid_sources[0x05]	1778	1			T13	83		T14	144		T104	2
valid_sources[0x06]	1657	1			T16	3		T13	73		T14	222
valid_sources[0x07]	1662	1			T13	58		T14	207		T104	1
valid_sources[0x08]	1674	1			T13	80		T14	164		T105	1
valid_sources[0x09]	1640	1			T13	69		T14	186		T31	1
valid_sources[0x0a]	1561	1			T13	66		T14	145		T32	2
valid_sources[0x0b]	1475	1			T13	69		T17	2		T14	198
valid_sources[0x0c]	1563	1			T13	65		T14	176		T73	2
valid_sources[0x0d]	1659	1			T13	79		T14	163		T35	1
valid_sources[0x0e]	1659	1			T13	62		T14	227		T106	1
valid_sources[0x0f]	1668	1			T13	85		T14	154		T50	3
valid_sources[0x10]	1577	1			T6	1		T13	77		T14	201
valid_sources[0x11]	1820	1			T16	2		T13	75		T14	196
valid_sources[0x12]	1649	1			T13	52		T14	174		T105	1
valid_sources[0x13]	1771	1			T13	70		T14	171		T104	1
valid_sources[0x14]	1731	1			T29	1		T13	47		T14	161
valid_sources[0x15]	1647	1			T13	74		T14	217		T69	64
valid_sources[0x16]	1782	1			T13	93		T14	154		T107	1
valid_sources[0x17]	1525	1			T13	61		T14	149		T108	4
valid_sources[0x18]	1587	1			T13	77		T14	138		T109	1
valid_sources[0x19]	1640	1			T13	66		T14	164		T110	1
valid_sources[0x1a]	1592	1			T16	3		T13	75		T14	149
valid_sources[0x1b]	1710	1			T13	72		T14	188		T111	1
valid_sources[0x1c]	1690	1			T13	64		T14	201		T73	1
valid_sources[0x1d]	1511	1			T16	1		T13	74		T14	205
valid_sources[0x1e]	1861	1			T16	2		T13	63		T14	198
valid_sources[0x1f]	1642	1			T13	79		T17	1		T14	178
valid_sources[0x20]	1570	1			T13	56		T14	149		T70	4
valid_sources[0x21]	1804	1			T6	2		T16	3		T13	72
valid_sources[0x22]	1670	1			T13	71		T14	146		T73	1
valid_sources[0x23]	1615	1			T16	2		T13	71		T14	232
valid_sources[0x24]	1595	1			T28	4		T13	69		T17	2
valid_sources[0x25]	1638	1			T13	83		T14	200		T105	2
valid_sources[0x26]	1560	1			T6	1		T13	66		T17	2
valid_sources[0x27]	1682	1			T13	82		T14	223		T112	1
valid_sources[0x28]	1609	1			T13	80		T14	152		T109	1
valid_sources[0x29]	1793	1			T4	26		T13	75		T14	214
valid_sources[0x2a]	1498	1			T13	69		T14	159		T113	1
valid_sources[0x2b]	1651	1			T13	65		T14	182		T70	4
valid_sources[0x2c]	1653	1			T13	79		T14	178		T73	3
valid_sources[0x2d]	1515	1			T13	53		T14	157		T104	1
valid_sources[0x2e]	1783	1			T16	2		T13	76		T14	196
valid_sources[0x2f]	1693	1			T13	72		T14	249		T72	2
valid_sources[0x30]	1709	1			T13	61		T14	235		T104	1
valid_sources[0x31]	1623	1			T29	1		T13	73		T17	2
valid_sources[0x32]	1667	1			T13	71		T14	221		T32	1
valid_sources[0x33]	1727	1			T16	2		T28	3		T13	68
valid_sources[0x34]	1712	1			T13	62		T17	9		T14	178
valid_sources[0x35]	1614	1			T29	1		T13	60		T14	156
valid_sources[0x36]	1674	1			T13	61		T14	170		T32	1
valid_sources[0x37]	1560	1			T13	64		T14	151		T51	1
valid_sources[0x38]	1826	1			T28	1		T13	86		T14	196
valid_sources[0x39]	1840	1			T13	72		T14	189		T108	2
valid_sources[0x3a]	1629	1			T13	82		T14	172		T104	2
valid_sources[0x3b]	1758	1			T13	65		T48	8		T14	226
valid_sources[0x3c]	1687	1			T13	66		T14	172		T104	2
valid_sources[0x3d]	1777	1			T24	1		T13	61		T14	135
valid_sources[0x3e]	1734	1			T13	63		T14	187		T104	1
valid_sources[0x3f]	1689	1			T16	3		T13	60		T14	204
valid_sources[0x40]	1591	1			T16	3		T13	62		T14	199
valid_sources[0x41]	1626	1			T13	55		T17	11		T14	154
valid_sources[0x42]	1789	1			T13	62		T14	192		T31	1
valid_sources[0x43]	1732	1			T13	66		T36	1		T14	166
valid_sources[0x44]	1822	1			T13	67		T14	152		T104	2
valid_sources[0x45]	1745	1			T13	63		T14	197		T108	2
valid_sources[0x46]	1571	1			T13	70		T14	185		T33	1
valid_sources[0x47]	1611	1			T13	72		T14	149		T32	1
valid_sources[0x48]	1489	1			T29	1		T13	81		T14	172
valid_sources[0x49]	1715	1			T6	1		T13	79		T14	189
valid_sources[0x4a]	1619	1			T13	52		T14	195		T32	2
valid_sources[0x4b]	1760	1			T16	5		T29	1		T13	64
valid_sources[0x4c]	1829	1			T13	62		T14	187		T73	6
valid_sources[0x4d]	1835	1			T13	63		T14	184		T51	4
valid_sources[0x4e]	1688	1			T13	79		T14	208		T50	1
valid_sources[0x4f]	1839	1			T13	75		T17	2		T14	189
valid_sources[0x50]	1786	1			T13	71		T14	218		T72	7
valid_sources[0x51]	1691	1			T16	2		T13	81		T14	165
valid_sources[0x52]	1569	1			T13	72		T17	2		T14	186
valid_sources[0x53]	1698	1			T13	52		T14	209		T114	1
valid_sources[0x54]	1657	1			T9	26		T13	55		T14	160
valid_sources[0x55]	1829	1			T13	78		T14	190		T107	1
valid_sources[0x56]	1779	1			T21	20		T29	1		T13	64
valid_sources[0x57]	1938	1			T13	62		T14	169		T107	1
valid_sources[0x58]	1512	1			T13	59		T17	7		T14	195
valid_sources[0x59]	1571	1			T13	77		T14	147		T109	2
valid_sources[0x5a]	1636	1			T9	6		T13	66		T14	139
valid_sources[0x5b]	1717	1			T13	76		T14	202		T51	4
valid_sources[0x5c]	1814	1			T1	1		T13	71		T17	1
valid_sources[0x5d]	1642	1			T13	63		T14	150		T104	1
valid_sources[0x5e]	1570	1			T13	64		T14	199		T50	1
valid_sources[0x5f]	1671	1			T16	5		T13	67		T14	207
valid_sources[0x60]	1644	1			T13	74		T14	169		T108	4
valid_sources[0x61]	1639	1			T6	1		T13	100		T49	1
valid_sources[0x62]	1634	1			T13	59		T14	196		T104	1
valid_sources[0x63]	1611	1			T13	71		T14	143		T70	1
valid_sources[0x64]	1713	1			T13	78		T14	177		T104	2
valid_sources[0x65]	1619	1			T13	59		T14	184		T104	1
valid_sources[0x66]	1804	1			T9	12		T13	68		T14	172
valid_sources[0x67]	1686	1			T2	10		T13	77		T14	169
valid_sources[0x68]	1661	1			T24	3		T13	71		T14	174
valid_sources[0x69]	1503	1			T16	2		T13	85		T14	175
valid_sources[0x6a]	1632	1			T13	88		T14	184		T109	1
valid_sources[0x6b]	1663	1			T29	1		T13	55		T14	149
valid_sources[0x6c]	1528	1			T16	3		T29	1		T13	72
valid_sources[0x6d]	1721	1			T13	90		T14	182		T50	1
valid_sources[0x6e]	1794	1			T16	4		T13	70		T14	178
valid_sources[0x6f]	1595	1			T13	64		T14	181		T115	32
valid_sources[0x70]	1630	1			T16	3		T13	65		T14	157
valid_sources[0x71]	1505	1			T13	60		T14	189		T104	1
valid_sources[0x72]	1431	1			T13	55		T14	166		T113	3
valid_sources[0x73]	1655	1			T13	56		T14	221		T107	1
valid_sources[0x74]	1710	1			T16	8		T13	60		T17	2
valid_sources[0x75]	1764	1			T13	59		T14	189		T104	1
valid_sources[0x76]	1629	1			T13	75		T17	3		T14	185
valid_sources[0x77]	1674	1			T13	71		T14	180		T104	3
valid_sources[0x78]	1813	1			T13	83		T14	222		T33	1
valid_sources[0x79]	1808	1			T13	72		T14	156		T109	1
valid_sources[0x7a]	1703	1			T13	52		T14	191		T70	1
valid_sources[0x7b]	1500	1			T29	2		T13	67		T17	1
valid_sources[0x7c]	1593	1			T13	43		T14	181		T71	1
valid_sources[0x7d]	1758	1			T13	81		T14	235		T73	2
valid_sources[0x7e]	1607	1			T6	1		T13	66		T14	176
valid_sources[0x7f]	1550	1			T13	79		T14	204		T57	4
valid_sources[0x80]	1773	1			T13	76		T14	149		T106	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

98744

1

T1

1

T2

9

T3

1

values[0x0]

all_enables

biggest_size

144503

1

T7

1

T24

2

T28

4

values[0x1]

all_enables

biggest_size

144981

1

T24

1

T29

4

T13

6156