Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

893611

1

T5

247

T8

204

T11

264

full_word

571315

1

T2

4

T4

12

T5

34

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1464636	1			T2	4		T4	12		T5	281
auto[TlIntgErrCmd]	98	1			T52	8		T53	3		T54	4
auto[TlIntgErrData]	94	1			T52	1		T53	4		T54	2
auto[TlIntgErrBoth]	98	1			T52	1		T53	13		T54	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

248601

1

T2

4

T4

12

T5

281

auto[1]

1216325

1

T13

54908

T14

134646

T15

82259

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	111047	1			T5	247		T8	204		T11	264
auto[TlIntgErrNone]	partial	auto[1]	782295	1			T13	36726		T14	84753		T15	53219
auto[TlIntgErrNone]	full_word	auto[0]	137421	1			T2	4		T4	12		T5	34
auto[TlIntgErrNone]	full_word	auto[1]	433873	1			T13	18182		T14	49893		T15	29040
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T52	1		T53	1		T54	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T52	7		T53	2		T90	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T90	1		T93	1		T99	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T100	1		T101	1		-	-
auto[TlIntgErrData]	partial	auto[0]	40	1			T53	3		T54	1		T90	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T52	1		T53	1		T54	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T90	1		T93	1		T91	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T91	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T52	1		T53	5		T54	2
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T53	8		T54	2		T90	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T97	2		T93	1		T98	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T90	1		T97	1		T101	1