Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 53086 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1130348 1 T1 7 T2 22 T5 25



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 315666 1 T1 61 T2 198 T5 229
values[0x0] 425733 1 T12 16238 T13 61817 T14 87241
values[0x1] 442035 1 T12 16787 T13 64247 T14 89807



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 26754 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1156680 1 T1 41 T2 108 T5 147



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3808 1 T5 1 T9 2 T27 1
valid_sources[0x01] 4817 1 T5 1 T9 1 T10 3
valid_sources[0x02] 3925 1 T5 1 T131 39 T132 3
valid_sources[0x03] 4949 1 T2 12 T9 4 T10 1
valid_sources[0x04] 4212 1 T9 3 T133 1 T16 1
valid_sources[0x05] 4610 1 T5 2 T9 2 T27 2
valid_sources[0x06] 4377 1 T2 1 T19 1 T113 3
valid_sources[0x07] 4563 1 T5 1 T7 1 T9 1
valid_sources[0x08] 4691 1 T1 2 T2 1 T19 1
valid_sources[0x09] 6050 1 T1 1 T5 3 T10 1
valid_sources[0x0a] 4651 1 T2 1 T5 1 T10 2
valid_sources[0x0b] 5981 1 T1 1 T27 2 T134 1
valid_sources[0x0c] 3904 1 T7 4 T27 1 T135 4
valid_sources[0x0d] 5729 1 T10 7 T16 10 T136 16
valid_sources[0x0e] 4236 1 T1 1 T9 1 T19 1
valid_sources[0x0f] 4181 1 T2 2 T9 1 T10 1
valid_sources[0x10] 4260 1 T9 2 T18 1 T19 1
valid_sources[0x11] 4019 1 T9 2 T113 2 T134 2
valid_sources[0x12] 4538 1 T2 3 T5 2 T9 1
valid_sources[0x13] 4740 1 T1 1 T10 2 T19 2
valid_sources[0x14] 5129 1 T9 1 T46 4 T27 1
valid_sources[0x15] 3938 1 T27 2 T134 1 T16 1
valid_sources[0x16] 3964 1 T5 8 T7 2 T9 1
valid_sources[0x17] 4546 1 T2 2 T19 1 T27 1
valid_sources[0x18] 4112 1 T19 2 T46 2 T134 2
valid_sources[0x19] 3854 1 T9 2 T19 3 T134 2
valid_sources[0x1a] 4591 1 T9 1 T19 1 T27 3
valid_sources[0x1b] 4817 1 T5 2 T10 3 T18 2
valid_sources[0x1c] 3907 1 T9 3 T113 2 T137 1
valid_sources[0x1d] 4343 1 T7 9 T9 1 T19 2
valid_sources[0x1e] 4664 1 T10 3 T18 1 T19 2
valid_sources[0x1f] 4141 1 T2 12 T9 2 T10 6
valid_sources[0x20] 4984 1 T9 4 T46 1 T113 4
valid_sources[0x21] 5147 1 T9 3 T46 2 T27 1
valid_sources[0x22] 4676 1 T10 1 T19 1 T133 1
valid_sources[0x23] 4368 1 T18 2 T19 1 T113 9
valid_sources[0x24] 4664 1 T1 1 T5 4 T19 1
valid_sources[0x25] 4366 1 T9 1 T10 2 T134 1
valid_sources[0x26] 4169 1 T27 1 T134 2 T69 2
valid_sources[0x27] 4893 1 T5 2 T10 1 T134 1
valid_sources[0x28] 3753 1 T1 2 T2 1 T9 1
valid_sources[0x29] 3901 1 T9 4 T39 2 T134 1
valid_sources[0x2a] 3827 1 T9 2 T19 1 T46 1
valid_sources[0x2b] 4331 1 T5 6 T9 1 T19 1
valid_sources[0x2c] 5941 1 T2 3 T91 5 T132 1
valid_sources[0x2d] 4003 1 T2 2 T5 2 T46 1
valid_sources[0x2e] 4231 1 T19 1 T27 4 T134 4
valid_sources[0x2f] 4931 1 T5 1 T7 4 T19 1
valid_sources[0x30] 4772 1 T1 1 T9 1 T10 1
valid_sources[0x31] 4002 1 T10 1 T18 1 T132 2
valid_sources[0x32] 4220 1 T1 1 T9 3 T27 4
valid_sources[0x33] 6462 1 T5 1 T7 1 T10 2
valid_sources[0x34] 4257 1 T2 1 T5 6 T19 2
valid_sources[0x35] 4724 1 T2 1 T5 1 T46 5
valid_sources[0x36] 4951 1 T5 2 T9 1 T19 1
valid_sources[0x37] 5667 1 T9 1 T27 2 T134 1
valid_sources[0x38] 4425 1 T1 1 T18 1 T19 1
valid_sources[0x39] 4213 1 T133 1 T132 3 T138 2
valid_sources[0x3a] 4833 1 T1 1 T9 1 T133 2
valid_sources[0x3b] 4132 1 T9 1 T27 1 T132 2
valid_sources[0x3c] 4648 1 T9 1 T18 1 T19 1
valid_sources[0x3d] 5268 1 T9 1 T10 2 T27 1
valid_sources[0x3e] 4337 1 T7 2 T9 2 T18 1
valid_sources[0x3f] 5055 1 T10 3 T19 1 T113 2
valid_sources[0x40] 4341 1 T1 1 T2 2 T27 2
valid_sources[0x41] 4222 1 T9 2 T10 2 T18 1
valid_sources[0x42] 4137 1 T1 1 T5 3 T9 1
valid_sources[0x43] 3753 1 T9 3 T10 1 T132 2
valid_sources[0x44] 4705 1 T2 2 T5 1 T9 1
valid_sources[0x45] 4107 1 T1 1 T10 3 T113 5
valid_sources[0x46] 5130 1 T5 3 T7 4 T9 2
valid_sources[0x47] 5973 1 T1 1 T5 1 T7 2
valid_sources[0x48] 4005 1 T5 2 T9 2 T18 1
valid_sources[0x49] 4633 1 T2 2 T18 1 T19 1
valid_sources[0x4a] 4106 1 T5 2 T7 3 T9 1
valid_sources[0x4b] 5739 1 T9 3 T10 7 T27 1
valid_sources[0x4c] 4452 1 T2 1 T7 1 T9 1
valid_sources[0x4d] 5904 1 T1 1 T7 1 T9 2
valid_sources[0x4e] 5951 1 T2 2 T131 12 T134 1
valid_sources[0x4f] 4556 1 T1 2 T2 2 T9 1
valid_sources[0x50] 3987 1 T9 1 T19 1 T134 1
valid_sources[0x51] 3880 1 T2 3 T9 1 T19 1
valid_sources[0x52] 4164 1 T5 1 T7 3 T9 1
valid_sources[0x53] 5215 1 T9 1 T16 2 T132 1
valid_sources[0x54] 5077 1 T2 1 T139 49 T140 3
valid_sources[0x55] 4165 1 T5 1 T9 1 T134 3
valid_sources[0x56] 3864 1 T5 5 T9 1 T10 1
valid_sources[0x57] 5172 1 T1 1 T2 2 T5 6
valid_sources[0x58] 5600 1 T1 2 T19 1 T113 4
valid_sources[0x59] 4884 1 T27 1 T113 5 T134 1
valid_sources[0x5a] 4621 1 T9 3 T46 2 T113 7
valid_sources[0x5b] 5970 1 T1 1 T46 6 T113 6
valid_sources[0x5c] 4276 1 T7 1 T18 1 T46 5
valid_sources[0x5d] 3858 1 T1 1 T9 4 T27 1
valid_sources[0x5e] 4525 1 T2 7 T5 1 T9 1
valid_sources[0x5f] 4794 1 T1 1 T2 3 T5 3
valid_sources[0x60] 4309 1 T5 4 T18 1 T19 1
valid_sources[0x61] 4486 1 T7 3 T9 4 T27 1
valid_sources[0x62] 5222 1 T1 1 T2 1 T19 2
valid_sources[0x63] 5979 1 T5 1 T9 2 T19 1
valid_sources[0x64] 4625 1 T5 3 T9 1 T137 25
valid_sources[0x65] 5068 1 T9 1 T19 2 T113 1
valid_sources[0x66] 4104 1 T2 7 T5 4 T9 1
valid_sources[0x67] 4175 1 T9 1 T46 13 T113 5
valid_sources[0x68] 4677 1 T1 1 T9 3 T10 2
valid_sources[0x69] 5560 1 T1 1 T2 3 T5 4
valid_sources[0x6a] 5818 1 T9 1 T10 1 T18 1
valid_sources[0x6b] 4639 1 T135 6 T138 3 T140 2
valid_sources[0x6c] 3878 1 T9 2 T27 1 T134 3
valid_sources[0x6d] 4996 1 T9 1 T19 1 T132 4
valid_sources[0x6e] 4281 1 T10 4 T18 1 T69 1
valid_sources[0x6f] 5248 1 T5 1 T9 2 T46 2
valid_sources[0x70] 3988 1 T5 3 T9 2 T46 1
valid_sources[0x71] 4545 1 T9 2 T10 2 T134 2
valid_sources[0x72] 3686 1 T19 2 T27 2 T113 1
valid_sources[0x73] 4414 1 T5 1 T113 5 T132 2
valid_sources[0x74] 3864 1 T9 2 T19 1 T113 3
valid_sources[0x75] 4072 1 T9 1 T46 1 T27 2
valid_sources[0x76] 4321 1 T9 3 T27 1 T113 2
valid_sources[0x77] 3724 1 T9 2 T27 1 T134 1
valid_sources[0x78] 4822 1 T46 9 T134 1 T91 8
valid_sources[0x79] 4498 1 T1 1 T2 3 T9 4
valid_sources[0x7a] 4901 1 T9 1 T18 2 T134 1
valid_sources[0x7b] 4527 1 T2 6 T9 1 T10 1
valid_sources[0x7c] 5158 1 T9 2 T27 4 T113 9
valid_sources[0x7d] 5157 1 T113 2 T136 45 T132 1
valid_sources[0x7e] 3943 1 T1 1 T9 3 T19 4
valid_sources[0x7f] 3988 1 T19 1 T113 7 T134 2
valid_sources[0x80] 4520 1 T9 2 T27 3 T132 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 285720 1 T1 7 T2 22 T5 25
values[0x0] all_enables biggest_size 422024 1 T12 16096 T13 61297 T14 86497
values[0x1] all_enables biggest_size 422604 1 T12 16004 T13 61574 T14 85890


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 87299 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 875209 1 T1 13 T2 49 T4 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 240762 1 T1 32 T2 96 T6 37
values[0x0] 335292 1 T3 2 T4 2 T26 4
values[0x1] 386454 1 T3 2 T4 3 T26 3



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 40116 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 922392 1 T1 18 T2 60 T3 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 4161 1 T9 1 T77 1 T141 1
valid_sources[0x01] 3592 1 T142 1 T143 1 T12 99
valid_sources[0x02] 4368 1 T9 1 T27 1 T91 1
valid_sources[0x03] 3251 1 T91 2 T43 3 T144 4
valid_sources[0x04] 3575 1 T9 2 T91 1 T145 1
valid_sources[0x05] 4233 1 T91 1 T78 1 T12 141
valid_sources[0x06] 3994 1 T90 4 T91 1 T44 2
valid_sources[0x07] 4231 1 T4 1 T27 2 T91 1
valid_sources[0x08] 4102 1 T9 2 T146 1 T144 4
valid_sources[0x09] 3839 1 T9 1 T141 1 T145 1
valid_sources[0x0a] 4145 1 T9 1 T77 1 T139 2
valid_sources[0x0b] 4109 1 T7 64 T27 1 T28 1
valid_sources[0x0c] 3605 1 T9 1 T91 1 T16 13
valid_sources[0x0d] 4174 1 T141 1 T12 156 T63 1
valid_sources[0x0e] 4168 1 T9 1 T78 1 T147 1
valid_sources[0x0f] 3997 1 T27 3 T69 1 T91 1
valid_sources[0x10] 3791 1 T9 6 T78 1 T12 140
valid_sources[0x11] 3813 1 T9 2 T79 2 T12 131
valid_sources[0x12] 3649 1 T27 1 T148 5 T149 1
valid_sources[0x13] 3695 1 T27 1 T150 2 T146 1
valid_sources[0x14] 3660 1 T91 1 T17 1 T78 1
valid_sources[0x15] 3554 1 T91 2 T142 1 T12 140
valid_sources[0x16] 3846 1 T6 37 T89 2 T91 3
valid_sources[0x17] 4021 1 T151 1 T138 1 T152 2
valid_sources[0x18] 3892 1 T3 1 T9 1 T17 1
valid_sources[0x19] 3798 1 T145 1 T153 4 T12 195
valid_sources[0x1a] 4603 1 T9 2 T27 2 T91 1
valid_sources[0x1b] 3587 1 T27 3 T44 3 T154 1
valid_sources[0x1c] 4442 1 T17 1 T138 5 T146 1
valid_sources[0x1d] 3648 1 T9 1 T91 1 T151 1
valid_sources[0x1e] 3563 1 T9 2 T138 1 T141 3
valid_sources[0x1f] 3791 1 T9 1 T146 1 T143 1
valid_sources[0x20] 3778 1 T9 1 T138 5 T155 2
valid_sources[0x21] 3230 1 T73 1 T155 2 T146 2
valid_sources[0x22] 4236 1 T91 1 T17 1 T44 1
valid_sources[0x23] 3773 1 T47 1 T151 1 T145 1
valid_sources[0x24] 4023 1 T9 1 T151 1 T138 2
valid_sources[0x25] 3859 1 T27 2 T44 1 T139 2
valid_sources[0x26] 4134 1 T73 1 T91 1 T16 5
valid_sources[0x27] 3522 1 T91 2 T77 1 T149 2
valid_sources[0x28] 3992 1 T9 1 T75 4 T151 1
valid_sources[0x29] 3684 1 T27 1 T141 1 T144 1
valid_sources[0x2a] 3626 1 T9 1 T142 1 T151 3
valid_sources[0x2b] 3564 1 T73 1 T91 1 T156 1
valid_sources[0x2c] 3586 1 T145 2 T143 1 T12 155
valid_sources[0x2d] 3578 1 T4 1 T27 2 T147 1
valid_sources[0x2e] 3741 1 T44 1 T78 1 T145 1
valid_sources[0x2f] 4342 1 T9 1 T91 1 T138 1
valid_sources[0x30] 3896 1 T77 1 T151 1 T12 146
valid_sources[0x31] 4142 1 T9 1 T91 1 T151 1
valid_sources[0x32] 3728 1 T9 1 T91 1 T139 2
valid_sources[0x33] 3747 1 T1 10 T9 1 T91 2
valid_sources[0x34] 3767 1 T27 3 T50 4 T151 1
valid_sources[0x35] 3924 1 T39 5 T141 3 T144 1
valid_sources[0x36] 3419 1 T9 1 T90 1 T29 1
valid_sources[0x37] 3652 1 T91 1 T12 152 T157 1
valid_sources[0x38] 3330 1 T44 1 T138 1 T145 1
valid_sources[0x39] 3752 1 T91 2 T158 3 T159 1
valid_sources[0x3a] 4087 1 T91 1 T17 1 T145 1
valid_sources[0x3b] 3471 1 T27 3 T89 1 T73 1
valid_sources[0x3c] 3725 1 T9 1 T151 1 T12 130
valid_sources[0x3d] 3531 1 T17 1 T158 4 T160 1
valid_sources[0x3e] 3754 1 T89 16 T91 1 T145 1
valid_sources[0x3f] 3092 1 T73 1 T91 1 T142 1
valid_sources[0x40] 3507 1 T27 3 T73 1 T145 2
valid_sources[0x41] 3890 1 T17 1 T50 1 T151 1
valid_sources[0x42] 3386 1 T9 1 T41 2 T91 1
valid_sources[0x43] 3627 1 T91 2 T12 92 T161 1
valid_sources[0x44] 3599 1 T50 4 T155 1 T143 1
valid_sources[0x45] 3405 1 T9 1 T44 1 T148 2
valid_sources[0x46] 3721 1 T27 3 T74 4 T91 1
valid_sources[0x47] 3869 1 T17 1 T12 135 T63 2
valid_sources[0x48] 3698 1 T91 2 T78 1 T139 2
valid_sources[0x49] 4074 1 T73 1 T90 1 T91 1
valid_sources[0x4a] 4055 1 T9 1 T90 3 T91 1
valid_sources[0x4b] 3671 1 T151 2 T155 2 T162 1
valid_sources[0x4c] 4005 1 T78 1 T145 1 T150 1
valid_sources[0x4d] 3569 1 T141 1 T155 1 T146 1
valid_sources[0x4e] 3957 1 T9 1 T90 1 T41 1
valid_sources[0x4f] 3410 1 T9 1 T74 1 T91 3
valid_sources[0x50] 3313 1 T9 3 T21 4 T91 3
valid_sources[0x51] 3552 1 T91 2 T150 1 T143 1
valid_sources[0x52] 4069 1 T27 2 T163 3 T149 1
valid_sources[0x53] 3539 1 T151 2 T141 1 T164 3
valid_sources[0x54] 3701 1 T91 3 T158 1 T151 1
valid_sources[0x55] 3598 1 T3 1 T9 1 T91 3
valid_sources[0x56] 3246 1 T9 1 T27 2 T89 2
valid_sources[0x57] 3852 1 T9 1 T139 2 T138 4
valid_sources[0x58] 4304 1 T149 4 T12 189 T60 1
valid_sources[0x59] 3661 1 T78 1 T145 1 T155 1
valid_sources[0x5a] 4381 1 T18 32 T145 1 T165 3
valid_sources[0x5b] 3747 1 T91 1 T17 1 T148 10
valid_sources[0x5c] 3645 1 T77 1 T142 1 T139 2
valid_sources[0x5d] 3314 1 T69 4 T12 130 T13 530
valid_sources[0x5e] 4022 1 T9 1 T91 1 T145 1
valid_sources[0x5f] 3649 1 T9 1 T91 1 T151 2
valid_sources[0x60] 3861 1 T145 1 T146 1 T12 176
valid_sources[0x61] 3749 1 T91 2 T151 1 T145 1
valid_sources[0x62] 3668 1 T4 1 T41 2 T43 1
valid_sources[0x63] 3846 1 T43 2 T44 1 T166 1
valid_sources[0x64] 3952 1 T41 2 T91 1 T50 5
valid_sources[0x65] 4346 1 T9 3 T91 3 T16 9
valid_sources[0x66] 4165 1 T142 1 T151 3 T159 2
valid_sources[0x67] 4459 1 T9 1 T17 1 T151 1
valid_sources[0x68] 3986 1 T74 1 T91 1 T17 1
valid_sources[0x69] 3626 1 T158 1 T150 2 T12 98
valid_sources[0x6a] 3943 1 T41 1 T91 1 T17 1
valid_sources[0x6b] 4558 1 T69 3 T12 133 T13 517
valid_sources[0x6c] 3936 1 T91 1 T145 1 T146 1
valid_sources[0x6d] 3336 1 T25 1 T39 4 T73 1
valid_sources[0x6e] 3423 1 T9 1 T39 2 T69 3
valid_sources[0x6f] 3544 1 T3 1 T39 6 T78 1
valid_sources[0x70] 3408 1 T141 1 T145 1 T149 1
valid_sources[0x71] 3723 1 T9 2 T73 1 T44 1
valid_sources[0x72] 3865 1 T9 2 T91 2 T142 1
valid_sources[0x73] 3540 1 T41 3 T50 1 T43 4
valid_sources[0x74] 3934 1 T91 2 T145 1 T155 1
valid_sources[0x75] 3776 1 T1 16 T27 1 T91 1
valid_sources[0x76] 4020 1 T90 2 T69 2 T162 4
valid_sources[0x77] 3999 1 T9 3 T27 1 T142 1
valid_sources[0x78] 4098 1 T145 1 T143 1 T12 111
valid_sources[0x79] 3785 1 T9 2 T44 1 T141 1
valid_sources[0x7a] 3795 1 T9 1 T91 1 T44 1
valid_sources[0x7b] 3597 1 T1 2 T9 1 T12 118
valid_sources[0x7c] 4300 1 T9 2 T74 1 T78 1
valid_sources[0x7d] 3759 1 T43 5 T77 1 T139 3
valid_sources[0x7e] 3685 1 T27 4 T160 2 T138 6
valid_sources[0x7f] 3755 1 T9 2 T75 1 T91 1
valid_sources[0x80] 3744 1 T17 1 T77 1 T146 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 220326 1 T1 13 T2 49 T6 18
values[0x0] all_enables biggest_size 328096 1 T26 2 T73 3 T76 1
values[0x1] all_enables biggest_size 326787 1 T4 1 T74 2 T77 1

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