Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2065351

1

T1

54

T2

176

T5

204

full_word

1319134

1

T1

7

T2

22

T5

25

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3384185	1			T1	61		T2	198		T5	229
auto[TlIntgErrCmd]	98	1			T66	5		T67	5		T68	6
auto[TlIntgErrData]	97	1			T66	3		T67	5		T68	10
auto[TlIntgErrBoth]	105	1			T66	2		T67	10		T68	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

545653

1

T1

61

T2

198

T5

229

auto[1]

2838832

1

T12

107434

T13

403251

T14

584242

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	232287	1			T1	54		T2	176		T5	204
auto[TlIntgErrNone]	partial	auto[1]	1832786	1			T12	69333		T13	257499		T14	378666
auto[TlIntgErrNone]	full_word	auto[0]	313238	1			T1	7		T2	22		T5	25
auto[TlIntgErrNone]	full_word	auto[1]	1005874	1			T12	38101		T13	145752		T14	205576
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T66	2		T68	1		T116	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T66	3		T67	4		T68	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T68	1		T116	1		T126	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T67	1		T127	1		T121	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T66	1		T67	2		T68	6
auto[TlIntgErrData]	partial	auto[1]	47	1			T66	1		T67	3		T68	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T66	1		T122	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T126	1		T125	1		T128	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T66	1		T67	3		T68	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T66	1		T67	7		T68	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T126	1		T118	1		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T122	1		T125	1		T129	1