SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
87.50 | 87.50 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
rom_ctrl_tlul_cg | 87.50 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
87.50 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 1 | 7 | 87.50 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_regs_req_check | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
cp_rom_invalid_condition | 2 | 1 | 1 | 50.00 | 100 | 1 | 1 | 0 | |
cp_rom_req_check | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
req_after_done | 501286 | 1 | T3 | 96 | T4 | 96 | T6 | 32 | ||||
req_and_done | 6 | 1 | T83 | 1 | T95 | 1 | T92 | 1 | ||||
req_before_done | 11 | 1 | T66 | 2 | T98 | 1 | T75 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
check_invalid | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
check_valid | 339845698 | 1 | T1 | 59972 | T2 | 343542 | T3 | 153905 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
req_after_done | 485716 | 1 | T3 | 194 | T4 | 157 | T5 | 6 | ||||
req_and_done | 63 | 1 | T5 | 1 | T6 | 1 | T11 | 1 | ||||
req_before_done | 240 | 1 | T3 | 3 | T4 | 1 | T6 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |