Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

957099

1

T3

193

T4

156

T5

235

full_word

607080

1

T3

26

T4

15

T5

13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1563909	1			T3	219		T4	171		T5	248
auto[TlIntgErrCmd]	97	1			T57	9		T60	6		T62	7
auto[TlIntgErrData]	100	1			T57	6		T60	1		T62	5
auto[TlIntgErrBoth]	73	1			T57	5		T60	3		T62	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

261678

1

T3

219

T4

171

T5

248

auto[1]

1302501

1

T9

112367

T12

639052

T13

197979

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	116656	1			T3	193		T4	156		T5	235
auto[TlIntgErrNone]	partial	auto[1]	840198	1			T9	75481		T12	412944		T13	126923
auto[TlIntgErrNone]	full_word	auto[0]	144906	1			T3	26		T4	15		T5	13
auto[TlIntgErrNone]	full_word	auto[1]	462149	1			T9	36886		T12	226108		T13	71056
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T57	3		T60	3		T62	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T57	5		T60	3		T62	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T109	1		T110	1		T111	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T57	1		T62	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T57	2		T113	1		T109	1
auto[TlIntgErrData]	partial	auto[1]	53	1			T57	4		T62	3		T113	4
auto[TlIntgErrData]	full_word	auto[0]	9	1			T60	1		T62	2		T114	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T115	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T57	1		T60	1		T62	3
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T57	4		T60	2		T62	5
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T116	1		T112	1		T117	1