Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52780	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1052844

1

T1

10

T2

10

T4

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	296356	1			T1	91		T2	155		T4	6
values[0x0]	397898	1			T16	53738		T17	65061		T18	59906
values[0x1]	411370	1			T16	55271		T17	67074		T18	62088

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26700	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1078924

1

T1

57

T2

89

T4

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4142	1			T6	2		T8	1		T22	1
valid_sources[0x01]	4373	1			T22	1		T21	2		T119	2
valid_sources[0x02]	4241	1			T8	3		T22	3		T21	2
valid_sources[0x03]	4209	1			T2	4		T6	9		T8	2
valid_sources[0x04]	4455	1			T21	1		T119	1		T120	1
valid_sources[0x05]	4257	1			T9	1		T120	1		T121	1
valid_sources[0x06]	4332	1			T6	3		T8	4		T10	16
valid_sources[0x07]	4379	1			T8	3		T122	1		T123	10
valid_sources[0x08]	4208	1			T22	2		T122	1		T124	3
valid_sources[0x09]	4267	1			T2	17		T6	2		T8	3
valid_sources[0x0a]	4393	1			T8	2		T21	1		T125	23
valid_sources[0x0b]	4251	1			T21	2		T126	8		T122	4
valid_sources[0x0c]	4269	1			T6	2		T8	1		T21	1
valid_sources[0x0d]	4356	1			T22	5		T21	1		T119	1
valid_sources[0x0e]	4439	1			T6	4		T8	1		T22	1
valid_sources[0x0f]	4394	1			T8	4		T127	1		T16	599
valid_sources[0x10]	4395	1			T8	1		T21	2		T119	2
valid_sources[0x11]	4540	1			T8	1		T22	1		T104	75
valid_sources[0x12]	4427	1			T2	4		T8	1		T22	1
valid_sources[0x13]	4343	1			T6	4		T8	2		T21	2
valid_sources[0x14]	3982	1			T6	1		T8	1		T20	1
valid_sources[0x15]	4487	1			T6	2		T8	2		T21	2
valid_sources[0x16]	4269	1			T8	1		T119	1		T121	1
valid_sources[0x17]	4309	1			T8	3		T120	1		T128	1
valid_sources[0x18]	4313	1			T2	5		T120	1		T16	557
valid_sources[0x19]	4538	1			T6	1		T8	4		T119	1
valid_sources[0x1a]	4238	1			T2	4		T8	1		T22	1
valid_sources[0x1b]	4175	1			T105	3		T119	2		T80	4
valid_sources[0x1c]	4272	1			T6	3		T8	1		T20	1
valid_sources[0x1d]	4729	1			T105	4		T129	2		T119	3
valid_sources[0x1e]	4261	1			T6	6		T14	33		T21	4
valid_sources[0x1f]	4186	1			T8	2		T22	1		T129	7
valid_sources[0x20]	4275	1			T6	5		T22	1		T21	2
valid_sources[0x21]	4349	1			T8	2		T22	1		T120	1
valid_sources[0x22]	4207	1			T8	1		T22	1		T119	2
valid_sources[0x23]	4246	1			T21	2		T119	6		T126	52
valid_sources[0x24]	4183	1			T8	2		T20	2		T21	1
valid_sources[0x25]	4251	1			T8	1		T22	1		T21	1
valid_sources[0x26]	4120	1			T8	2		T9	1		T22	1
valid_sources[0x27]	4385	1			T21	1		T36	2		T119	2
valid_sources[0x28]	4473	1			T6	8		T20	3		T21	1
valid_sources[0x29]	4404	1			T8	1		T22	1		T13	2
valid_sources[0x2a]	4359	1			T9	4		T21	2		T122	3
valid_sources[0x2b]	4331	1			T8	1		T21	1		T119	2
valid_sources[0x2c]	4253	1			T8	1		T21	3		T119	1
valid_sources[0x2d]	4297	1			T22	1		T21	1		T119	2
valid_sources[0x2e]	4027	1			T6	4		T8	1		T22	2
valid_sources[0x2f]	4314	1			T6	3		T22	1		T120	2
valid_sources[0x30]	4216	1			T8	1		T21	1		T119	1
valid_sources[0x31]	4368	1			T2	4		T13	2		T21	1
valid_sources[0x32]	4431	1			T8	1		T105	1		T21	2
valid_sources[0x33]	4351	1			T6	2		T21	2		T119	2
valid_sources[0x34]	4142	1			T6	3		T8	1		T129	7
valid_sources[0x35]	4323	1			T6	1		T22	1		T20	4
valid_sources[0x36]	4156	1			T2	4		T6	1		T22	2
valid_sources[0x37]	4249	1			T8	1		T21	5		T130	56
valid_sources[0x38]	4321	1			T6	2		T8	1		T22	2
valid_sources[0x39]	4427	1			T22	1		T105	3		T21	1
valid_sources[0x3a]	4137	1			T2	6		T8	2		T22	1
valid_sources[0x3b]	4456	1			T2	1		T8	1		T9	1
valid_sources[0x3c]	4325	1			T8	2		T21	1		T119	2
valid_sources[0x3d]	4393	1			T6	1		T13	6		T105	3
valid_sources[0x3e]	4255	1			T6	2		T8	2		T22	2
valid_sources[0x3f]	4501	1			T6	4		T22	1		T21	1
valid_sources[0x40]	4349	1			T8	2		T22	1		T119	2
valid_sources[0x41]	4365	1			T8	2		T119	3		T131	75
valid_sources[0x42]	4330	1			T8	1		T22	1		T21	1
valid_sources[0x43]	4374	1			T6	1		T119	2		T126	1
valid_sources[0x44]	4092	1			T6	1		T119	2		T120	3
valid_sources[0x45]	4221	1			T8	2		T22	1		T21	1
valid_sources[0x46]	4081	1			T8	1		T21	1		T119	2
valid_sources[0x47]	4401	1			T6	16		T11	3		T22	1
valid_sources[0x48]	4319	1			T8	2		T21	1		T119	2
valid_sources[0x49]	4424	1			T21	2		T119	1		T120	4
valid_sources[0x4a]	4404	1			T6	3		T8	3		T119	1
valid_sources[0x4b]	4310	1			T22	1		T119	1		T120	2
valid_sources[0x4c]	4316	1			T8	4		T22	1		T21	1
valid_sources[0x4d]	4157	1			T21	1		T120	4		T121	1
valid_sources[0x4e]	4434	1			T6	1		T8	1		T21	1
valid_sources[0x4f]	4447	1			T6	9		T11	1		T21	1
valid_sources[0x50]	4221	1			T2	12		T6	2		T22	3
valid_sources[0x51]	4387	1			T8	4		T22	2		T105	2
valid_sources[0x52]	4385	1			T6	2		T8	1		T22	1
valid_sources[0x53]	4347	1			T20	3		T105	1		T119	1
valid_sources[0x54]	4317	1			T8	3		T21	1		T120	2
valid_sources[0x55]	4202	1			T6	2		T8	2		T104	23
valid_sources[0x56]	4389	1			T8	3		T32	1		T43	1
valid_sources[0x57]	4538	1			T8	1		T21	1		T120	1
valid_sources[0x58]	4265	1			T6	5		T8	1		T21	1
valid_sources[0x59]	4164	1			T6	4		T8	2		T119	2
valid_sources[0x5a]	4287	1			T8	1		T43	2		T21	2
valid_sources[0x5b]	4308	1			T6	2		T21	1		T119	2
valid_sources[0x5c]	4483	1			T8	1		T22	1		T119	1
valid_sources[0x5d]	4262	1			T6	2		T8	2		T21	1
valid_sources[0x5e]	4219	1			T2	2		T8	1		T13	1
valid_sources[0x5f]	4229	1			T8	1		T22	1		T120	6
valid_sources[0x60]	4278	1			T6	2		T8	1		T13	1
valid_sources[0x61]	4315	1			T2	3		T8	1		T22	2
valid_sources[0x62]	4066	1			T8	1		T119	2		T122	1
valid_sources[0x63]	4267	1			T22	1		T13	1		T21	1
valid_sources[0x64]	4327	1			T2	7		T6	3		T8	1
valid_sources[0x65]	4324	1			T6	2		T13	3		T32	1
valid_sources[0x66]	4375	1			T8	3		T21	1		T129	2
valid_sources[0x67]	4430	1			T6	3		T8	2		T22	3
valid_sources[0x68]	4255	1			T8	1		T32	1		T21	1
valid_sources[0x69]	4522	1			T21	1		T120	2		T122	4
valid_sources[0x6a]	4457	1			T20	2		T119	1		T120	1
valid_sources[0x6b]	4242	1			T22	1		T119	1		T122	1
valid_sources[0x6c]	4307	1			T13	2		T119	4		T120	1
valid_sources[0x6d]	4320	1			T6	5		T8	1		T22	1
valid_sources[0x6e]	4375	1			T20	1		T119	3		T120	1
valid_sources[0x6f]	4485	1			T6	6		T22	1		T13	2
valid_sources[0x70]	4398	1			T21	2		T120	2		T122	9
valid_sources[0x71]	4333	1			T8	1		T119	4		T132	1
valid_sources[0x72]	4241	1			T8	1		T20	5		T32	1
valid_sources[0x73]	4165	1			T6	1		T8	2		T22	2
valid_sources[0x74]	4267	1			T22	2		T20	5		T128	1
valid_sources[0x75]	4272	1			T8	2		T20	6		T21	1
valid_sources[0x76]	4407	1			T8	3		T105	1		T120	2
valid_sources[0x77]	4404	1			T21	2		T119	3		T122	1
valid_sources[0x78]	4402	1			T6	1		T13	7		T21	1
valid_sources[0x79]	4373	1			T6	3		T8	3		T21	3
valid_sources[0x7a]	4475	1			T6	2		T11	9		T22	2
valid_sources[0x7b]	4319	1			T8	1		T21	1		T125	17
valid_sources[0x7c]	4249	1			T6	5		T8	1		T22	1
valid_sources[0x7d]	4208	1			T6	2		T10	10		T21	2
valid_sources[0x7e]	4287	1			T2	1		T119	3		T132	3
valid_sources[0x7f]	4288	1			T21	2		T119	4		T80	3
valid_sources[0x80]	4387	1			T8	1		T21	1		T119	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

265328

1

T1

10

T2

10

T4

6

values[0x0]

all_enables

biggest_size

394371

1

T16

53245

T17

64491

T18

59398

values[0x1]

all_enables

biggest_size

393145

1

T16

52729

T17

64164

T18

59311

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	82449	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

796686

1

T1

15

T3

1

T4

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	221973	1			T1	32		T3	1		T4	26
values[0x0]	304760	1			T5	4		T7	6		T26	6
values[0x1]	352402	1			T5	3		T7	3		T26	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38510	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

840625

1

T1

18

T3

1

T4

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4016	1			T64	1		T21	1		T16	526
valid_sources[0x01]	2521	1			T64	1		T21	1		T16	90
valid_sources[0x02]	2840	1			T8	1		T21	2		T16	168
valid_sources[0x03]	2884	1			T11	1		T23	3		T21	2
valid_sources[0x04]	3943	1			T8	2		T105	1		T21	3
valid_sources[0x05]	3278	1			T5	1		T11	1		T26	3
valid_sources[0x06]	2614	1			T8	1		T105	3		T80	4
valid_sources[0x07]	3111	1			T8	1		T11	1		T32	27
valid_sources[0x08]	3407	1			T11	1		T77	1		T79	1
valid_sources[0x09]	3620	1			T129	1		T16	616		T55	7
valid_sources[0x0a]	3587	1			T15	1		T121	2		T16	306
valid_sources[0x0b]	2942	1			T20	1		T33	1		T79	4
valid_sources[0x0c]	3105	1			T33	2		T130	1		T79	1
valid_sources[0x0d]	4024	1			T11	1		T22	1		T23	2
valid_sources[0x0e]	2876	1			T8	1		T129	2		T130	1
valid_sources[0x0f]	3821	1			T13	1		T128	1		T77	1
valid_sources[0x10]	2791	1			T8	1		T21	2		T129	1
valid_sources[0x11]	3671	1			T21	1		T130	1		T133	3
valid_sources[0x12]	4207	1			T8	2		T21	1		T77	1
valid_sources[0x13]	4028	1			T1	1		T9	1		T21	1
valid_sources[0x14]	3595	1			T22	2		T129	3		T16	388
valid_sources[0x15]	2548	1			T8	1		T22	2		T13	1
valid_sources[0x16]	3795	1			T16	379		T17	528		T18	879
valid_sources[0x17]	4418	1			T80	1		T16	709		T17	527
valid_sources[0x18]	3358	1			T9	1		T11	1		T16	428
valid_sources[0x19]	3381	1			T8	1		T11	1		T64	1
valid_sources[0x1a]	3836	1			T8	2		T21	1		T130	1
valid_sources[0x1b]	3123	1			T8	1		T43	5		T16	208
valid_sources[0x1c]	2993	1			T130	1		T128	1		T16	469
valid_sources[0x1d]	3306	1			T13	1		T20	1		T43	1
valid_sources[0x1e]	3755	1			T23	1		T130	2		T121	3
valid_sources[0x1f]	3915	1			T8	1		T9	2		T21	1
valid_sources[0x20]	3249	1			T128	1		T80	22		T133	7
valid_sources[0x21]	3356	1			T129	2		T121	2		T128	1
valid_sources[0x22]	3381	1			T16	466		T17	552		T18	695
valid_sources[0x23]	3699	1			T8	1		T20	1		T77	1
valid_sources[0x24]	3658	1			T1	7		T22	2		T20	1
valid_sources[0x25]	3875	1			T8	1		T21	1		T130	1
valid_sources[0x26]	2887	1			T13	1		T65	6		T80	3
valid_sources[0x27]	3212	1			T13	1		T30	1		T129	1
valid_sources[0x28]	3396	1			T13	1		T79	4		T16	756
valid_sources[0x29]	3073	1			T133	3		T16	591		T17	525
valid_sources[0x2a]	3639	1			T9	1		T130	1		T16	711
valid_sources[0x2b]	3811	1			T8	1		T129	2		T134	1
valid_sources[0x2c]	2694	1			T8	2		T13	1		T130	1
valid_sources[0x2d]	3704	1			T8	1		T129	1		T81	1
valid_sources[0x2e]	4054	1			T128	1		T16	477		T17	561
valid_sources[0x2f]	2816	1			T22	1		T129	3		T79	1
valid_sources[0x30]	4375	1			T8	3		T21	1		T129	2
valid_sources[0x31]	4159	1			T5	1		T8	1		T130	1
valid_sources[0x32]	3214	1			T22	1		T33	1		T21	1
valid_sources[0x33]	4178	1			T20	1		T21	1		T77	1
valid_sources[0x34]	3713	1			T22	1		T23	4		T64	1
valid_sources[0x35]	3343	1			T8	1		T64	2		T129	2
valid_sources[0x36]	3592	1			T8	1		T135	1		T130	1
valid_sources[0x37]	4156	1			T26	4		T22	1		T13	2
valid_sources[0x38]	3252	1			T5	1		T8	2		T22	2
valid_sources[0x39]	3511	1			T21	1		T16	583		T17	539
valid_sources[0x3a]	3486	1			T11	1		T13	1		T16	326
valid_sources[0x3b]	3848	1			T8	1		T16	644		T51	1
valid_sources[0x3c]	3255	1			T8	1		T36	1		T121	1
valid_sources[0x3d]	4258	1			T8	1		T11	1		T22	1
valid_sources[0x3e]	3457	1			T16	505		T17	533		T136	1
valid_sources[0x3f]	3546	1			T137	1		T16	274		T17	534
valid_sources[0x40]	3292	1			T8	5		T21	1		T79	5
valid_sources[0x41]	3296	1			T8	2		T80	4		T16	211
valid_sources[0x42]	3086	1			T11	1		T43	2		T21	1
valid_sources[0x43]	3390	1			T8	1		T20	1		T79	3
valid_sources[0x44]	3182	1			T16	326		T17	548		T18	635
valid_sources[0x45]	2798	1			T8	1		T13	1		T105	1
valid_sources[0x46]	3401	1			T8	2		T129	1		T16	612
valid_sources[0x47]	3037	1			T8	1		T21	2		T129	5
valid_sources[0x48]	3505	1			T11	2		T20	1		T21	1
valid_sources[0x49]	3474	1			T129	1		T16	182		T17	557
valid_sources[0x4a]	2758	1			T128	1		T81	1		T16	142
valid_sources[0x4b]	3469	1			T1	4		T16	461		T17	560
valid_sources[0x4c]	2941	1			T8	1		T66	1		T80	1
valid_sources[0x4d]	2793	1			T8	1		T37	5		T16	140
valid_sources[0x4e]	2645	1			T22	1		T130	1		T81	1
valid_sources[0x4f]	3393	1			T16	524		T17	562		T18	268
valid_sources[0x50]	3608	1			T21	1		T129	1		T16	927
valid_sources[0x51]	2905	1			T3	1		T13	1		T20	2
valid_sources[0x52]	3222	1			T129	1		T121	1		T16	78
valid_sources[0x53]	3703	1			T16	662		T55	1		T17	591
valid_sources[0x54]	3134	1			T8	2		T22	2		T128	1
valid_sources[0x55]	3324	1			T20	1		T43	4		T133	1
valid_sources[0x56]	2711	1			T33	1		T21	1		T16	189
valid_sources[0x57]	3490	1			T1	2		T20	1		T128	1
valid_sources[0x58]	3276	1			T11	1		T21	1		T81	1
valid_sources[0x59]	4068	1			T33	1		T129	1		T16	542
valid_sources[0x5a]	3859	1			T4	7		T11	1		T129	1
valid_sources[0x5b]	3228	1			T22	1		T36	2		T16	443
valid_sources[0x5c]	3742	1			T20	1		T21	1		T16	908
valid_sources[0x5d]	3223	1			T21	1		T81	1		T16	201
valid_sources[0x5e]	3631	1			T21	1		T130	1		T77	1
valid_sources[0x5f]	3859	1			T128	1		T77	2		T16	559
valid_sources[0x60]	4036	1			T105	1		T66	1		T16	8
valid_sources[0x61]	2982	1			T22	1		T16	156		T17	542
valid_sources[0x62]	4152	1			T8	1		T13	1		T20	1
valid_sources[0x63]	3927	1			T8	1		T16	1046		T55	2
valid_sources[0x64]	2825	1			T8	1		T66	1		T129	3
valid_sources[0x65]	3617	1			T8	2		T130	1		T16	642
valid_sources[0x66]	4051	1			T4	4		T20	1		T105	4
valid_sources[0x67]	3221	1			T21	1		T41	1		T77	1
valid_sources[0x68]	3549	1			T8	4		T43	6		T80	2
valid_sources[0x69]	2830	1			T9	1		T129	2		T130	1
valid_sources[0x6a]	3940	1			T22	1		T67	1		T16	476
valid_sources[0x6b]	4208	1			T21	6		T66	1		T128	2
valid_sources[0x6c]	4212	1			T16	720		T17	515		T138	1
valid_sources[0x6d]	3271	1			T21	2		T129	2		T128	1
valid_sources[0x6e]	4264	1			T12	20		T20	1		T21	1
valid_sources[0x6f]	2810	1			T8	2		T27	1		T21	2
valid_sources[0x70]	3616	1			T11	1		T64	1		T65	1
valid_sources[0x71]	3527	1			T23	1		T34	26		T77	1
valid_sources[0x72]	3991	1			T8	1		T16	698		T17	566
valid_sources[0x73]	3275	1			T8	1		T36	1		T128	1
valid_sources[0x74]	3004	1			T8	1		T16	402		T17	595
valid_sources[0x75]	3633	1			T23	3		T16	335		T51	1
valid_sources[0x76]	3832	1			T5	1		T77	1		T133	1
valid_sources[0x77]	3375	1			T22	1		T21	1		T41	1
valid_sources[0x78]	2866	1			T21	1		T130	1		T16	325
valid_sources[0x79]	3839	1			T16	985		T55	1		T17	546
valid_sources[0x7a]	3562	1			T11	1		T36	2		T80	2
valid_sources[0x7b]	3571	1			T33	2		T21	1		T130	1
valid_sources[0x7c]	2894	1			T22	1		T129	4		T80	4
valid_sources[0x7d]	3081	1			T8	2		T21	1		T133	1
valid_sources[0x7e]	3606	1			T8	1		T64	2		T130	1
valid_sources[0x7f]	3264	1			T8	1		T13	2		T128	1
valid_sources[0x80]	3781	1			T128	1		T77	1		T16	980

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

201341

1

T1

15

T3

1

T4

12

values[0x0]

all_enables

biggest_size

297881

1

T5

1

T7

3

T26

1

values[0x1]

all_enables

biggest_size

297464

1

T7

1

T26

2

T64

1