Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1925090

1

T1

81

T2

145

T6

241

full_word

1227649

1

T1

10

T2

10

T4

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3152399	1			T1	91		T2	155		T4	4
auto[TlIntgErrCmd]	105	1			T58	8		T59	2		T60	5
auto[TlIntgErrData]	105	1			T58	4		T59	9		T60	6
auto[TlIntgErrBoth]	130	1			T58	8		T59	9		T60	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

508518

1

T1

91

T2

155

T4

4

auto[1]

2644221

1

T16

357417

T17

421494

T18

399672

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	217773	1			T1	81		T2	145		T6	241
auto[TlIntgErrNone]	partial	auto[1]	1707000	1			T16	231310		T17	269348		T18	258217
auto[TlIntgErrNone]	full_word	auto[0]	290585	1			T1	10		T2	10		T4	4
auto[TlIntgErrNone]	full_word	auto[1]	937041	1			T16	126107		T17	152146		T18	141455
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T58	4		T59	1		T60	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T58	4		T59	1		T60	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T111	1		T113	1		T114	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T108	2		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	52	1			T59	5		T60	4		T115	5
auto[TlIntgErrData]	partial	auto[1]	46	1			T58	2		T59	4		T60	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T112	1		T113	2		T116	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T58	2		T117	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T58	2		T59	4		T60	4
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T58	4		T59	4		T60	5
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T58	1		T59	1		T115	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T58	1		T109	1		T118	1