Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 46836 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 856835 1 T2 24 T3 19 T4 27



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 245371 1 T2 242 T3 211 T4 243
values[0x0] 323610 1 T12 25477 T13 24105 T14 35002
values[0x1] 334690 1 T12 26294 T13 24723 T14 36446



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 23481 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 880190 1 T2 149 T3 129 T4 152



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2829 1 T3 4 T18 4 T19 1
valid_sources[0x01] 3405 1 T2 3 T4 2 T10 4
valid_sources[0x02] 2817 1 T3 1 T10 1 T18 1
valid_sources[0x03] 2503 1 T4 1 T10 4 T18 3
valid_sources[0x04] 3171 1 T2 1 T9 23 T10 1
valid_sources[0x05] 2948 1 T2 9 T10 2 T11 4
valid_sources[0x06] 3667 1 T2 3 T19 2 T99 1
valid_sources[0x07] 2757 1 T2 1 T3 3 T12 248
valid_sources[0x08] 3275 1 T4 1 T19 1 T117 1
valid_sources[0x09] 2895 1 T10 5 T19 4 T99 1
valid_sources[0x0a] 3237 1 T2 9 T4 1 T12 284
valid_sources[0x0b] 3455 1 T3 3 T4 3 T10 1
valid_sources[0x0c] 3060 1 T3 2 T99 1 T12 262
valid_sources[0x0d] 3649 1 T3 3 T4 3 T10 2
valid_sources[0x0e] 6230 1 T2 1 T80 2 T100 2
valid_sources[0x0f] 4669 1 T2 5 T4 1 T18 1
valid_sources[0x10] 3340 1 T2 2 T10 5 T18 4
valid_sources[0x11] 3575 1 T3 1 T4 2 T18 1
valid_sources[0x12] 5295 1 T2 3 T80 1 T100 3
valid_sources[0x13] 3083 1 T4 2 T10 3 T19 5
valid_sources[0x14] 3967 1 T4 2 T45 1 T100 2
valid_sources[0x15] 3779 1 T18 1 T45 2 T46 4
valid_sources[0x16] 3394 1 T10 1 T19 3 T99 5
valid_sources[0x17] 3517 1 T10 2 T11 2 T100 1
valid_sources[0x18] 3311 1 T10 9 T18 2 T80 1
valid_sources[0x19] 3558 1 T2 1 T4 2 T99 1
valid_sources[0x1a] 3651 1 T4 2 T19 1 T99 1
valid_sources[0x1b] 3530 1 T19 4 T99 2 T100 1
valid_sources[0x1c] 3818 1 T2 5 T3 1 T4 3
valid_sources[0x1d] 3036 1 T10 1 T19 4 T45 4
valid_sources[0x1e] 4714 1 T4 1 T10 1 T18 2
valid_sources[0x1f] 3532 1 T99 1 T101 8 T12 294
valid_sources[0x20] 4564 1 T4 1 T19 2 T80 1
valid_sources[0x21] 4926 1 T4 1 T9 21 T10 3
valid_sources[0x22] 3079 1 T2 1 T4 2 T10 1
valid_sources[0x23] 3133 1 T2 1 T99 2 T12 280
valid_sources[0x24] 2746 1 T4 1 T10 1 T18 2
valid_sources[0x25] 3095 1 T2 1 T4 1 T18 1
valid_sources[0x26] 4693 1 T4 1 T10 5 T18 1
valid_sources[0x27] 4058 1 T19 3 T80 1 T99 3
valid_sources[0x28] 3200 1 T10 1 T18 4 T11 5
valid_sources[0x29] 3795 1 T4 5 T19 4 T99 1
valid_sources[0x2a] 4124 1 T10 3 T19 2 T80 1
valid_sources[0x2b] 4207 1 T2 5 T4 3 T18 4
valid_sources[0x2c] 3477 1 T4 2 T19 2 T99 2
valid_sources[0x2d] 4741 1 T3 5 T4 2 T10 9
valid_sources[0x2e] 3532 1 T18 1 T19 3 T80 1
valid_sources[0x2f] 5665 1 T4 1 T19 1 T80 1
valid_sources[0x30] 4223 1 T4 3 T18 2 T80 1
valid_sources[0x31] 3011 1 T2 2 T4 1 T10 1
valid_sources[0x32] 3341 1 T10 3 T81 32 T99 1
valid_sources[0x33] 3064 1 T3 2 T18 1 T80 1
valid_sources[0x34] 3472 1 T4 1 T10 2 T18 1
valid_sources[0x35] 2835 1 T4 3 T19 2 T99 2
valid_sources[0x36] 4107 1 T2 8 T4 1 T10 1
valid_sources[0x37] 2805 1 T2 1 T4 1 T11 3
valid_sources[0x38] 3249 1 T4 2 T10 1 T19 2
valid_sources[0x39] 4636 1 T3 6 T4 2 T10 1
valid_sources[0x3a] 4506 1 T18 6 T19 1 T80 1
valid_sources[0x3b] 3515 1 T2 2 T4 3 T10 2
valid_sources[0x3c] 5267 1 T3 1 T4 4 T99 1
valid_sources[0x3d] 3093 1 T4 2 T10 1 T18 1
valid_sources[0x3e] 3451 1 T4 1 T19 1 T80 1
valid_sources[0x3f] 3366 1 T117 1 T99 1 T12 278
valid_sources[0x40] 4154 1 T18 1 T80 1 T117 2
valid_sources[0x41] 2416 1 T2 1 T3 3 T4 1
valid_sources[0x42] 2949 1 T4 1 T18 1 T19 4
valid_sources[0x43] 4025 1 T18 2 T117 2 T99 3
valid_sources[0x44] 2691 1 T4 5 T46 15 T99 2
valid_sources[0x45] 4795 1 T4 1 T10 2 T117 1
valid_sources[0x46] 3183 1 T3 2 T10 4 T18 3
valid_sources[0x47] 5187 1 T10 1 T99 2 T12 310
valid_sources[0x48] 2997 1 T18 3 T11 4 T117 1
valid_sources[0x49] 4211 1 T3 1 T4 2 T11 7
valid_sources[0x4a] 3456 1 T4 1 T99 1 T100 2
valid_sources[0x4b] 3448 1 T2 8 T4 1 T19 1
valid_sources[0x4c] 3976 1 T4 1 T18 2 T99 1
valid_sources[0x4d] 2769 1 T2 7 T4 2 T10 3
valid_sources[0x4e] 3992 1 T3 4 T4 2 T18 1
valid_sources[0x4f] 5009 1 T18 2 T19 2 T99 2
valid_sources[0x50] 3402 1 T4 1 T18 2 T80 1
valid_sources[0x51] 3252 1 T4 1 T18 1 T100 4
valid_sources[0x52] 3262 1 T2 4 T3 1 T4 1
valid_sources[0x53] 3566 1 T80 1 T99 2 T12 253
valid_sources[0x54] 3016 1 T2 4 T4 2 T10 3
valid_sources[0x55] 3612 1 T2 2 T10 1 T11 3
valid_sources[0x56] 4667 1 T18 1 T11 9 T46 14
valid_sources[0x57] 3248 1 T4 1 T18 1 T80 1
valid_sources[0x58] 4105 1 T4 2 T10 1 T19 1
valid_sources[0x59] 3232 1 T4 2 T10 2 T18 1
valid_sources[0x5a] 2923 1 T10 2 T18 3 T80 1
valid_sources[0x5b] 3600 1 T2 1 T80 1 T12 262
valid_sources[0x5c] 2634 1 T3 10 T4 1 T18 2
valid_sources[0x5d] 2495 1 T2 1 T19 1 T80 1
valid_sources[0x5e] 3486 1 T3 2 T4 1 T117 2
valid_sources[0x5f] 2858 1 T4 1 T18 4 T11 1
valid_sources[0x60] 4003 1 T2 1 T4 1 T18 1
valid_sources[0x61] 3658 1 T4 1 T81 21 T99 1
valid_sources[0x62] 3256 1 T4 1 T19 7 T117 1
valid_sources[0x63] 3314 1 T2 1 T3 3 T80 1
valid_sources[0x64] 3627 1 T3 1 T80 1 T101 1
valid_sources[0x65] 3745 1 T3 1 T4 1 T10 1
valid_sources[0x66] 4246 1 T19 2 T80 1 T117 1
valid_sources[0x67] 2590 1 T2 1 T81 20 T99 1
valid_sources[0x68] 3010 1 T2 2 T19 9 T12 293
valid_sources[0x69] 4253 1 T10 6 T18 1 T81 36
valid_sources[0x6a] 2843 1 T3 1 T4 1 T10 4
valid_sources[0x6b] 4833 1 T3 3 T4 1 T80 1
valid_sources[0x6c] 3345 1 T3 3 T4 2 T18 2
valid_sources[0x6d] 4017 1 T3 2 T99 1 T101 1
valid_sources[0x6e] 4238 1 T4 2 T12 267 T118 2
valid_sources[0x6f] 3004 1 T2 3 T11 1 T19 3
valid_sources[0x70] 3669 1 T99 1 T100 1 T12 264
valid_sources[0x71] 3645 1 T2 5 T4 3 T10 1
valid_sources[0x72] 4068 1 T3 1 T46 6 T117 1
valid_sources[0x73] 2785 1 T3 4 T80 2 T101 1
valid_sources[0x74] 3680 1 T2 1 T3 4 T18 2
valid_sources[0x75] 2868 1 T18 1 T19 3 T99 2
valid_sources[0x76] 2794 1 T3 4 T4 1 T100 2
valid_sources[0x77] 3430 1 T117 1 T99 1 T100 1
valid_sources[0x78] 3047 1 T19 4 T99 1 T100 3
valid_sources[0x79] 4474 1 T10 1 T11 2 T117 1
valid_sources[0x7a] 3879 1 T2 1 T3 1 T4 2
valid_sources[0x7b] 2801 1 T3 2 T4 1 T10 1
valid_sources[0x7c] 3213 1 T2 3 T3 2 T18 2
valid_sources[0x7d] 4974 1 T3 1 T4 4 T10 3
valid_sources[0x7e] 3229 1 T4 1 T18 1 T101 8
valid_sources[0x7f] 3510 1 T117 1 T99 2 T100 2
valid_sources[0x80] 3849 1 T2 4 T4 1 T10 3



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 216150 1 T2 24 T3 19 T4 27
values[0x0] all_enables biggest_size 320794 1 T12 25253 T13 23874 T14 34668
values[0x1] all_enables biggest_size 319891 1 T12 25136 T13 23557 T14 34841


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 68098 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 664039 1 T2 44 T3 53 T4 61



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 186510 1 T1 1 T2 96 T3 96
values[0x0] 252733 1 T12 20620 T24 2 T25 4
values[0x1] 292894 1 T12 23987 T24 6 T25 3



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 32122 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 700015 1 T1 1 T2 50 T3 59



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2864 1 T12 225 T119 1 T120 6
valid_sources[0x01] 3029 1 T11 1 T81 1 T12 226
valid_sources[0x02] 2634 1 T2 2 T18 1 T12 257
valid_sources[0x03] 2757 1 T2 2 T10 1 T45 1
valid_sources[0x04] 2694 1 T12 229 T39 2 T13 162
valid_sources[0x05] 2669 1 T81 1 T121 3 T101 1
valid_sources[0x06] 3033 1 T2 2 T18 2 T12 252
valid_sources[0x07] 2636 1 T10 1 T101 2 T12 228
valid_sources[0x08] 3799 1 T121 1 T101 2 T12 220
valid_sources[0x09] 2517 1 T18 3 T101 1 T12 244
valid_sources[0x0a] 2429 1 T2 2 T18 1 T46 1
valid_sources[0x0b] 2676 1 T10 1 T12 232 T13 54
valid_sources[0x0c] 2945 1 T46 1 T12 225 T122 2
valid_sources[0x0d] 2966 1 T10 1 T45 1 T12 235
valid_sources[0x0e] 2665 1 T10 1 T81 3 T101 1
valid_sources[0x0f] 2791 1 T18 1 T101 3 T12 211
valid_sources[0x10] 3363 1 T8 1 T81 1 T101 1
valid_sources[0x11] 2580 1 T10 1 T81 1 T12 245
valid_sources[0x12] 2720 1 T3 2 T8 1 T18 2
valid_sources[0x13] 2755 1 T12 225 T20 1 T13 60
valid_sources[0x14] 3131 1 T2 1 T10 1 T18 1
valid_sources[0x15] 2979 1 T17 1 T81 1 T12 230
valid_sources[0x16] 2721 1 T8 1 T18 1 T11 1
valid_sources[0x17] 2706 1 T8 1 T12 208 T68 1
valid_sources[0x18] 2992 1 T1 1 T12 248 T13 298
valid_sources[0x19] 2787 1 T18 1 T101 2 T12 233
valid_sources[0x1a] 2629 1 T7 1 T12 232 T20 1
valid_sources[0x1b] 3410 1 T17 1 T18 2 T12 225
valid_sources[0x1c] 2702 1 T12 219 T58 1 T13 270
valid_sources[0x1d] 3221 1 T11 1 T117 1 T12 244
valid_sources[0x1e] 2680 1 T81 1 T12 236 T122 5
valid_sources[0x1f] 3503 1 T10 1 T18 2 T81 3
valid_sources[0x20] 2776 1 T10 2 T18 2 T12 243
valid_sources[0x21] 3301 1 T18 1 T11 1 T81 1
valid_sources[0x22] 2426 1 T3 2 T12 214 T122 3
valid_sources[0x23] 2417 1 T3 1 T10 1 T81 1
valid_sources[0x24] 2560 1 T17 1 T18 1 T121 4
valid_sources[0x25] 2525 1 T12 209 T122 10 T13 15
valid_sources[0x26] 2762 1 T3 6 T17 1 T18 1
valid_sources[0x27] 3419 1 T2 1 T5 1 T10 1
valid_sources[0x28] 2912 1 T3 2 T12 224 T122 5
valid_sources[0x29] 2737 1 T8 2 T18 2 T101 1
valid_sources[0x2a] 2706 1 T2 7 T12 211 T60 7
valid_sources[0x2b] 2674 1 T8 1 T10 1 T18 1
valid_sources[0x2c] 2871 1 T18 1 T11 1 T117 3
valid_sources[0x2d] 2973 1 T2 2 T3 1 T10 3
valid_sources[0x2e] 3355 1 T2 2 T81 1 T12 253
valid_sources[0x2f] 2809 1 T12 216 T58 1 T13 32
valid_sources[0x30] 2935 1 T17 1 T18 1 T81 1
valid_sources[0x31] 3075 1 T3 3 T10 1 T46 1
valid_sources[0x32] 3008 1 T3 5 T101 9 T12 231
valid_sources[0x33] 3179 1 T2 1 T10 4 T101 2
valid_sources[0x34] 3091 1 T101 1 T12 235 T58 1
valid_sources[0x35] 3554 1 T12 237 T60 1 T13 448
valid_sources[0x36] 2632 1 T12 207 T13 27 T14 350
valid_sources[0x37] 2613 1 T10 1 T45 1 T121 2
valid_sources[0x38] 3352 1 T10 1 T11 1 T45 1
valid_sources[0x39] 3122 1 T3 1 T10 2 T101 1
valid_sources[0x3a] 2644 1 T11 1 T81 2 T117 3
valid_sources[0x3b] 3192 1 T2 3 T101 5 T12 247
valid_sources[0x3c] 3298 1 T2 1 T8 1 T10 1
valid_sources[0x3d] 2928 1 T18 1 T12 237 T60 7
valid_sources[0x3e] 2652 1 T3 2 T8 1 T10 1
valid_sources[0x3f] 2801 1 T2 3 T45 1 T81 1
valid_sources[0x40] 2898 1 T45 2 T81 1 T12 239
valid_sources[0x41] 2576 1 T10 2 T12 228 T13 38
valid_sources[0x42] 2639 1 T47 1 T101 1 T12 233
valid_sources[0x43] 3049 1 T17 1 T18 1 T12 221
valid_sources[0x44] 3151 1 T18 1 T121 3 T12 226
valid_sources[0x45] 3179 1 T12 230 T39 1 T13 196
valid_sources[0x46] 2887 1 T11 1 T121 1 T12 243
valid_sources[0x47] 2770 1 T10 1 T18 1 T11 2
valid_sources[0x48] 2930 1 T3 5 T8 1 T10 1
valid_sources[0x49] 3007 1 T12 207 T13 180 T14 278
valid_sources[0x4a] 3041 1 T10 1 T12 224 T13 19
valid_sources[0x4b] 2826 1 T18 2 T12 254 T13 77
valid_sources[0x4c] 2826 1 T12 212 T59 6 T13 186
valid_sources[0x4d] 2833 1 T10 1 T12 223 T60 3
valid_sources[0x4e] 2725 1 T2 1 T46 1 T12 217
valid_sources[0x4f] 2793 1 T18 1 T12 186 T68 1
valid_sources[0x50] 2970 1 T18 1 T11 1 T121 1
valid_sources[0x51] 2692 1 T12 237 T20 2 T13 223
valid_sources[0x52] 2542 1 T8 2 T12 209 T13 161
valid_sources[0x53] 3148 1 T121 1 T12 221 T51 1
valid_sources[0x54] 3075 1 T8 1 T12 231 T39 1
valid_sources[0x55] 3249 1 T8 1 T101 1 T12 218
valid_sources[0x56] 3253 1 T11 1 T46 1 T101 1
valid_sources[0x57] 2773 1 T2 2 T10 1 T12 229
valid_sources[0x58] 3122 1 T2 2 T10 1 T12 234
valid_sources[0x59] 2966 1 T17 1 T81 1 T121 3
valid_sources[0x5a] 2731 1 T10 1 T80 32 T81 1
valid_sources[0x5b] 3383 1 T10 1 T81 1 T12 218
valid_sources[0x5c] 2872 1 T10 1 T12 245 T120 1
valid_sources[0x5d] 3064 1 T2 1 T12 220 T13 9
valid_sources[0x5e] 2946 1 T18 1 T101 2 T12 215
valid_sources[0x5f] 3209 1 T17 1 T12 239 T69 1
valid_sources[0x60] 3098 1 T10 1 T18 2 T12 247
valid_sources[0x61] 3050 1 T18 1 T12 256 T13 423
valid_sources[0x62] 2888 1 T101 1 T12 242 T51 1
valid_sources[0x63] 2871 1 T10 1 T101 1 T12 260
valid_sources[0x64] 2573 1 T2 3 T3 2 T18 2
valid_sources[0x65] 3137 1 T3 5 T121 2 T101 2
valid_sources[0x66] 2712 1 T2 2 T10 1 T11 1
valid_sources[0x67] 2761 1 T10 1 T81 2 T101 1
valid_sources[0x68] 3198 1 T3 2 T8 1 T18 2
valid_sources[0x69] 2698 1 T81 1 T12 200 T39 1
valid_sources[0x6a] 2536 1 T10 1 T12 198 T58 1
valid_sources[0x6b] 2527 1 T2 6 T10 2 T18 1
valid_sources[0x6c] 2942 1 T46 1 T81 1 T117 2
valid_sources[0x6d] 2700 1 T3 4 T18 2 T81 1
valid_sources[0x6e] 2666 1 T2 1 T12 220 T13 243
valid_sources[0x6f] 2747 1 T8 1 T12 238 T13 358
valid_sources[0x70] 2728 1 T17 1 T12 220 T122 4
valid_sources[0x71] 3512 1 T10 1 T18 3 T12 240
valid_sources[0x72] 2449 1 T2 1 T18 3 T12 206
valid_sources[0x73] 2706 1 T12 247 T119 1 T13 87
valid_sources[0x74] 2552 1 T2 1 T3 1 T10 1
valid_sources[0x75] 3285 1 T3 1 T10 1 T18 1
valid_sources[0x76] 3194 1 T45 3 T12 194 T13 596
valid_sources[0x77] 3753 1 T2 4 T12 236 T13 316
valid_sources[0x78] 3044 1 T17 1 T121 1 T12 240
valid_sources[0x79] 3022 1 T17 1 T11 1 T81 1
valid_sources[0x7a] 2865 1 T81 1 T12 215 T60 1
valid_sources[0x7b] 2533 1 T46 1 T12 235 T20 1
valid_sources[0x7c] 2401 1 T2 1 T10 2 T101 1
valid_sources[0x7d] 3622 1 T101 3 T12 250 T13 412
valid_sources[0x7e] 2641 1 T12 235 T13 237 T14 302
valid_sources[0x7f] 2545 1 T10 1 T12 235 T13 142
valid_sources[0x80] 2923 1 T18 1 T117 1 T12 249



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 168837 1 T2 44 T3 53 T4 61
values[0x0] all_enables biggest_size 247172 1 T12 20227 T24 1 T25 1
values[0x1] all_enables biggest_size 248030 1 T12 20192 T27 1 T26 1

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