Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1575801

1

T2

218

T3

192

T4

216

full_word

999186

1

T2

24

T3

19

T4

27

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2574717	1			T2	242		T3	211		T4	243
auto[TlIntgErrCmd]	88	1			T61	6		T62	6		T63	5
auto[TlIntgErrData]	82	1			T61	7		T62	3		T63	6
auto[TlIntgErrBoth]	100	1			T61	7		T62	11		T63	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

417617

1

T2

242

T3

211

T4

243

auto[1]

2157370

1

T12

172051

T13

165034

T14

240978

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	180789	1			T2	218		T3	192		T4	216
auto[TlIntgErrNone]	partial	auto[1]	1394762	1			T12	112087		T13	108166		T14	157810
auto[TlIntgErrNone]	full_word	auto[0]	236701	1			T2	24		T3	19		T4	27
auto[TlIntgErrNone]	full_word	auto[1]	762465	1			T12	59964		T13	56868		T14	83168
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T61	2		T62	4		T63	3
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T61	3		T62	2		T63	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T110	1		T111	1		T112	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T61	1		T113	1		T107	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T61	3		T62	1		T63	2
auto[TlIntgErrData]	partial	auto[1]	39	1			T61	4		T62	2		T63	4
auto[TlIntgErrData]	full_word	auto[0]	1	1			T113	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T114	1		T112	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T61	4		T62	4		T63	5
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T61	3		T62	5		T63	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T62	1		T111	1		T115	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T62	1		T63	1		T116	1