Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 42405 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 727203 1 T1 43 T2 8 T3 14



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 211243 1 T1 374 T2 85 T3 120
values[0x0] 274133 1 T13 54125 T14 18655 T15 21250
values[0x1] 284232 1 T13 56406 T14 19317 T15 21913



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 21082 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 748526 1 T1 235 T2 47 T3 74



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2259 1 T1 3 T6 1 T10 4
valid_sources[0x01] 2701 1 T12 1 T107 2 T122 1
valid_sources[0x02] 3691 1 T1 4 T3 9 T6 1
valid_sources[0x03] 2575 1 T2 1 T6 1 T11 8
valid_sources[0x04] 3575 1 T1 1 T3 3 T10 3
valid_sources[0x05] 2593 1 T1 1 T107 2 T48 2
valid_sources[0x06] 2072 1 T10 6 T48 1 T91 1
valid_sources[0x07] 2823 1 T1 2 T6 1 T122 1
valid_sources[0x08] 2773 1 T1 2 T2 1 T6 1
valid_sources[0x09] 2451 1 T3 8 T6 1 T10 2
valid_sources[0x0a] 3890 1 T1 1 T6 2 T107 1
valid_sources[0x0b] 2848 1 T2 1 T6 1 T107 1
valid_sources[0x0c] 3468 1 T6 3 T49 1 T13 691
valid_sources[0x0d] 2589 1 T6 1 T10 1 T122 1
valid_sources[0x0e] 2955 1 T6 1 T107 1 T13 931
valid_sources[0x0f] 3437 1 T1 7 T6 4 T38 3
valid_sources[0x10] 2442 1 T2 1 T12 1 T107 1
valid_sources[0x11] 2726 1 T6 1 T12 1 T107 2
valid_sources[0x12] 3338 1 T1 4 T6 2 T12 1
valid_sources[0x13] 3945 1 T1 7 T10 4 T122 1
valid_sources[0x14] 2781 1 T2 1 T5 24 T6 1
valid_sources[0x15] 2094 1 T6 2 T48 1 T91 4
valid_sources[0x16] 3002 1 T1 1 T6 1 T12 1
valid_sources[0x17] 3701 1 T6 1 T12 1 T13 393
valid_sources[0x18] 2999 1 T3 2 T10 5 T122 1
valid_sources[0x19] 3462 1 T1 1 T6 1 T16 3
valid_sources[0x1a] 2931 1 T2 1 T3 4 T6 1
valid_sources[0x1b] 2977 1 T6 1 T17 7 T13 595
valid_sources[0x1c] 2388 1 T1 3 T107 1 T13 402
valid_sources[0x1d] 3715 1 T6 1 T13 836 T14 261
valid_sources[0x1e] 2348 1 T1 5 T2 1 T6 3
valid_sources[0x1f] 3379 1 T6 5 T13 297 T67 1
valid_sources[0x20] 2711 1 T6 4 T16 1 T107 2
valid_sources[0x21] 3577 1 T107 1 T53 10 T13 1552
valid_sources[0x22] 3507 1 T1 1 T6 1 T10 1
valid_sources[0x23] 3245 1 T1 5 T6 2 T107 2
valid_sources[0x24] 2809 1 T1 8 T2 1 T6 1
valid_sources[0x25] 3038 1 T1 7 T6 3 T107 4
valid_sources[0x26] 2463 1 T1 1 T2 1 T6 1
valid_sources[0x27] 3091 1 T10 7 T107 2 T49 2
valid_sources[0x28] 2597 1 T1 3 T2 1 T6 1
valid_sources[0x29] 2882 1 T1 3 T2 1 T6 1
valid_sources[0x2a] 2812 1 T6 2 T17 4 T107 1
valid_sources[0x2b] 2545 1 T2 1 T6 1 T107 1
valid_sources[0x2c] 2869 1 T6 2 T10 1 T11 10
valid_sources[0x2d] 2491 1 T6 2 T12 1 T107 2
valid_sources[0x2e] 2730 1 T1 7 T5 82 T6 2
valid_sources[0x2f] 2531 1 T1 7 T6 2 T17 2
valid_sources[0x30] 2902 1 T107 2 T49 4 T13 346
valid_sources[0x31] 2419 1 T2 1 T6 1 T11 2
valid_sources[0x32] 4031 1 T1 3 T13 1997 T14 205
valid_sources[0x33] 3183 1 T1 1 T6 2 T12 1
valid_sources[0x34] 4230 1 T1 2 T6 1 T107 1
valid_sources[0x35] 3237 1 T6 4 T10 1 T17 8
valid_sources[0x36] 3297 1 T1 2 T6 1 T107 1
valid_sources[0x37] 2549 1 T1 6 T107 3 T48 3
valid_sources[0x38] 2878 1 T107 1 T13 617 T14 217
valid_sources[0x39] 3200 1 T1 2 T3 5 T6 1
valid_sources[0x3a] 3044 1 T107 3 T91 2 T13 389
valid_sources[0x3b] 4017 1 T1 4 T2 1 T6 2
valid_sources[0x3c] 2754 1 T6 3 T12 1 T13 279
valid_sources[0x3d] 3308 1 T6 1 T13 210 T14 192
valid_sources[0x3e] 3924 1 T16 4 T123 1 T13 1109
valid_sources[0x3f] 3634 1 T1 3 T17 3 T16 1
valid_sources[0x40] 3071 1 T1 1 T2 1 T5 16
valid_sources[0x41] 2358 1 T1 3 T12 1 T107 1
valid_sources[0x42] 2593 1 T1 4 T2 1 T6 3
valid_sources[0x43] 2348 1 T1 2 T6 1 T16 1
valid_sources[0x44] 3968 1 T6 2 T107 1 T13 1351
valid_sources[0x45] 3257 1 T6 1 T107 1 T48 1
valid_sources[0x46] 3013 1 T1 1 T3 3 T6 1
valid_sources[0x47] 2328 1 T1 1 T13 223 T67 1
valid_sources[0x48] 4177 1 T2 2 T6 3 T107 1
valid_sources[0x49] 2306 1 T6 2 T16 2 T107 2
valid_sources[0x4a] 3190 1 T6 2 T122 1 T13 909
valid_sources[0x4b] 2976 1 T2 1 T6 1 T91 1
valid_sources[0x4c] 3648 1 T6 1 T107 2 T13 1023
valid_sources[0x4d] 2623 1 T1 4 T2 3 T49 1
valid_sources[0x4e] 3686 1 T2 1 T16 1 T107 2
valid_sources[0x4f] 2899 1 T6 2 T12 1 T107 1
valid_sources[0x50] 3145 1 T1 2 T123 2 T42 1
valid_sources[0x51] 2932 1 T6 2 T10 8 T107 2
valid_sources[0x52] 4190 1 T1 9 T8 1 T10 1
valid_sources[0x53] 2528 1 T1 1 T6 1 T41 1
valid_sources[0x54] 2039 1 T1 1 T14 203 T15 148
valid_sources[0x55] 2861 1 T6 2 T107 1 T13 758
valid_sources[0x56] 3125 1 T6 1 T12 1 T107 1
valid_sources[0x57] 3032 1 T107 1 T13 757 T14 176
valid_sources[0x58] 2289 1 T6 2 T107 2 T48 1
valid_sources[0x59] 2611 1 T3 6 T6 1 T8 1
valid_sources[0x5a] 4369 1 T1 1 T12 1 T107 2
valid_sources[0x5b] 2576 1 T2 1 T3 3 T17 4
valid_sources[0x5c] 4086 1 T16 1 T11 2 T107 4
valid_sources[0x5d] 3015 1 T1 5 T107 2 T13 944
valid_sources[0x5e] 3049 1 T6 1 T122 2 T123 2
valid_sources[0x5f] 3490 1 T6 1 T107 1 T48 1
valid_sources[0x60] 2845 1 T1 4 T107 1 T13 793
valid_sources[0x61] 2588 1 T1 1 T6 2 T107 1
valid_sources[0x62] 2250 1 T1 1 T6 1 T10 1
valid_sources[0x63] 3483 1 T6 1 T17 4 T16 5
valid_sources[0x64] 2316 1 T1 1 T2 1 T6 1
valid_sources[0x65] 3780 1 T1 7 T6 2 T107 1
valid_sources[0x66] 3589 1 T1 1 T2 2 T10 4
valid_sources[0x67] 3251 1 T2 1 T6 3 T107 1
valid_sources[0x68] 3308 1 T8 1 T16 3 T13 1265
valid_sources[0x69] 2408 1 T2 1 T6 1 T107 2
valid_sources[0x6a] 2625 1 T6 1 T12 1 T107 1
valid_sources[0x6b] 2925 1 T17 1 T13 390 T67 1
valid_sources[0x6c] 2417 1 T1 5 T10 4 T107 2
valid_sources[0x6d] 3317 1 T6 3 T107 1 T49 3
valid_sources[0x6e] 3238 1 T1 3 T6 1 T107 2
valid_sources[0x6f] 2733 1 T1 2 T16 1 T107 1
valid_sources[0x70] 3072 1 T1 5 T6 1 T123 2
valid_sources[0x71] 3352 1 T1 1 T12 1 T91 1
valid_sources[0x72] 2255 1 T1 6 T6 3 T107 3
valid_sources[0x73] 2969 1 T1 1 T107 4 T49 2
valid_sources[0x74] 2982 1 T2 2 T6 3 T10 1
valid_sources[0x75] 2400 1 T1 3 T2 1 T6 1
valid_sources[0x76] 2522 1 T6 1 T10 2 T122 1
valid_sources[0x77] 2674 1 T1 1 T10 1 T17 11
valid_sources[0x78] 2873 1 T1 3 T6 1 T12 3
valid_sources[0x79] 2723 1 T1 3 T6 1 T16 1
valid_sources[0x7a] 2290 1 T1 6 T2 1 T3 2
valid_sources[0x7b] 3426 1 T1 3 T2 1 T6 1
valid_sources[0x7c] 3684 1 T1 1 T6 1 T10 1
valid_sources[0x7d] 2850 1 T1 1 T2 2 T6 4
valid_sources[0x7e] 3163 1 T2 3 T13 763 T14 219
valid_sources[0x7f] 3319 1 T3 7 T6 1 T107 1
valid_sources[0x80] 3919 1 T6 1 T12 1 T48 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 183958 1 T1 43 T2 8 T3 14
values[0x0] all_enables biggest_size 271682 1 T13 53652 T14 18499 T15 21066
values[0x1] all_enables biggest_size 271563 1 T13 54063 T14 18446 T15 21037


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 59651 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 561388 1 T2 14 T3 38 T4 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 157683 1 T2 32 T3 64 T4 1
values[0x0] 214727 1 T7 4 T9 3 T24 3
values[0x1] 248629 1 T7 6 T9 10 T24 4



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 28283 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 592756 1 T2 18 T3 43 T4 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2237 1 T27 1 T13 449 T14 157
valid_sources[0x01] 2949 1 T2 1 T75 4 T51 4
valid_sources[0x02] 2146 1 T27 1 T42 4 T91 2
valid_sources[0x03] 2669 1 T75 1 T19 1 T42 1
valid_sources[0x04] 2443 1 T5 1 T90 3 T91 1
valid_sources[0x05] 2605 1 T75 1 T42 1 T13 446
valid_sources[0x06] 2621 1 T90 4 T75 1 T13 447
valid_sources[0x07] 2898 1 T5 1 T27 1 T75 1
valid_sources[0x08] 2630 1 T2 1 T75 1 T13 460
valid_sources[0x09] 2301 1 T5 1 T18 1 T38 1
valid_sources[0x0a] 2373 1 T13 438 T14 133 T15 166
valid_sources[0x0b] 2332 1 T5 1 T75 2 T13 417
valid_sources[0x0c] 2624 1 T39 1 T13 476 T14 145
valid_sources[0x0d] 3029 1 T42 2 T91 1 T13 475
valid_sources[0x0e] 2394 1 T75 1 T91 1 T13 447
valid_sources[0x0f] 2599 1 T2 2 T27 1 T75 1
valid_sources[0x10] 2626 1 T2 3 T3 17 T27 1
valid_sources[0x11] 2345 1 T122 4 T123 32 T13 453
valid_sources[0x12] 3144 1 T5 1 T17 18 T13 462
valid_sources[0x13] 1966 1 T18 1 T48 2 T91 1
valid_sources[0x14] 2743 1 T90 1 T13 492 T14 188
valid_sources[0x15] 2580 1 T39 1 T42 2 T13 413
valid_sources[0x16] 2698 1 T122 1 T13 478 T14 194
valid_sources[0x17] 2304 1 T58 2 T13 459 T14 137
valid_sources[0x18] 2171 1 T13 468 T14 182 T15 133
valid_sources[0x19] 2691 1 T27 1 T13 478 T14 165
valid_sources[0x1a] 2359 1 T75 1 T48 2 T13 441
valid_sources[0x1b] 2159 1 T19 1 T92 1 T13 478
valid_sources[0x1c] 2197 1 T75 2 T38 1 T13 474
valid_sources[0x1d] 1998 1 T2 2 T5 1 T90 4
valid_sources[0x1e] 2006 1 T2 1 T46 1 T13 481
valid_sources[0x1f] 2657 1 T91 1 T13 464 T14 145
valid_sources[0x20] 1919 1 T46 1 T91 1 T13 451
valid_sources[0x21] 2435 1 T42 2 T13 447 T14 232
valid_sources[0x22] 2782 1 T5 1 T75 1 T48 4
valid_sources[0x23] 2111 1 T2 1 T19 1 T122 1
valid_sources[0x24] 2987 1 T5 2 T75 2 T43 8
valid_sources[0x25] 2464 1 T19 1 T13 476 T14 185
valid_sources[0x26] 2622 1 T5 1 T41 1 T13 463
valid_sources[0x27] 2092 1 T18 1 T13 452 T14 163
valid_sources[0x28] 2124 1 T5 1 T75 1 T40 33
valid_sources[0x29] 2438 1 T13 472 T67 1 T14 153
valid_sources[0x2a] 2177 1 T12 32 T13 433 T14 160
valid_sources[0x2b] 2438 1 T41 1 T13 463 T14 117
valid_sources[0x2c] 2449 1 T46 1 T38 1 T13 466
valid_sources[0x2d] 2291 1 T13 492 T14 147 T15 189
valid_sources[0x2e] 2098 1 T75 1 T48 1 T39 1
valid_sources[0x2f] 1715 1 T4 1 T49 1 T51 1
valid_sources[0x30] 2744 1 T27 1 T75 1 T13 453
valid_sources[0x31] 2067 1 T75 1 T122 1 T13 430
valid_sources[0x32] 2306 1 T48 1 T92 1 T13 444
valid_sources[0x33] 2446 1 T5 1 T27 1 T75 1
valid_sources[0x34] 2288 1 T90 2 T58 1 T13 437
valid_sources[0x35] 2393 1 T5 1 T75 1 T13 436
valid_sources[0x36] 2415 1 T2 1 T13 459 T14 175
valid_sources[0x37] 2435 1 T48 2 T39 4 T13 465
valid_sources[0x38] 2897 1 T47 8 T49 4 T91 2
valid_sources[0x39] 2497 1 T2 1 T5 1 T75 2
valid_sources[0x3a] 2231 1 T5 1 T13 442 T14 194
valid_sources[0x3b] 2673 1 T39 1 T13 444 T14 136
valid_sources[0x3c] 2360 1 T27 1 T75 1 T39 1
valid_sources[0x3d] 2980 1 T48 1 T13 465 T14 140
valid_sources[0x3e] 2191 1 T90 2 T91 1 T13 485
valid_sources[0x3f] 2885 1 T13 438 T14 139 T15 124
valid_sources[0x40] 2032 1 T75 1 T46 1 T48 1
valid_sources[0x41] 2183 1 T13 431 T14 249 T15 141
valid_sources[0x42] 2107 1 T39 1 T13 439 T14 162
valid_sources[0x43] 2175 1 T7 1 T75 1 T46 1
valid_sources[0x44] 2313 1 T5 1 T17 1 T13 474
valid_sources[0x45] 2206 1 T5 1 T90 4 T122 1
valid_sources[0x46] 2236 1 T58 1 T92 1 T13 438
valid_sources[0x47] 2385 1 T27 1 T122 1 T13 456
valid_sources[0x48] 2080 1 T58 1 T13 448 T67 1
valid_sources[0x49] 1989 1 T13 433 T14 185 T15 156
valid_sources[0x4a] 2225 1 T23 1 T27 1 T58 1
valid_sources[0x4b] 2007 1 T75 1 T13 436 T14 149
valid_sources[0x4c] 2853 1 T75 1 T13 456 T14 154
valid_sources[0x4d] 2444 1 T5 1 T75 1 T13 445
valid_sources[0x4e] 2182 1 T75 1 T18 1 T13 429
valid_sources[0x4f] 2474 1 T19 1 T122 1 T13 438
valid_sources[0x50] 1950 1 T5 1 T7 2 T75 1
valid_sources[0x51] 2247 1 T2 1 T5 1 T19 2
valid_sources[0x52] 2609 1 T17 2 T75 1 T39 1
valid_sources[0x53] 2747 1 T75 1 T91 1 T13 425
valid_sources[0x54] 3172 1 T90 1 T75 1 T122 1
valid_sources[0x55] 2599 1 T39 1 T91 1 T13 435
valid_sources[0x56] 2312 1 T75 1 T38 1 T58 1
valid_sources[0x57] 2253 1 T5 1 T7 3 T75 2
valid_sources[0x58] 2526 1 T3 25 T90 3 T39 1
valid_sources[0x59] 2109 1 T75 1 T41 1 T13 421
valid_sources[0x5a] 2651 1 T75 2 T39 1 T13 453
valid_sources[0x5b] 2202 1 T75 1 T92 1 T13 427
valid_sources[0x5c] 2350 1 T5 1 T75 1 T13 481
valid_sources[0x5d] 2313 1 T5 1 T75 1 T19 3
valid_sources[0x5e] 2777 1 T90 2 T75 2 T26 1
valid_sources[0x5f] 2244 1 T27 1 T75 1 T51 3
valid_sources[0x60] 2224 1 T27 1 T49 3 T13 480
valid_sources[0x61] 2708 1 T13 410 T14 182 T15 199
valid_sources[0x62] 2322 1 T48 2 T13 464 T14 151
valid_sources[0x63] 2767 1 T41 1 T13 489 T69 4
valid_sources[0x64] 2355 1 T27 1 T13 483 T14 141
valid_sources[0x65] 2604 1 T75 3 T38 1 T13 456
valid_sources[0x66] 2490 1 T3 4 T5 1 T16 11
valid_sources[0x67] 2285 1 T27 1 T18 1 T48 1
valid_sources[0x68] 2931 1 T75 1 T48 1 T39 1
valid_sources[0x69] 2197 1 T13 469 T14 171 T15 161
valid_sources[0x6a] 2118 1 T2 1 T7 2 T92 1
valid_sources[0x6b] 2299 1 T18 2 T91 2 T13 449
valid_sources[0x6c] 2744 1 T5 1 T90 5 T48 3
valid_sources[0x6d] 2835 1 T27 1 T75 4 T13 481
valid_sources[0x6e] 2242 1 T2 1 T27 1 T13 461
valid_sources[0x6f] 2536 1 T41 4 T91 1 T13 526
valid_sources[0x70] 2962 1 T75 1 T92 1 T13 476
valid_sources[0x71] 2123 1 T2 1 T19 2 T13 427
valid_sources[0x72] 2748 1 T27 1 T75 1 T38 1
valid_sources[0x73] 2271 1 T80 1 T13 496 T69 2
valid_sources[0x74] 3085 1 T39 1 T13 460 T14 172
valid_sources[0x75] 2489 1 T38 1 T91 1 T13 437
valid_sources[0x76] 2594 1 T13 485 T14 187 T15 258
valid_sources[0x77] 2902 1 T18 1 T13 462 T14 186
valid_sources[0x78] 1988 1 T3 7 T90 5 T13 443
valid_sources[0x79] 2119 1 T57 1 T44 8 T13 427
valid_sources[0x7a] 2039 1 T5 1 T75 1 T91 1
valid_sources[0x7b] 2653 1 T13 434 T14 207 T15 207
valid_sources[0x7c] 2945 1 T5 1 T13 462 T69 1
valid_sources[0x7d] 2104 1 T75 2 T92 1 T13 466
valid_sources[0x7e] 2808 1 T49 2 T38 1 T13 487
valid_sources[0x7f] 2630 1 T27 1 T18 1 T38 2
valid_sources[0x80] 2180 1 T5 1 T75 1 T39 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 141705 1 T2 14 T3 38 T4 1
values[0x0] all_enables biggest_size 209866 1 T7 1 T9 1 T25 1
values[0x1] all_enables biggest_size 209817 1 T9 2 T24 1 T79 2

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