Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1350984

1

T1

331

T2

77

T3

106

full_word

849594

1

T1

43

T2

8

T3

14

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2200248	1			T1	374		T2	85		T3	120
auto[TlIntgErrCmd]	108	1			T72	3		T73	8		T74	2
auto[TlIntgErrData]	115	1			T72	4		T73	7		T74	5
auto[TlIntgErrBoth]	107	1			T72	3		T73	5		T74	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

359605

1

T1

374

T2

85

T3

120

auto[1]

1840973

1

T13

365534

T14

127031

T15

133526

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157894	1			T1	331		T2	77		T3	106
auto[TlIntgErrNone]	partial	auto[1]	1192796	1			T13	236590		T14	82701		T15	84102
auto[TlIntgErrNone]	full_word	auto[0]	201545	1			T1	43		T2	8		T3	14
auto[TlIntgErrNone]	full_word	auto[1]	648013	1			T13	128944		T14	44330		T15	49424
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T73	3		T108	5		T113	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T72	3		T73	3		T74	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T110	1		T119	1		T111	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T73	2		T108	1		T110	2
auto[TlIntgErrData]	partial	auto[0]	56	1			T72	4		T73	2		T74	3
auto[TlIntgErrData]	partial	auto[1]	49	1			T73	3		T74	2		T108	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T73	2		T108	1		T113	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T116	2		T118	1		T120	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T72	2		T73	2		T108	4
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T72	1		T73	2		T74	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T74	1		T121	1		T120	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T73	1		T108	1		T121	1