Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.05	100.00	98.28	97.26		100.00	69.70

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	93.05	100.00	98.28	97.26		100.00	69.70

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.05	100.00	98.28	97.26		100.00	69.70

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.10	96.89	92.13	97.68	100.00	98.62	97.30

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	96.36	100.00	97.22	90.00	100.00	100.00	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.18	100.00				100.00	97.55
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	93.10	90.70	82.93	97.66		94.20	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	442	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
212	1	1
258	1	1
313	1	1
414	8	8
415	8	8
417	8	8
418	8	8
420	8	8
421	8	8
425	1	1
427	1	1
430	1	1
431	1	1
432	1	1
433	1	1
438	1	1
442	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       212
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       258
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T18,T19
1	1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T22
1	0	Not Covered

 LINE       427
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T18,T19
1	0	Covered	T4,T8,T23

 LINE       438
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T9,T24

 LINE       442
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T8,T18,T19
0	1	0	Covered	T4,T8,T23
1	0	0	Covered	T20,T21,T22

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	62	56	90.32
Total Bits	2884	2805	97.26
Total Bits 0->1	1442	1402	97.23
Total Bits 1->0	1442	1403	97.30

Ports	62	56	90.32
Port Bits	2884	2805	97.26
Port Bits 0->1	1442	1402	97.23
Port Bits 1->0	1442	1403	97.30

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_cfg_i.test	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T6,T11,T12	Yes	T6,T11,T12	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T6,T11,T12	Yes	T6,T11,T12	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_o.a_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T16	Yes	T3,T16,T25	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T3,T7,T9	Yes	T3,T4,T7	INPUT
regs_tl_i.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_o.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_error	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T3,*T5	Yes	T2,T3,T5	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T4,T7,T8	Yes	T4,T7,T8	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T4,T7,T8	Yes	T4,T7,T8	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	OUTPUT
keymgr_data_o.valid	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
kmac_data_i.error	No	Yes	T4,T23,T26	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T6,T8,T27	Yes	T2,T3,T5	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T6,T8,T16	Yes	T3,T6,T8	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	212	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	23	69.70
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	23	69.70

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	286417207	286246093	0	0
BusRomIndicesMatch_A	286401544	286236823	0	0
FpvSecCmRegWeOnehotCheck_A	286417207	60	0	0
FpvSecCmReqFifoRptrCheck_A	286417207	0	0	0
FpvSecCmReqFifoWptrCheck_A	286417207	0	0	0
FpvSecCmRspFifoRptrCheck_A	286417207	0	0	0
FpvSecCmRspFifoWptrCheck_A	286417207	0	0	0
FpvSecCmSramReqFifoRptrCheck_A	286417207	0	0	0
FpvSecCmSramReqFifoWptrCheck_A	286417207	0	0	0
KeymgrDataODataKnown_A	286417207	27332572	0	0
KeymgrDataODataKnown_AKnownEnable	286417207	286246093	0	0
KeymgrDataOValidKnown_A	286417207	286246093	0	0
KeymgrValidChk_A	286417207	0	0	311
KmacDataODataKnown_A	286417207	258795891	0	0
KmacDataODataKnown_AKnownEnable	286417207	286246093	0	0
KmacDataOValidKnown_A	286417207	286246093	0	0
PwrmgrDataChk_A	286417207	0	0	311
PwrmgrDataOKnown_A	286417207	286246093	0	0
RegsTlOAReadyKnown_A	286417207	286246093	0	0
RegsTlODDataKnown_A	286417207	3735629	0	0
RegsTlODDataKnown_AKnownEnable	286417207	286246093	0	0
RegsTlODValidKnown_A	286417207	286246093	0	0
RomTlOAReadyKnown_A	286417207	286246093	0	0
RomTlODDataKnown_A	286417207	4701958	0	0
RomTlODDataKnown_AKnownEnable	286417207	286246093	0	0
RomTlODValidKnown_A	286417207	286246093	0	0
StabilityChkKmac_A	286417207	258793555	0	0
StabilityChkkeymgr_A	286417207	27331472	0	0
TlAccessChk_A	286417207	258913521	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	286417207	60	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	286417207	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	286417207	539	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	286417207	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	286246093	0	0
T1	197944	197856	0	0
T2	231945	231791	0	0
T3	938942	938698	0	0
T4	637800	637651	0	0
T5	37965	37688	0	0
T6	164478	164401	0	0
T7	277352	277269	0	0
T8	689573	687957	0	0
T9	294578	294523	0	0
T10	148693	148613	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286401544	286236823	0	0
T1	197944	197856	0	0
T2	231945	231791	0	0
T3	938942	938698	0	0
T4	637800	637651	0	0
T5	37965	37688	0	0
T6	164478	164401	0	0
T7	277352	277269	0	0
T8	688924	687486	0	0
T9	294578	294523	0	0
T10	148693	148613	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	60	0	0
T20	256227	10	0	0
T21	213262	10	0	0
T22	0	10	0	0
T28	0	20	0	0
T29	0	10	0	0
T30	511330	0	0	0
T31	395316	0	0	0
T32	265142	0	0	0
T33	105612	0	0	0
T34	17483	0	0	0
T35	454352	0	0	0
T36	412887	0	0	0
T37	294944	0	0	0

FpvSecCmReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	0	0	0

FpvSecCmReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	0	0	0

FpvSecCmRspFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	0	0	0

FpvSecCmRspFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	0	0	0

FpvSecCmSramReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	0	0	0

FpvSecCmSramReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	27332572	0	0
T1	197944	1273	0	0
T2	231945	1497	0	0
T3	938942	2207	0	0
T4	637800	145	0	0
T5	37965	4033	0	0
T6	164478	4516	0	0
T7	277352	7	0	0
T8	689573	10319	0	0
T9	294578	227	0	0
T10	148693	818	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	286246093	0	0
T1	197944	197856	0	0
T2	231945	231791	0	0
T3	938942	938698	0	0
T4	637800	637651	0	0
T5	37965	37688	0	0
T6	164478	164401	0	0
T7	277352	277269	0	0
T8	689573	687957	0	0
T9	294578	294523	0	0
T10	148693	148613	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	286246093	0	0
T1	197944	197856	0	0
T2	231945	231791	0	0
T3	938942	938698	0	0
T4	637800	637651	0	0
T5	37965	37688	0	0
T6	164478	164401	0	0
T7	277352	277269	0	0
T8	689573	687957	0	0
T9	294578	294523	0	0
T10	148693	148613	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	0	0	311

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	258795891	0	0
T1	197944	196470	0	0
T2	231945	230204	0	0
T3	938942	936275	0	0
T4	637800	637288	0	0
T5	37965	33609	0	0
T6	164478	163892	0	0
T7	277352	277217	0	0
T8	689573	676440	0	0
T9	294578	294206	0	0
T10	148693	147706	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	286246093	0	0
T1	197944	197856	0	0
T2	231945	231791	0	0
T3	938942	938698	0	0
T4	637800	637651	0	0
T5	37965	37688	0	0
T6	164478	164401	0	0
T7	277352	277269	0	0
T8	689573	687957	0	0
T9	294578	294523	0	0
T10	148693	148613	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	286246093	0	0
T1	197944	197856	0	0
T2	231945	231791	0	0
T3	938942	938698	0	0
T4	637800	637651	0	0
T5	37965	37688	0	0
T6	164478	164401	0	0
T7	277352	277269	0	0
T8	689573	687957	0	0
T9	294578	294523	0	0
T10	148693	148613	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	0	0	311

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	286246093	0	0
T1	197944	197856	0	0
T2	231945	231791	0	0
T3	938942	938698	0	0
T4	637800	637651	0	0
T5	37965	37688	0	0
T6	164478	164401	0	0
T7	277352	277269	0	0
T8	689573	687957	0	0
T9	294578	294523	0	0
T10	148693	148613	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	286246093	0	0
T1	197944	197856	0	0
T2	231945	231791	0	0
T3	938942	938698	0	0
T4	637800	637651	0	0
T5	37965	37688	0	0
T6	164478	164401	0	0
T7	277352	277269	0	0
T8	689573	687957	0	0
T9	294578	294523	0	0
T10	148693	148613	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	3735629	0	0
T2	231945	32	0	0
T3	938942	64	0	0
T4	637800	1	0	0
T5	37965	64	0	0
T6	164478	128	0	0
T7	277352	42	0	0
T8	689573	17	0	0
T9	294578	47	0	0
T10	148693	0	0	0
T16	0	108	0	0
T17	688973	148	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	286246093	0	0
T1	197944	197856	0	0
T2	231945	231791	0	0
T3	938942	938698	0	0
T4	637800	637651	0	0
T5	37965	37688	0	0
T6	164478	164401	0	0
T7	277352	277269	0	0
T8	689573	687957	0	0
T9	294578	294523	0	0
T10	148693	148613	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	286246093	0	0
T1	197944	197856	0	0
T2	231945	231791	0	0
T3	938942	938698	0	0
T4	637800	637651	0	0
T5	37965	37688	0	0
T6	164478	164401	0	0
T7	277352	277269	0	0
T8	689573	687957	0	0
T9	294578	294523	0	0
T10	148693	148613	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	286246093	0	0
T1	197944	197856	0	0
T2	231945	231791	0	0
T3	938942	938698	0	0
T4	637800	637651	0	0
T5	37965	37688	0	0
T6	164478	164401	0	0
T7	277352	277269	0	0
T8	689573	687957	0	0
T9	294578	294523	0	0
T10	148693	148613	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	4701958	0	0
T1	197944	374	0	0
T2	231945	474	0	0
T3	938942	592	0	0
T4	637800	0	0	0
T5	37965	161	0	0
T6	164478	300	0	0
T7	277352	0	0	0
T8	689573	26	0	0
T9	294578	0	0	0
T10	148693	157	0	0
T11	0	76	0	0
T16	0	365	0	0
T17	0	61	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	286246093	0	0
T1	197944	197856	0	0
T2	231945	231791	0	0
T3	938942	938698	0	0
T4	637800	637651	0	0
T5	37965	37688	0	0
T6	164478	164401	0	0
T7	277352	277269	0	0
T8	689573	687957	0	0
T9	294578	294523	0	0
T10	148693	148613	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	286246093	0	0
T1	197944	197856	0	0
T2	231945	231791	0	0
T3	938942	938698	0	0
T4	637800	637651	0	0
T5	37965	37688	0	0
T6	164478	164401	0	0
T7	277352	277269	0	0
T8	689573	687957	0	0
T9	294578	294523	0	0
T10	148693	148613	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	258793555	0	0
T1	197944	196469	0	0
T2	231945	230202	0	0
T3	938942	936272	0	0
T4	637800	637286	0	0
T5	37965	33605	0	0
T6	164478	163891	0	0
T7	277352	277216	0	0
T8	689573	676419	0	0
T9	294578	294205	0	0
T10	148693	147705	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	27331472	0	0
T1	197944	1272	0	0
T2	231945	1495	0	0
T3	938942	2204	0	0
T4	637800	144	0	0
T5	37965	4031	0	0
T6	164478	4508	0	0
T7	277352	6	0	0
T8	689573	10309	0	0
T9	294578	226	0	0
T10	148693	817	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	258913521	0	0
T1	197944	196583	0	0
T2	231945	230294	0	0
T3	938942	936491	0	0
T4	637800	637506	0	0
T5	37965	33655	0	0
T6	164478	163949	0	0
T7	277352	277262	0	0
T8	689573	677638	0	0
T9	294578	294296	0	0
T10	148693	147795	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	60	0	0
T20	256227	10	0	0
T21	213262	10	0	0
T22	0	10	0	0
T28	0	20	0	0
T29	0	10	0	0
T30	511330	0	0	0
T31	395316	0	0	0
T32	265142	0	0	0
T33	105612	0	0	0
T34	17483	0	0	0
T35	454352	0	0	0
T36	412887	0	0	0
T37	294944	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	539	0	0
T18	243336	5	0	0
T19	396279	15	0	0
T38	294523	10	0	0
T39	543573	15	0	0
T40	0	15	0	0
T41	0	5	0	0
T42	0	10	0	0
T43	0	5	0	0
T44	0	10	0	0
T45	0	20	0	0
T46	244829	0	0	0
T47	384043	0	0	0
T48	804101	0	0	0
T49	132944	0	0	0
T50	33222	0	0	0
T51	378652	0	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286417207	0	0	0