Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36476	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

515898

1

T4

30

T7

5

T9

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	157334	1			T4	375		T7	56		T9	66
values[0x0]	193931	1			T13	19106		T14	13650		T15	18600
values[0x1]	201109	1			T13	19725		T14	14182		T15	19693

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17762	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

534612

1

T4

218

T7

28

T9

44

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2235	1			T12	1		T18	1		T86	1
valid_sources[0x01]	1807	1			T9	18		T11	9		T118	7
valid_sources[0x02]	2116	1			T22	1		T32	2		T35	1
valid_sources[0x03]	2004	1			T32	3		T35	2		T37	1
valid_sources[0x04]	2037	1			T22	1		T84	4		T85	1
valid_sources[0x05]	1831	1			T23	1		T35	2		T37	1
valid_sources[0x06]	2370	1			T22	2		T23	1		T37	2
valid_sources[0x07]	2340	1			T4	8		T11	5		T35	3
valid_sources[0x08]	1772	1			T4	5		T37	2		T119	1
valid_sources[0x09]	1716	1			T22	2		T17	1		T35	2
valid_sources[0x0a]	1721	1			T4	4		T22	2		T32	5
valid_sources[0x0b]	3172	1			T23	1		T84	1		T120	3
valid_sources[0x0c]	2234	1			T22	1		T35	2		T118	3
valid_sources[0x0d]	1799	1			T23	3		T38	1		T119	1
valid_sources[0x0e]	2345	1			T23	1		T35	3		T120	2
valid_sources[0x0f]	1917	1			T23	1		T37	1		T118	1
valid_sources[0x10]	1692	1			T22	1		T84	3		T119	3
valid_sources[0x11]	2211	1			T23	1		T32	7		T35	1
valid_sources[0x12]	2806	1			T11	5		T35	3		T118	4
valid_sources[0x13]	1914	1			T11	4		T23	1		T35	1
valid_sources[0x14]	1974	1			T11	5		T12	1		T17	1
valid_sources[0x15]	2700	1			T4	15		T119	2		T121	2
valid_sources[0x16]	1883	1			T22	1		T35	6		T18	1
valid_sources[0x17]	2572	1			T12	1		T118	8		T86	1
valid_sources[0x18]	1945	1			T22	2		T35	2		T85	1
valid_sources[0x19]	1720	1			T12	1		T23	1		T122	1
valid_sources[0x1a]	1928	1			T22	1		T17	1		T35	4
valid_sources[0x1b]	1836	1			T9	1		T22	1		T32	3
valid_sources[0x1c]	2183	1			T21	3		T35	3		T123	23
valid_sources[0x1d]	1939	1			T4	10		T11	3		T22	1
valid_sources[0x1e]	2786	1			T7	10		T12	1		T22	1
valid_sources[0x1f]	2634	1			T9	1		T124	21		T125	1
valid_sources[0x20]	1879	1			T11	4		T22	1		T23	1
valid_sources[0x21]	1803	1			T4	21		T23	2		T120	12
valid_sources[0x22]	3451	1			T4	4		T35	1		T118	4
valid_sources[0x23]	2046	1			T25	2		T35	1		T118	6
valid_sources[0x24]	2021	1			T35	1		T120	2		T85	1
valid_sources[0x25]	2078	1			T17	1		T35	2		T118	2
valid_sources[0x26]	1877	1			T22	2		T35	2		T126	2
valid_sources[0x27]	2272	1			T12	1		T22	2		T35	1
valid_sources[0x28]	2701	1			T23	1		T84	4		T120	1
valid_sources[0x29]	2469	1			T4	10		T22	1		T118	15
valid_sources[0x2a]	1750	1			T11	3		T17	1		T126	1
valid_sources[0x2b]	2194	1			T22	2		T118	1		T18	1
valid_sources[0x2c]	1827	1			T12	1		T35	1		T37	2
valid_sources[0x2d]	2358	1			T4	10		T17	2		T35	3
valid_sources[0x2e]	2148	1			T4	7		T120	3		T119	2
valid_sources[0x2f]	1829	1			T10	4		T17	1		T35	4
valid_sources[0x30]	2389	1			T118	5		T121	2		T127	1
valid_sources[0x31]	2621	1			T4	2		T12	1		T23	1
valid_sources[0x32]	1996	1			T11	1		T35	6		T119	1
valid_sources[0x33]	1850	1			T4	9		T35	12		T37	1
valid_sources[0x34]	2404	1			T4	14		T22	2		T23	1
valid_sources[0x35]	1971	1			T22	1		T35	1		T18	2
valid_sources[0x36]	2711	1			T12	3		T32	1		T18	1
valid_sources[0x37]	1955	1			T22	4		T128	1		T129	2
valid_sources[0x38]	1644	1			T37	1		T130	1		T121	1
valid_sources[0x39]	2248	1			T4	11		T11	15		T19	2
valid_sources[0x3a]	1769	1			T11	6		T22	1		T17	1
valid_sources[0x3b]	1774	1			T118	5		T119	2		T86	2
valid_sources[0x3c]	4166	1			T21	4		T23	2		T35	2
valid_sources[0x3d]	1817	1			T22	1		T37	1		T120	2
valid_sources[0x3e]	1712	1			T20	1		T32	5		T119	1
valid_sources[0x3f]	1899	1			T4	1		T21	2		T22	1
valid_sources[0x40]	2240	1			T11	1		T20	1		T17	1
valid_sources[0x41]	3084	1			T22	1		T35	1		T37	2
valid_sources[0x42]	2345	1			T22	2		T37	1		T84	2
valid_sources[0x43]	1791	1			T22	1		T32	1		T118	1
valid_sources[0x44]	2375	1			T22	1		T130	2		T128	4
valid_sources[0x45]	1786	1			T120	2		T85	2		T86	1
valid_sources[0x46]	2486	1			T12	1		T17	1		T18	2
valid_sources[0x47]	1801	1			T12	2		T22	1		T19	1
valid_sources[0x48]	2602	1			T22	2		T17	1		T35	4
valid_sources[0x49]	1967	1			T4	3		T35	2		T120	1
valid_sources[0x4a]	2633	1			T12	2		T35	2		T118	1
valid_sources[0x4b]	3061	1			T12	1		T23	1		T35	3
valid_sources[0x4c]	1709	1			T22	3		T17	1		T35	4
valid_sources[0x4d]	2099	1			T35	1		T86	1		T131	1
valid_sources[0x4e]	2269	1			T23	1		T17	1		T119	1
valid_sources[0x4f]	1733	1			T12	1		T23	1		T35	2
valid_sources[0x50]	2114	1			T22	1		T120	1		T121	3
valid_sources[0x51]	2924	1			T7	14		T12	2		T22	3
valid_sources[0x52]	1862	1			T4	5		T17	3		T35	5
valid_sources[0x53]	1805	1			T12	1		T22	1		T17	1
valid_sources[0x54]	1699	1			T22	1		T35	3		T118	2
valid_sources[0x55]	2099	1			T23	3		T35	2		T120	4
valid_sources[0x56]	2860	1			T10	1		T35	7		T120	1
valid_sources[0x57]	2070	1			T21	11		T17	1		T35	1
valid_sources[0x58]	1861	1			T17	1		T103	63		T39	2
valid_sources[0x59]	2294	1			T11	1		T17	1		T35	2
valid_sources[0x5a]	1783	1			T4	6		T12	2		T21	10
valid_sources[0x5b]	2039	1			T37	2		T83	1		T84	5
valid_sources[0x5c]	2507	1			T23	1		T118	1		T119	2
valid_sources[0x5d]	1836	1			T12	1		T22	1		T35	2
valid_sources[0x5e]	2067	1			T17	1		T130	1		T121	2
valid_sources[0x5f]	3883	1			T22	1		T32	4		T18	2
valid_sources[0x60]	1884	1			T120	3		T121	1		T127	1
valid_sources[0x61]	1667	1			T119	1		T127	1		T128	2
valid_sources[0x62]	1781	1			T35	7		T118	3		T120	2
valid_sources[0x63]	2674	1			T4	4		T22	1		T35	3
valid_sources[0x64]	1998	1			T4	3		T39	1		T85	1
valid_sources[0x65]	2329	1			T7	3		T12	2		T23	1
valid_sources[0x66]	1863	1			T118	1		T86	1		T121	2
valid_sources[0x67]	2099	1			T12	1		T22	2		T122	3
valid_sources[0x68]	2085	1			T37	1		T18	1		T132	1
valid_sources[0x69]	1891	1			T4	1		T11	8		T12	1
valid_sources[0x6a]	2382	1			T12	3		T23	1		T17	1
valid_sources[0x6b]	2316	1			T4	3		T12	2		T17	1
valid_sources[0x6c]	2057	1			T22	2		T35	1		T126	8
valid_sources[0x6d]	2442	1			T21	14		T22	2		T35	2
valid_sources[0x6e]	1833	1			T9	7		T22	1		T35	7
valid_sources[0x6f]	2331	1			T9	12		T12	1		T118	3
valid_sources[0x70]	2228	1			T4	3		T32	2		T37	1
valid_sources[0x71]	1832	1			T12	2		T17	1		T18	2
valid_sources[0x72]	1982	1			T4	5		T22	1		T18	2
valid_sources[0x73]	2687	1			T4	10		T12	1		T23	1
valid_sources[0x74]	1862	1			T7	6		T11	9		T21	1
valid_sources[0x75]	2032	1			T12	1		T23	1		T35	1
valid_sources[0x76]	1827	1			T11	16		T22	1		T23	1
valid_sources[0x77]	2418	1			T12	2		T35	2		T37	1
valid_sources[0x78]	2178	1			T4	2		T17	1		T35	2
valid_sources[0x79]	2376	1			T120	1		T119	1		T86	2
valid_sources[0x7a]	1930	1			T17	1		T103	11		T119	1
valid_sources[0x7b]	1807	1			T22	1		T118	10		T120	1
valid_sources[0x7c]	2102	1			T4	5		T35	2		T118	11
valid_sources[0x7d]	2496	1			T35	2		T118	3		T121	2
valid_sources[0x7e]	2090	1			T35	4		T118	1		T83	14
valid_sources[0x7f]	2204	1			T4	5		T37	1		T118	2
valid_sources[0x80]	1930	1			T35	5		T121	1		T128	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

131248

1

T4

30

T7

5

T9

8

values[0x0]

all_enables

biggest_size

192204

1

T13

18931

T14

13523

T15

18423

values[0x1]

all_enables

biggest_size

192446

1

T13

18925

T14

13583

T15

18770

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44661	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

397140

1

T2

2

T3

5

T5

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	114230	1			T1	1		T6	1		T7	32
values[0x0]	151837	1			T2	1		T3	7		T5	3
values[0x1]	175734	1			T2	4		T3	9		T5	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21839	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

419962

1

T2

4

T3

7

T5

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1679	1			T37	1		T19	1		T44	1
valid_sources[0x01]	1320	1			T133	1		T13	178		T14	120
valid_sources[0x02]	1220	1			T13	160		T134	2		T135	1
valid_sources[0x03]	1641	1			T20	5		T25	1		T27	1
valid_sources[0x04]	2032	1			T32	2		T68	1		T133	1
valid_sources[0x05]	1738	1			T136	1		T13	175		T14	95
valid_sources[0x06]	2201	1			T17	1		T26	3		T130	1
valid_sources[0x07]	1576	1			T43	2		T130	2		T125	3
valid_sources[0x08]	2018	1			T18	1		T120	11		T13	148
valid_sources[0x09]	2105	1			T17	1		T32	2		T133	1
valid_sources[0x0a]	1684	1			T26	3		T47	1		T137	1
valid_sources[0x0b]	1705	1			T19	1		T133	1		T137	1
valid_sources[0x0c]	1438	1			T18	2		T138	1		T13	164
valid_sources[0x0d]	1598	1			T138	1		T13	156		T14	112
valid_sources[0x0e]	1044	1			T124	1		T133	2		T139	3
valid_sources[0x0f]	1821	1			T7	1		T31	1		T128	8
valid_sources[0x10]	2665	1			T130	2		T13	172		T140	1
valid_sources[0x11]	2204	1			T7	2		T47	1		T13	155
valid_sources[0x12]	1460	1			T9	1		T120	28		T47	2
valid_sources[0x13]	2132	1			T17	1		T26	1		T25	1
valid_sources[0x14]	2555	1			T18	1		T136	1		T13	155
valid_sources[0x15]	1392	1			T138	2		T136	1		T13	163
valid_sources[0x16]	1413	1			T133	1		T141	1		T136	2
valid_sources[0x17]	1624	1			T133	1		T138	1		T139	1
valid_sources[0x18]	1952	1			T43	1		T31	1		T125	1
valid_sources[0x19]	1714	1			T9	1		T32	2		T37	1
valid_sources[0x1a]	1693	1			T17	1		T13	142		T142	5
valid_sources[0x1b]	2004	1			T18	1		T70	1		T13	148
valid_sources[0x1c]	1264	1			T68	1		T143	1		T47	1
valid_sources[0x1d]	1566	1			T9	2		T26	1		T13	179
valid_sources[0x1e]	1549	1			T7	1		T124	4		T141	1
valid_sources[0x1f]	1484	1			T6	1		T128	15		T129	1
valid_sources[0x20]	2180	1			T7	1		T32	1		T13	178
valid_sources[0x21]	1449	1			T32	1		T141	1		T13	136
valid_sources[0x22]	1459	1			T7	1		T12	32		T17	1
valid_sources[0x23]	2707	1			T17	1		T38	1		T139	1
valid_sources[0x24]	1329	1			T7	1		T32	1		T41	1
valid_sources[0x25]	2312	1			T3	16		T133	1		T13	160
valid_sources[0x26]	1730	1			T19	1		T85	32		T133	1
valid_sources[0x27]	1739	1			T43	1		T13	164		T144	1
valid_sources[0x28]	1858	1			T9	1		T17	1		T48	3
valid_sources[0x29]	1216	1			T9	1		T84	1		T145	1
valid_sources[0x2a]	1877	1			T20	1		T37	1		T13	172
valid_sources[0x2b]	1345	1			T32	1		T37	1		T133	1
valid_sources[0x2c]	1561	1			T7	1		T9	1		T19	1
valid_sources[0x2d]	2483	1			T32	1		T19	1		T13	162
valid_sources[0x2e]	1529	1			T130	2		T133	1		T13	143
valid_sources[0x2f]	1349	1			T9	1		T86	1		T127	1
valid_sources[0x30]	1713	1			T5	9		T31	1		T18	2
valid_sources[0x31]	1660	1			T133	1		T13	171		T134	2
valid_sources[0x32]	1822	1			T13	172		T146	96		T147	1
valid_sources[0x33]	1560	1			T47	1		T127	5		T148	1
valid_sources[0x34]	1998	1			T9	1		T26	1		T37	1
valid_sources[0x35]	2526	1			T149	1		T141	1		T136	1
valid_sources[0x36]	1548	1			T37	1		T18	1		T136	1
valid_sources[0x37]	2331	1			T138	1		T13	155		T142	3
valid_sources[0x38]	1778	1			T7	1		T37	2		T13	142
valid_sources[0x39]	1456	1			T19	1		T18	1		T130	1
valid_sources[0x3a]	1546	1			T130	7		T133	1		T13	176
valid_sources[0x3b]	2619	1			T71	2		T129	1		T13	163
valid_sources[0x3c]	1505	1			T7	1		T9	1		T37	2
valid_sources[0x3d]	1265	1			T31	1		T19	1		T13	197
valid_sources[0x3e]	1284	1			T27	2		T143	6		T125	1
valid_sources[0x3f]	975	1			T18	1		T133	2		T13	167
valid_sources[0x40]	1761	1			T84	3		T141	1		T13	162
valid_sources[0x41]	1908	1			T9	1		T41	1		T13	164
valid_sources[0x42]	2396	1			T13	170		T150	2		T135	2
valid_sources[0x43]	1435	1			T1	1		T128	4		T133	2
valid_sources[0x44]	1874	1			T84	1		T133	1		T141	1
valid_sources[0x45]	1297	1			T41	1		T124	1		T133	1
valid_sources[0x46]	1869	1			T20	2		T84	1		T71	1
valid_sources[0x47]	1896	1			T2	1		T26	2		T69	2
valid_sources[0x48]	2282	1			T9	1		T68	1		T13	170
valid_sources[0x49]	1345	1			T86	31		T13	168		T151	1
valid_sources[0x4a]	1223	1			T47	1		T129	1		T13	160
valid_sources[0x4b]	1681	1			T20	10		T130	2		T133	1
valid_sources[0x4c]	1175	1			T24	1		T21	24		T37	2
valid_sources[0x4d]	1484	1			T17	1		T136	1		T13	164
valid_sources[0x4e]	1447	1			T7	1		T17	2		T26	1
valid_sources[0x4f]	2450	1			T124	1		T141	1		T132	96
valid_sources[0x50]	2181	1			T128	7		T13	135		T142	6
valid_sources[0x51]	1177	1			T27	2		T130	1		T125	3
valid_sources[0x52]	1487	1			T133	1		T13	169		T152	1
valid_sources[0x53]	1966	1			T17	1		T38	1		T47	1
valid_sources[0x54]	1343	1			T25	1		T41	2		T153	1
valid_sources[0x55]	1814	1			T154	1		T13	148		T134	1
valid_sources[0x56]	1856	1			T19	1		T139	2		T13	133
valid_sources[0x57]	1670	1			T31	1		T120	6		T130	3
valid_sources[0x58]	1730	1			T17	1		T13	189		T135	1
valid_sources[0x59]	1691	1			T7	1		T25	1		T18	1
valid_sources[0x5a]	2239	1			T149	1		T13	178		T155	1
valid_sources[0x5b]	1456	1			T128	1		T13	190		T156	1
valid_sources[0x5c]	1978	1			T25	1		T18	1		T125	1
valid_sources[0x5d]	1242	1			T48	2		T133	1		T13	177
valid_sources[0x5e]	1907	1			T127	2		T133	1		T157	1
valid_sources[0x5f]	1690	1			T43	2		T32	1		T13	180
valid_sources[0x60]	1831	1			T9	1		T41	1		T138	1
valid_sources[0x61]	2033	1			T84	1		T13	166		T150	1
valid_sources[0x62]	1230	1			T39	20		T13	170		T135	1
valid_sources[0x63]	1856	1			T7	1		T153	8		T13	161
valid_sources[0x64]	1476	1			T20	1		T127	1		T141	1
valid_sources[0x65]	1467	1			T7	1		T32	1		T143	7
valid_sources[0x66]	1298	1			T149	1		T13	161		T147	1
valid_sources[0x67]	1670	1			T7	1		T17	1		T31	1
valid_sources[0x68]	1833	1			T13	164		T14	101		T15	169
valid_sources[0x69]	1805	1			T130	3		T129	3		T148	3
valid_sources[0x6a]	2023	1			T31	1		T19	1		T84	1
valid_sources[0x6b]	1878	1			T7	1		T18	1		T120	5
valid_sources[0x6c]	1643	1			T7	1		T19	1		T136	1
valid_sources[0x6d]	1273	1			T32	1		T86	2		T130	2
valid_sources[0x6e]	1163	1			T17	1		T19	2		T68	1
valid_sources[0x6f]	2451	1			T7	2		T17	1		T129	1
valid_sources[0x70]	2164	1			T124	1		T13	167		T158	8
valid_sources[0x71]	1963	1			T32	2		T13	156		T135	1
valid_sources[0x72]	1355	1			T25	1		T31	1		T120	16
valid_sources[0x73]	1893	1			T9	1		T84	2		T13	177
valid_sources[0x74]	2001	1			T2	1		T137	1		T13	172
valid_sources[0x75]	1999	1			T32	1		T47	1		T133	2
valid_sources[0x76]	1681	1			T9	1		T129	1		T13	167
valid_sources[0x77]	2166	1			T133	3		T149	2		T136	2
valid_sources[0x78]	1902	1			T10	38		T26	1		T37	1
valid_sources[0x79]	2123	1			T71	6		T133	1		T13	146
valid_sources[0x7a]	1461	1			T27	3		T130	1		T127	1
valid_sources[0x7b]	2031	1			T130	1		T13	141		T147	1
valid_sources[0x7c]	1542	1			T37	1		T130	1		T133	1
valid_sources[0x7d]	1820	1			T2	1		T84	1		T159	1
valid_sources[0x7e]	1506	1			T18	2		T41	1		T136	1
valid_sources[0x7f]	2097	1			T13	156		T59	22		T160	4
valid_sources[0x80]	1461	1			T19	1		T129	1		T136	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

100898

1

T6

1

T7

11

T8

1

values[0x0]

all_enables

biggest_size

148309

1

T2

1

T3

4

T5

3

values[0x1]

all_enables

biggest_size

147933

1

T2

1

T3

1

T5

2