Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

944804

1

T4

345

T7

51

T9

58

full_word

600713

1

T4

30

T7

5

T9

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1545177	1			T4	375		T7	56		T9	66
auto[TlIntgErrCmd]	124	1			T53	8		T64	3		T65	6
auto[TlIntgErrData]	94	1			T53	8		T64	3		T65	7
auto[TlIntgErrBoth]	122	1			T53	4		T64	4		T65	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

261336

1

T4

375

T7

56

T9

66

auto[1]

1284181

1

T13

127631

T14

87904

T15

127111

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	117427	1			T4	345		T7	51		T9	58
auto[TlIntgErrNone]	partial	auto[1]	827071	1			T13	82530		T14	55987		T15	82724
auto[TlIntgErrNone]	full_word	auto[0]	143759	1			T4	30		T7	5		T9	8
auto[TlIntgErrNone]	full_word	auto[1]	456920	1			T13	45101		T14	31917		T15	44387
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T53	5		T65	3		T105	2
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T53	3		T64	3		T65	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T108	1		T112	1		T109	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T65	1		T113	1		T114	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T64	2		T65	3		T105	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T53	6		T64	1		T65	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T53	1		T65	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T53	1		T115	1		T112	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T64	3		T65	3		T115	1
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T53	3		T64	1		T65	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T112	2		T109	2		T116	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T53	1		T107	2		T117	1