Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47908	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

907712

1

T2

48964

T4

7

T7

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	258209	1			T2	13000		T4	107		T7	12
values[0x0]	342448	1			T2	18430		T8	61366		T12	63798
values[0x1]	354963	1			T2	19158		T8	63133		T12	66310

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24170	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

931450

1

T2

49716

T4

68

T7

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3669	1			T2	205		T8	603		T21	1
valid_sources[0x01]	3782	1			T2	198		T8	664		T13	4
valid_sources[0x02]	3779	1			T2	217		T8	659		T21	3
valid_sources[0x03]	3501	1			T2	209		T8	673		T21	1
valid_sources[0x04]	3598	1			T2	186		T8	634		T13	1
valid_sources[0x05]	3692	1			T2	233		T8	653		T21	1
valid_sources[0x06]	4154	1			T2	202		T8	684		T65	2
valid_sources[0x07]	3715	1			T2	193		T8	697		T21	2
valid_sources[0x08]	3644	1			T2	193		T8	620		T21	2
valid_sources[0x09]	3608	1			T2	211		T8	640		T13	1
valid_sources[0x0a]	3526	1			T2	168		T8	632		T21	2
valid_sources[0x0b]	3709	1			T2	202		T8	641		T13	1
valid_sources[0x0c]	3789	1			T2	182		T8	694		T21	1
valid_sources[0x0d]	3616	1			T2	182		T8	670		T21	2
valid_sources[0x0e]	3787	1			T2	207		T8	692		T65	3
valid_sources[0x0f]	3804	1			T2	207		T8	698		T18	3
valid_sources[0x10]	3564	1			T2	195		T8	627		T18	1
valid_sources[0x11]	3793	1			T2	216		T8	680		T18	1
valid_sources[0x12]	3861	1			T2	210		T8	654		T13	1
valid_sources[0x13]	4012	1			T2	174		T8	597		T21	1
valid_sources[0x14]	3699	1			T2	201		T8	683		T21	1
valid_sources[0x15]	3803	1			T2	197		T8	668		T21	1
valid_sources[0x16]	3689	1			T2	200		T8	666		T21	1
valid_sources[0x17]	3907	1			T2	200		T8	664		T21	1
valid_sources[0x18]	3693	1			T2	166		T8	658		T21	2
valid_sources[0x19]	3801	1			T2	191		T8	701		T21	2
valid_sources[0x1a]	3934	1			T2	216		T8	621		T18	1
valid_sources[0x1b]	3626	1			T2	219		T8	592		T21	2
valid_sources[0x1c]	3946	1			T2	201		T8	660		T21	1
valid_sources[0x1d]	3653	1			T2	180		T8	633		T21	2
valid_sources[0x1e]	3811	1			T2	237		T8	662		T13	1
valid_sources[0x1f]	4075	1			T2	179		T8	664		T18	2
valid_sources[0x20]	3821	1			T2	207		T8	621		T13	1
valid_sources[0x21]	3886	1			T2	231		T8	631		T13	1
valid_sources[0x22]	3770	1			T2	192		T8	607		T21	3
valid_sources[0x23]	3479	1			T2	186		T8	580		T21	1
valid_sources[0x24]	3648	1			T2	186		T8	605		T18	1
valid_sources[0x25]	3824	1			T2	208		T8	695		T21	2
valid_sources[0x26]	3639	1			T2	194		T8	641		T21	1
valid_sources[0x27]	3639	1			T2	208		T8	645		T13	2
valid_sources[0x28]	3804	1			T2	205		T8	650		T21	2
valid_sources[0x29]	3586	1			T2	189		T8	653		T12	658
valid_sources[0x2a]	3843	1			T2	214		T8	663		T13	1
valid_sources[0x2b]	3801	1			T2	171		T8	640		T21	2
valid_sources[0x2c]	3890	1			T2	176		T8	572		T13	5
valid_sources[0x2d]	3734	1			T2	192		T8	651		T21	4
valid_sources[0x2e]	3605	1			T2	210		T8	602		T21	3
valid_sources[0x2f]	3575	1			T2	203		T8	652		T21	1
valid_sources[0x30]	3737	1			T2	193		T8	691		T21	2
valid_sources[0x31]	3548	1			T2	190		T8	685		T21	2
valid_sources[0x32]	3680	1			T2	212		T8	706		T13	1
valid_sources[0x33]	3505	1			T2	207		T8	652		T13	1
valid_sources[0x34]	3692	1			T2	217		T8	644		T13	1
valid_sources[0x35]	3716	1			T2	179		T8	689		T13	1
valid_sources[0x36]	3811	1			T2	198		T8	691		T21	4
valid_sources[0x37]	3831	1			T2	207		T8	646		T65	1
valid_sources[0x38]	3718	1			T2	208		T8	625		T65	1
valid_sources[0x39]	4363	1			T2	205		T8	670		T21	1
valid_sources[0x3a]	3632	1			T2	200		T8	629		T21	2
valid_sources[0x3b]	3800	1			T2	192		T8	661		T21	1
valid_sources[0x3c]	3691	1			T2	184		T8	642		T13	1
valid_sources[0x3d]	3619	1			T2	203		T8	632		T12	672
valid_sources[0x3e]	3505	1			T2	179		T8	611		T20	1
valid_sources[0x3f]	3890	1			T2	214		T8	756		T65	2
valid_sources[0x40]	3803	1			T2	180		T8	665		T18	1
valid_sources[0x41]	3803	1			T2	194		T8	676		T65	3
valid_sources[0x42]	3930	1			T2	218		T8	682		T13	1
valid_sources[0x43]	3617	1			T2	204		T8	629		T21	1
valid_sources[0x44]	3653	1			T2	193		T8	568		T13	2
valid_sources[0x45]	3632	1			T2	225		T8	615		T18	1
valid_sources[0x46]	3645	1			T2	191		T8	653		T13	4
valid_sources[0x47]	3633	1			T2	196		T8	611		T21	1
valid_sources[0x48]	3742	1			T2	186		T8	694		T18	1
valid_sources[0x49]	3735	1			T2	203		T8	667		T18	2
valid_sources[0x4a]	3587	1			T2	190		T8	648		T21	2
valid_sources[0x4b]	3580	1			T2	200		T8	567		T21	1
valid_sources[0x4c]	4010	1			T2	192		T8	642		T12	723
valid_sources[0x4d]	3685	1			T2	164		T8	632		T21	2
valid_sources[0x4e]	3774	1			T2	207		T8	640		T18	1
valid_sources[0x4f]	3754	1			T2	199		T8	691		T13	2
valid_sources[0x50]	3740	1			T2	196		T8	632		T12	710
valid_sources[0x51]	3755	1			T2	222		T8	634		T21	1
valid_sources[0x52]	4020	1			T2	198		T8	602		T21	1
valid_sources[0x53]	3869	1			T2	212		T8	668		T18	1
valid_sources[0x54]	3495	1			T2	184		T8	647		T65	1
valid_sources[0x55]	3738	1			T2	171		T8	663		T12	676
valid_sources[0x56]	3652	1			T2	205		T8	639		T12	712
valid_sources[0x57]	3654	1			T2	207		T8	589		T13	1
valid_sources[0x58]	3630	1			T2	203		T8	675		T11	82
valid_sources[0x59]	3725	1			T2	220		T8	677		T19	1
valid_sources[0x5a]	3878	1			T2	206		T8	639		T21	1
valid_sources[0x5b]	3577	1			T2	176		T8	657		T21	2
valid_sources[0x5c]	3769	1			T2	175		T8	633		T21	3
valid_sources[0x5d]	3666	1			T2	196		T8	639		T13	2
valid_sources[0x5e]	3598	1			T2	167		T8	635		T21	3
valid_sources[0x5f]	4086	1			T2	200		T8	668		T13	1
valid_sources[0x60]	3753	1			T2	214		T8	674		T21	2
valid_sources[0x61]	3733	1			T2	197		T8	676		T11	10
valid_sources[0x62]	3814	1			T2	191		T8	653		T21	3
valid_sources[0x63]	3958	1			T2	192		T8	628		T21	2
valid_sources[0x64]	3551	1			T2	223		T8	646		T21	2
valid_sources[0x65]	3744	1			T2	202		T8	656		T21	3
valid_sources[0x66]	4367	1			T2	203		T8	691		T13	1
valid_sources[0x67]	3928	1			T2	193		T8	616		T18	1
valid_sources[0x68]	3721	1			T2	224		T8	657		T13	1
valid_sources[0x69]	3719	1			T2	211		T8	650		T21	3
valid_sources[0x6a]	3946	1			T2	218		T8	639		T13	1
valid_sources[0x6b]	3588	1			T2	176		T8	651		T11	20
valid_sources[0x6c]	3599	1			T2	171		T8	638		T13	1
valid_sources[0x6d]	3648	1			T2	218		T8	640		T18	3
valid_sources[0x6e]	3770	1			T2	214		T8	655		T21	3
valid_sources[0x6f]	3695	1			T2	187		T8	617		T20	2
valid_sources[0x70]	3734	1			T2	178		T8	632		T65	2
valid_sources[0x71]	3828	1			T2	192		T8	684		T11	19
valid_sources[0x72]	3900	1			T2	208		T8	671		T13	2
valid_sources[0x73]	3897	1			T2	211		T8	650		T21	2
valid_sources[0x74]	3694	1			T2	202		T8	638		T18	1
valid_sources[0x75]	3594	1			T2	214		T8	622		T12	674
valid_sources[0x76]	3710	1			T2	203		T8	627		T65	1
valid_sources[0x77]	3640	1			T2	167		T8	599		T21	3
valid_sources[0x78]	3772	1			T2	199		T8	621		T21	2
valid_sources[0x79]	3768	1			T2	177		T8	687		T13	1
valid_sources[0x7a]	3551	1			T2	198		T8	637		T13	2
valid_sources[0x7b]	3986	1			T2	180		T8	627		T21	1
valid_sources[0x7c]	3839	1			T2	197		T8	625		T21	1
valid_sources[0x7d]	3561	1			T2	198		T8	618		T12	648
valid_sources[0x7e]	3968	1			T2	185		T8	675		T13	2
valid_sources[0x7f]	3610	1			T2	196		T8	652		T21	1
valid_sources[0x80]	3819	1			T2	208		T8	697		T65	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

229029

1

T2

12326

T4

7

T7

12

values[0x0]

all_enables

biggest_size

339407

1

T2

18265

T8

60807

T12

63242

values[0x1]

all_enables

biggest_size

339276

1

T2

18373

T8

60440

T12

63366

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	71745	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

699421

1

T1

9

T2

39734

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	195722	1			T1	29		T2	10858		T5	1
values[0x0]	266557	1			T2	15059		T3	5		T8	46926
values[0x1]	308887	1			T2	17671		T3	5		T8	54565

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

737710

1

T1

13

T2

41899

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2865	1			T2	163		T8	448		T12	515
valid_sources[0x01]	3153	1			T2	166		T8	686		T12	523
valid_sources[0x02]	3063	1			T2	140		T8	636		T12	521
valid_sources[0x03]	3254	1			T2	163		T8	801		T48	2
valid_sources[0x04]	3358	1			T2	164		T8	752		T16	1
valid_sources[0x05]	3228	1			T2	159		T8	711		T16	2
valid_sources[0x06]	3239	1			T2	185		T8	786		T12	553
valid_sources[0x07]	3154	1			T2	133		T8	751		T12	552
valid_sources[0x08]	2974	1			T2	160		T8	478		T20	1
valid_sources[0x09]	3198	1			T2	160		T8	625		T12	578
valid_sources[0x0a]	2890	1			T2	177		T8	554		T16	1
valid_sources[0x0b]	2733	1			T2	181		T8	220		T12	546
valid_sources[0x0c]	3018	1			T2	175		T8	508		T12	519
valid_sources[0x0d]	3019	1			T2	179		T7	1		T8	505
valid_sources[0x0e]	2617	1			T2	191		T8	142		T61	1
valid_sources[0x0f]	2950	1			T2	151		T8	413		T12	553
valid_sources[0x10]	2901	1			T2	178		T8	368		T12	555
valid_sources[0x11]	2682	1			T2	177		T7	1		T8	253
valid_sources[0x12]	2932	1			T2	162		T8	214		T12	529
valid_sources[0x13]	3059	1			T2	164		T8	546		T12	543
valid_sources[0x14]	2901	1			T2	163		T8	365		T61	1
valid_sources[0x15]	3028	1			T1	1		T2	180		T8	416
valid_sources[0x16]	2899	1			T2	168		T8	460		T13	1
valid_sources[0x17]	3472	1			T2	168		T8	997		T13	2
valid_sources[0x18]	2720	1			T2	169		T8	409		T12	541
valid_sources[0x19]	2992	1			T2	146		T8	524		T13	1
valid_sources[0x1a]	2982	1			T2	158		T8	607		T12	537
valid_sources[0x1b]	3009	1			T2	167		T8	654		T16	1
valid_sources[0x1c]	2943	1			T2	177		T8	463		T12	541
valid_sources[0x1d]	3363	1			T2	169		T8	790		T12	577
valid_sources[0x1e]	2775	1			T2	183		T8	361		T12	576
valid_sources[0x1f]	2712	1			T1	1		T2	159		T8	205
valid_sources[0x20]	2867	1			T2	178		T8	388		T12	532
valid_sources[0x21]	2957	1			T2	173		T8	558		T12	565
valid_sources[0x22]	2908	1			T2	165		T8	386		T12	551
valid_sources[0x23]	3058	1			T2	179		T8	673		T12	536
valid_sources[0x24]	2729	1			T2	162		T8	261		T20	4
valid_sources[0x25]	2991	1			T2	187		T8	382		T12	532
valid_sources[0x26]	2789	1			T2	176		T8	403		T12	565
valid_sources[0x27]	3105	1			T2	183		T8	325		T16	1
valid_sources[0x28]	3065	1			T2	152		T8	679		T12	516
valid_sources[0x29]	2945	1			T2	157		T8	335		T12	531
valid_sources[0x2a]	2787	1			T2	168		T8	344		T12	543
valid_sources[0x2b]	3213	1			T2	148		T8	593		T12	533
valid_sources[0x2c]	3615	1			T2	169		T8	1012		T12	577
valid_sources[0x2d]	2991	1			T1	1		T2	196		T8	367
valid_sources[0x2e]	2942	1			T2	200		T8	500		T12	553
valid_sources[0x2f]	2831	1			T2	172		T8	317		T19	1
valid_sources[0x30]	2828	1			T2	177		T8	330		T13	1
valid_sources[0x31]	2666	1			T1	2		T2	177		T8	360
valid_sources[0x32]	3422	1			T2	169		T8	843		T12	526
valid_sources[0x33]	3081	1			T2	166		T8	485		T12	561
valid_sources[0x34]	2827	1			T2	175		T8	354		T19	3
valid_sources[0x35]	2770	1			T2	160		T8	158		T13	1
valid_sources[0x36]	3620	1			T2	202		T8	1114		T13	2
valid_sources[0x37]	2981	1			T2	171		T8	321		T13	1
valid_sources[0x38]	2860	1			T2	166		T8	213		T12	507
valid_sources[0x39]	2800	1			T2	194		T8	218		T12	532
valid_sources[0x3a]	3177	1			T2	157		T8	591		T12	521
valid_sources[0x3b]	2879	1			T2	172		T8	320		T12	497
valid_sources[0x3c]	3170	1			T1	1		T2	151		T8	571
valid_sources[0x3d]	2747	1			T1	1		T2	174		T7	1
valid_sources[0x3e]	2957	1			T2	185		T8	482		T12	527
valid_sources[0x3f]	2846	1			T1	1		T2	169		T8	484
valid_sources[0x40]	3025	1			T2	170		T8	551		T12	553
valid_sources[0x41]	2965	1			T2	165		T8	461		T12	523
valid_sources[0x42]	2951	1			T2	173		T8	551		T12	549
valid_sources[0x43]	2545	1			T1	1		T2	163		T3	10
valid_sources[0x44]	3127	1			T2	171		T8	520		T61	1
valid_sources[0x45]	2957	1			T2	160		T6	1		T8	610
valid_sources[0x46]	3210	1			T2	185		T8	503		T16	2
valid_sources[0x47]	3070	1			T2	165		T8	596		T16	1
valid_sources[0x48]	3308	1			T2	162		T8	921		T12	534
valid_sources[0x49]	3227	1			T2	176		T8	781		T12	501
valid_sources[0x4a]	3014	1			T2	146		T8	498		T25	16
valid_sources[0x4b]	2984	1			T2	161		T8	608		T20	1
valid_sources[0x4c]	3087	1			T1	1		T2	173		T8	636
valid_sources[0x4d]	3094	1			T1	1		T2	175		T8	581
valid_sources[0x4e]	2844	1			T2	180		T7	3		T8	404
valid_sources[0x4f]	3086	1			T2	180		T8	654		T12	541
valid_sources[0x50]	3143	1			T2	169		T8	753		T19	1
valid_sources[0x51]	2970	1			T2	169		T8	340		T12	548
valid_sources[0x52]	2907	1			T2	181		T8	373		T12	566
valid_sources[0x53]	3067	1			T2	185		T8	659		T12	518
valid_sources[0x54]	3214	1			T2	181		T8	600		T12	552
valid_sources[0x55]	2844	1			T2	168		T8	429		T12	542
valid_sources[0x56]	2656	1			T1	1		T2	163		T8	281
valid_sources[0x57]	2628	1			T2	174		T8	355		T13	1
valid_sources[0x58]	2434	1			T2	167		T8	226		T12	507
valid_sources[0x59]	2976	1			T2	165		T8	648		T12	548
valid_sources[0x5a]	2915	1			T2	164		T8	540		T12	535
valid_sources[0x5b]	3269	1			T1	1		T2	181		T8	806
valid_sources[0x5c]	3049	1			T2	156		T8	576		T12	552
valid_sources[0x5d]	2761	1			T2	165		T8	353		T12	519
valid_sources[0x5e]	3101	1			T1	1		T2	175		T8	528
valid_sources[0x5f]	3267	1			T2	180		T8	708		T12	545
valid_sources[0x60]	3153	1			T2	165		T8	630		T12	549
valid_sources[0x61]	2667	1			T2	158		T8	337		T16	2
valid_sources[0x62]	2776	1			T2	177		T8	302		T19	1
valid_sources[0x63]	2974	1			T2	192		T7	1		T8	437
valid_sources[0x64]	3100	1			T2	177		T8	561		T12	532
valid_sources[0x65]	2898	1			T2	210		T8	448		T12	534
valid_sources[0x66]	2926	1			T2	147		T8	502		T12	542
valid_sources[0x67]	2766	1			T2	162		T8	298		T12	534
valid_sources[0x68]	2952	1			T2	178		T8	607		T12	564
valid_sources[0x69]	3333	1			T2	168		T8	716		T12	548
valid_sources[0x6a]	2934	1			T2	154		T7	1		T8	395
valid_sources[0x6b]	3192	1			T2	169		T7	3		T8	702
valid_sources[0x6c]	3396	1			T2	169		T8	872		T13	1
valid_sources[0x6d]	2962	1			T2	168		T8	469		T12	525
valid_sources[0x6e]	3040	1			T2	164		T8	630		T16	1
valid_sources[0x6f]	3256	1			T1	1		T2	172		T7	1
valid_sources[0x70]	3073	1			T2	182		T7	1		T8	546
valid_sources[0x71]	3036	1			T2	154		T8	566		T13	1
valid_sources[0x72]	3191	1			T1	1		T2	176		T8	618
valid_sources[0x73]	2957	1			T2	142		T8	411		T12	559
valid_sources[0x74]	2868	1			T2	155		T8	442		T12	550
valid_sources[0x75]	3209	1			T2	170		T8	741		T16	1
valid_sources[0x76]	2974	1			T1	2		T2	155		T8	455
valid_sources[0x77]	2894	1			T2	178		T8	244		T13	1
valid_sources[0x78]	2930	1			T2	177		T8	442		T19	1
valid_sources[0x79]	3202	1			T2	160		T8	626		T12	549
valid_sources[0x7a]	3035	1			T2	177		T8	691		T12	529
valid_sources[0x7b]	2736	1			T2	160		T8	346		T12	507
valid_sources[0x7c]	2879	1			T2	148		T8	514		T20	2
valid_sources[0x7d]	3437	1			T2	192		T8	909		T12	610
valid_sources[0x7e]	3275	1			T2	163		T8	715		T12	509
valid_sources[0x7f]	3024	1			T2	167		T8	551		T12	493
valid_sources[0x80]	3445	1			T2	173		T8	877		T12	559

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

177439

1

T1

9

T2

10092

T5

1

values[0x0]

all_enables

biggest_size

260866

1

T2

14744

T3

2

T8

46088

values[0x1]

all_enables

biggest_size

261116

1

T2

14898

T8

46307

T9

2