Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1668704

1

T2

88331

T4

100

T8

296433

full_word

1058290

1

T2

57007

T4

7

T7

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2726684	1			T2	145338		T4	107		T7	8
auto[TlIntgErrCmd]	110	1			T55	4		T56	1		T57	7
auto[TlIntgErrData]	89	1			T55	4		T56	3		T57	2
auto[TlIntgErrBoth]	111	1			T55	2		T56	6		T57	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

439098

1

T2

23145

T4

107

T7

8

auto[1]

2287896

1

T2

122193

T8

411031

T12

428704

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	188402	1			T2	9650		T4	100		T8	29931
auto[TlIntgErrNone]	partial	auto[1]	1480018	1			T2	78681		T8	266502		T12	277816
auto[TlIntgErrNone]	full_word	auto[0]	250555	1			T2	13495		T4	7		T7	8
auto[TlIntgErrNone]	full_word	auto[1]	807709	1			T2	43512		T8	144529		T12	150888
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T56	1		T57	5		T105	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T55	3		T57	2		T105	4
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T55	1		T106	1		T107	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T55	2		T56	1		T106	2
auto[TlIntgErrData]	partial	auto[1]	39	1			T55	2		T56	1		T57	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T107	2		T108	1		T109	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T56	1		T108	1		T110	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T55	2		T56	4		T106	1
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T56	2		T57	1		T106	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T111	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T106	1		T112	1		T111	1