Unified Coverage Report :: Module :: rom_ctrl_scrambled_rom

Module : rom_ctrl_scrambled_rom

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	75.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_scrambled_rom.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_rom_scramble_enabled.u_rom	87.50	75.00					100.00

---

Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	75.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	88.24		100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.05	100.00	98.28	97.26		100.00	69.70	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prince	100.00			100.00
u_rom	94.44	83.33				100.00	100.00
u_seed_anchor	0.00	0.00
u_sp_addr	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl_scrambled_rom

	Line No.	Total	Covered	Percent
TOTAL		4	3	75.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	0	0
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	153	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_scrambled_rom.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_scrambled_rom.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
81	0	1
82		unreachable
128	1	1
149	1	1
153	1	1

---

Assert Coverage for Module : rom_ctrl_scrambled_rom

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DepthPow2Check_A	312	312	0	0
MaxWidthCheck_A	312	312	0	0

DepthPow2Check_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312	312	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MaxWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312	312	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0