Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1323045

1

T2

325

T4

95

T10

51

full_word

838220

1

T2

31

T4

12

T10

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2160945	1			T2	356		T4	107		T10	54
auto[TlIntgErrCmd]	112	1			T62	6		T63	7		T64	1
auto[TlIntgErrData]	106	1			T62	6		T63	7		T64	4
auto[TlIntgErrBoth]	102	1			T62	8		T63	6		T64	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

356485

1

T2

356

T4

107

T10

54

auto[1]

1804780

1

T16

110286

T17

80516

T18

152287

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	156811	1			T2	325		T4	95		T10	51
auto[TlIntgErrNone]	partial	auto[1]	1165950	1			T16	72627		T17	51277		T18	100261
auto[TlIntgErrNone]	full_word	auto[0]	199524	1			T2	31		T4	12		T10	3
auto[TlIntgErrNone]	full_word	auto[1]	638660	1			T16	37659		T17	29239		T18	52026
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T62	4		T63	4		T109	3
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T62	2		T63	1		T64	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T63	1		T119	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T63	1		T109	1		T121	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T63	4		T64	3		T109	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T62	5		T63	1		T64	1
auto[TlIntgErrData]	full_word	auto[0]	10	1			T63	1		T110	1		T121	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T62	1		T63	1		T109	2
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T62	4		T63	1		T64	2
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T62	4		T63	5		T64	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T113	1		T118	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T109	1		T116	1		T111	1