Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43119	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

774281

1

T1

4

T2

18

T4

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	222647	1			T1	87		T2	185		T4	88
values[0x0]	292148	1			T5	17431		T9	56818		T11	43694
values[0x1]	302605	1			T5	17957		T9	58759		T11	45157

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21448	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

795952

1

T1

49

T2

106

T4

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2643	1			T1	1		T5	163		T9	568
valid_sources[0x01]	3262	1			T5	208		T7	1		T9	594
valid_sources[0x02]	2904	1			T5	174		T7	1		T9	549
valid_sources[0x03]	2897	1			T5	167		T9	630		T10	1
valid_sources[0x04]	3523	1			T5	241		T9	630		T10	1
valid_sources[0x05]	2792	1			T5	198		T9	626		T116	2
valid_sources[0x06]	3285	1			T5	183		T9	604		T13	1
valid_sources[0x07]	2748	1			T5	242		T9	627		T116	2
valid_sources[0x08]	3285	1			T5	225		T9	631		T13	2
valid_sources[0x09]	2779	1			T5	148		T9	679		T116	1
valid_sources[0x0a]	2873	1			T5	207		T9	650		T42	1
valid_sources[0x0b]	3454	1			T5	169		T9	640		T42	1
valid_sources[0x0c]	2845	1			T5	127		T7	2		T9	597
valid_sources[0x0d]	2890	1			T5	260		T7	1		T9	587
valid_sources[0x0e]	3177	1			T5	161		T9	596		T116	2
valid_sources[0x0f]	3596	1			T5	179		T9	596		T42	1
valid_sources[0x10]	2924	1			T5	237		T7	2		T9	647
valid_sources[0x11]	2810	1			T5	271		T9	619		T13	2
valid_sources[0x12]	3679	1			T1	1		T5	174		T7	1
valid_sources[0x13]	3712	1			T4	22		T5	153		T7	1
valid_sources[0x14]	2667	1			T5	161		T9	579		T42	1
valid_sources[0x15]	3101	1			T5	143		T7	2		T9	590
valid_sources[0x16]	2773	1			T1	1		T5	214		T9	561
valid_sources[0x17]	3280	1			T5	153		T9	589		T10	1
valid_sources[0x18]	2768	1			T5	146		T9	615		T117	5
valid_sources[0x19]	2993	1			T5	255		T7	1		T9	621
valid_sources[0x1a]	3228	1			T5	151		T9	609		T42	1
valid_sources[0x1b]	3250	1			T5	213		T9	591		T116	1
valid_sources[0x1c]	3067	1			T5	170		T9	622		T42	1
valid_sources[0x1d]	3047	1			T1	1		T5	199		T7	1
valid_sources[0x1e]	3101	1			T1	2		T5	210		T9	622
valid_sources[0x1f]	4576	1			T5	151		T9	587		T42	2
valid_sources[0x20]	3528	1			T5	165		T9	597		T10	1
valid_sources[0x21]	2707	1			T5	171		T7	1		T9	580
valid_sources[0x22]	3514	1			T5	200		T9	547		T13	1
valid_sources[0x23]	3419	1			T5	228		T9	654		T10	1
valid_sources[0x24]	2963	1			T2	39		T5	185		T9	574
valid_sources[0x25]	3477	1			T1	2		T5	185		T7	1
valid_sources[0x26]	3654	1			T5	234		T7	1		T9	643
valid_sources[0x27]	3026	1			T5	185		T9	604		T44	2
valid_sources[0x28]	2549	1			T5	144		T9	568		T98	3
valid_sources[0x29]	4101	1			T5	134		T7	1		T9	574
valid_sources[0x2a]	2914	1			T5	173		T7	2		T9	620
valid_sources[0x2b]	3525	1			T5	224		T9	586		T43	2
valid_sources[0x2c]	2884	1			T1	1		T5	145		T9	555
valid_sources[0x2d]	2753	1			T5	144		T7	1		T9	634
valid_sources[0x2e]	2968	1			T5	174		T7	2		T9	610
valid_sources[0x2f]	2803	1			T1	3		T5	187		T7	1
valid_sources[0x30]	2923	1			T5	129		T9	575		T42	2
valid_sources[0x31]	3148	1			T5	230		T9	584		T13	3
valid_sources[0x32]	3199	1			T5	181		T7	1		T9	559
valid_sources[0x33]	2700	1			T5	137		T9	599		T10	2
valid_sources[0x34]	3226	1			T5	197		T7	1		T9	624
valid_sources[0x35]	2893	1			T1	2		T4	21		T5	190
valid_sources[0x36]	3215	1			T5	132		T9	569		T42	1
valid_sources[0x37]	3502	1			T5	313		T9	560		T45	4
valid_sources[0x38]	2773	1			T5	159		T7	2		T9	585
valid_sources[0x39]	2854	1			T5	213		T9	635		T44	3
valid_sources[0x3a]	3534	1			T1	1		T5	159		T7	1
valid_sources[0x3b]	2964	1			T2	14		T5	216		T9	601
valid_sources[0x3c]	2708	1			T5	192		T9	621		T43	3
valid_sources[0x3d]	2682	1			T5	145		T9	661		T77	2
valid_sources[0x3e]	3997	1			T5	257		T9	659		T42	2
valid_sources[0x3f]	2930	1			T5	250		T7	1		T9	634
valid_sources[0x40]	2748	1			T1	3		T5	175		T7	1
valid_sources[0x41]	3200	1			T5	168		T9	649		T13	1
valid_sources[0x42]	2877	1			T5	141		T9	641		T45	2
valid_sources[0x43]	3948	1			T5	194		T9	582		T13	2
valid_sources[0x44]	2752	1			T5	189		T9	582		T43	1
valid_sources[0x45]	2678	1			T5	218		T7	1		T9	549
valid_sources[0x46]	2814	1			T5	200		T9	632		T10	1
valid_sources[0x47]	3603	1			T1	2		T5	151		T9	631
valid_sources[0x48]	3229	1			T5	153		T7	1		T9	628
valid_sources[0x49]	2831	1			T5	169		T9	564		T10	1
valid_sources[0x4a]	4091	1			T5	239		T9	658		T10	1
valid_sources[0x4b]	3251	1			T5	210		T9	598		T13	2
valid_sources[0x4c]	2707	1			T5	171		T9	590		T13	2
valid_sources[0x4d]	3100	1			T5	193		T9	593		T43	1
valid_sources[0x4e]	3710	1			T5	145		T9	676		T13	9
valid_sources[0x4f]	3247	1			T5	197		T9	597		T10	1
valid_sources[0x50]	3634	1			T5	188		T9	669		T42	2
valid_sources[0x51]	3854	1			T5	162		T7	1		T9	550
valid_sources[0x52]	3126	1			T5	172		T7	1		T9	560
valid_sources[0x53]	2812	1			T5	203		T9	597		T13	1
valid_sources[0x54]	3133	1			T5	172		T9	614		T13	1
valid_sources[0x55]	2860	1			T5	176		T9	639		T12	1
valid_sources[0x56]	3384	1			T1	3		T5	167		T9	631
valid_sources[0x57]	2593	1			T5	152		T9	586		T13	1
valid_sources[0x58]	3558	1			T5	151		T7	1		T9	618
valid_sources[0x59]	3042	1			T5	150		T7	1		T9	572
valid_sources[0x5a]	3002	1			T5	210		T7	2		T9	575
valid_sources[0x5b]	2830	1			T5	203		T9	598		T13	7
valid_sources[0x5c]	4221	1			T5	206		T9	612		T14	3
valid_sources[0x5d]	2813	1			T5	183		T7	1		T9	618
valid_sources[0x5e]	3503	1			T1	3		T5	178		T9	595
valid_sources[0x5f]	2976	1			T5	204		T7	1		T9	637
valid_sources[0x60]	3371	1			T5	197		T7	1		T9	591
valid_sources[0x61]	3125	1			T5	229		T7	1		T9	607
valid_sources[0x62]	5098	1			T5	180		T7	1		T9	608
valid_sources[0x63]	3701	1			T5	241		T9	585		T42	2
valid_sources[0x64]	3064	1			T5	164		T9	659		T13	2
valid_sources[0x65]	2931	1			T1	2		T5	185		T9	620
valid_sources[0x66]	2947	1			T5	146		T9	610		T43	2
valid_sources[0x67]	3178	1			T5	202		T9	647		T42	8
valid_sources[0x68]	3150	1			T5	202		T7	1		T9	640
valid_sources[0x69]	2940	1			T5	201		T9	539		T42	2
valid_sources[0x6a]	2809	1			T5	183		T7	1		T9	544
valid_sources[0x6b]	3099	1			T5	137		T9	563		T14	2
valid_sources[0x6c]	3353	1			T1	2		T5	153		T9	587
valid_sources[0x6d]	2839	1			T5	226		T9	540		T42	2
valid_sources[0x6e]	4044	1			T1	2		T5	190		T7	1
valid_sources[0x6f]	3019	1			T5	188		T9	527		T12	1
valid_sources[0x70]	4609	1			T5	215		T7	1		T9	644
valid_sources[0x71]	2971	1			T5	175		T9	629		T42	6
valid_sources[0x72]	3341	1			T5	179		T9	544		T13	1
valid_sources[0x73]	3421	1			T1	1		T5	258		T9	636
valid_sources[0x74]	2922	1			T1	2		T5	167		T9	570
valid_sources[0x75]	2770	1			T5	226		T9	563		T42	2
valid_sources[0x76]	2999	1			T5	170		T9	521		T42	5
valid_sources[0x77]	2905	1			T5	214		T9	603		T13	2
valid_sources[0x78]	3089	1			T5	170		T9	600		T43	2
valid_sources[0x79]	2983	1			T1	5		T5	147		T9	580
valid_sources[0x7a]	3562	1			T1	1		T5	121		T7	1
valid_sources[0x7b]	2942	1			T5	195		T9	612		T13	1
valid_sources[0x7c]	2706	1			T5	228		T9	547		T43	1
valid_sources[0x7d]	3757	1			T1	2		T5	197		T9	581
valid_sources[0x7e]	2941	1			T5	200		T9	591		T98	14
valid_sources[0x7f]	3243	1			T5	205		T9	553		T42	1
valid_sources[0x80]	2913	1			T5	252		T9	621		T13	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

195546

1

T1

4

T2

18

T4

10

values[0x0]

all_enables

biggest_size

289603

1

T5

17284

T9

56312

T11

43287

values[0x1]

all_enables

biggest_size

289132

1

T5

17127

T9

56273

T11

43125

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

599117

1

T1

21

T3

2

T5

36379

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	167894	1			T1	32		T5	9943		T7	32
values[0x0]	229030	1			T3	7		T5	13867		T6	1
values[0x1]	264795	1			T3	6		T5	15813		T9	51462

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29371	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

632348

1

T1

25

T3

3

T5

38182

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2660	1			T5	109		T9	544		T12	12
valid_sources[0x01]	2537	1			T5	141		T9	521		T42	3
valid_sources[0x02]	2093	1			T5	97		T9	516		T42	1
valid_sources[0x03]	2092	1			T5	115		T9	457		T13	1
valid_sources[0x04]	3150	1			T5	146		T9	520		T10	1
valid_sources[0x05]	2904	1			T5	109		T9	479		T14	4
valid_sources[0x06]	1867	1			T5	128		T9	495		T13	1
valid_sources[0x07]	2303	1			T5	160		T9	508		T10	1
valid_sources[0x08]	2945	1			T5	204		T9	494		T77	1
valid_sources[0x09]	2438	1			T5	151		T9	483		T43	11
valid_sources[0x0a]	2199	1			T5	162		T9	451		T98	3
valid_sources[0x0b]	2272	1			T5	109		T9	461		T44	3
valid_sources[0x0c]	2118	1			T5	251		T9	422		T80	4
valid_sources[0x0d]	2267	1			T5	211		T9	543		T13	1
valid_sources[0x0e]	2036	1			T5	163		T9	438		T13	1
valid_sources[0x0f]	3618	1			T5	151		T9	560		T42	1
valid_sources[0x10]	2893	1			T5	158		T9	492		T13	1
valid_sources[0x11]	2216	1			T5	156		T9	567		T80	1
valid_sources[0x12]	3056	1			T5	89		T9	497		T118	1
valid_sources[0x13]	1932	1			T5	109		T8	2		T9	529
valid_sources[0x14]	2515	1			T5	171		T9	568		T13	1
valid_sources[0x15]	2857	1			T5	109		T8	1		T9	536
valid_sources[0x16]	2218	1			T5	187		T9	511		T98	1
valid_sources[0x17]	2169	1			T5	180		T9	543		T13	1
valid_sources[0x18]	2765	1			T5	153		T9	468		T42	1
valid_sources[0x19]	1878	1			T5	128		T8	3		T9	445
valid_sources[0x1a]	3090	1			T5	140		T8	1		T9	494
valid_sources[0x1b]	2381	1			T5	116		T9	445		T20	1
valid_sources[0x1c]	3398	1			T5	99		T9	589		T13	1
valid_sources[0x1d]	2008	1			T5	151		T9	454		T119	4
valid_sources[0x1e]	2210	1			T5	139		T9	487		T13	1
valid_sources[0x1f]	2726	1			T5	179		T9	454		T11	277
valid_sources[0x20]	2920	1			T5	159		T9	531		T120	1
valid_sources[0x21]	3205	1			T5	156		T9	521		T42	2
valid_sources[0x22]	2387	1			T5	242		T9	503		T11	453
valid_sources[0x23]	2849	1			T5	165		T9	513		T42	1
valid_sources[0x24]	3698	1			T5	176		T9	481		T13	1
valid_sources[0x25]	2719	1			T5	184		T9	503		T13	2
valid_sources[0x26]	2620	1			T5	111		T9	482		T13	1
valid_sources[0x27]	2884	1			T5	105		T9	479		T98	1
valid_sources[0x28]	2484	1			T5	254		T9	510		T13	1
valid_sources[0x29]	2796	1			T5	199		T9	466		T11	724
valid_sources[0x2a]	1747	1			T5	127		T9	516		T15	1
valid_sources[0x2b]	3283	1			T5	152		T9	507		T44	1
valid_sources[0x2c]	2914	1			T5	117		T9	475		T121	1
valid_sources[0x2d]	1904	1			T5	90		T9	484		T15	1
valid_sources[0x2e]	2336	1			T5	147		T9	441		T13	1
valid_sources[0x2f]	3034	1			T5	184		T8	1		T9	546
valid_sources[0x30]	2221	1			T5	168		T9	520		T42	6
valid_sources[0x31]	2342	1			T5	218		T9	486		T10	1
valid_sources[0x32]	3518	1			T5	145		T9	490		T13	1
valid_sources[0x33]	2678	1			T5	102		T9	518		T119	1
valid_sources[0x34]	2184	1			T5	120		T9	475		T98	1
valid_sources[0x35]	3052	1			T5	107		T9	424		T38	3
valid_sources[0x36]	2201	1			T5	132		T9	466		T98	1
valid_sources[0x37]	2156	1			T5	102		T9	474		T13	1
valid_sources[0x38]	2535	1			T5	102		T9	504		T10	1
valid_sources[0x39]	2551	1			T5	128		T9	451		T98	2
valid_sources[0x3a]	1897	1			T5	130		T8	2		T9	437
valid_sources[0x3b]	2164	1			T5	170		T9	519		T79	1
valid_sources[0x3c]	2829	1			T5	195		T9	506		T122	4
valid_sources[0x3d]	3100	1			T5	211		T9	459		T117	2
valid_sources[0x3e]	2510	1			T5	160		T9	464		T98	2
valid_sources[0x3f]	2719	1			T5	125		T8	1		T9	499
valid_sources[0x40]	2230	1			T5	83		T9	498		T13	1
valid_sources[0x41]	2404	1			T5	167		T9	483		T77	2
valid_sources[0x42]	2579	1			T5	291		T9	435		T98	1
valid_sources[0x43]	2420	1			T5	130		T8	1		T9	540
valid_sources[0x44]	2763	1			T3	6		T5	186		T9	421
valid_sources[0x45]	2821	1			T5	151		T8	1		T9	586
valid_sources[0x46]	2472	1			T5	118		T9	491		T98	3
valid_sources[0x47]	2479	1			T5	132		T9	511		T11	35
valid_sources[0x48]	2513	1			T5	186		T9	570		T42	3
valid_sources[0x49]	2257	1			T5	221		T9	498		T13	2
valid_sources[0x4a]	2356	1			T5	185		T9	498		T98	2
valid_sources[0x4b]	2845	1			T5	170		T8	2		T9	489
valid_sources[0x4c]	2836	1			T5	288		T9	478		T77	1
valid_sources[0x4d]	2048	1			T5	154		T8	1		T9	490
valid_sources[0x4e]	3012	1			T5	156		T9	487		T13	1
valid_sources[0x4f]	2760	1			T5	148		T9	494		T13	2
valid_sources[0x50]	2490	1			T5	62		T8	1		T9	581
valid_sources[0x51]	3575	1			T5	145		T9	548		T42	12
valid_sources[0x52]	2127	1			T5	182		T9	496		T98	2
valid_sources[0x53]	2319	1			T5	128		T9	497		T13	1
valid_sources[0x54]	2628	1			T5	116		T9	460		T120	1
valid_sources[0x55]	2600	1			T5	202		T9	434		T13	1
valid_sources[0x56]	2721	1			T5	176		T8	1		T9	445
valid_sources[0x57]	2259	1			T5	191		T8	1		T9	502
valid_sources[0x58]	3470	1			T5	176		T9	479		T98	1
valid_sources[0x59]	4279	1			T5	182		T9	450		T42	1
valid_sources[0x5a]	2170	1			T5	152		T9	496		T42	6
valid_sources[0x5b]	2070	1			T5	200		T9	505		T13	1
valid_sources[0x5c]	2795	1			T5	96		T9	461		T10	3
valid_sources[0x5d]	3030	1			T5	153		T9	488		T40	5
valid_sources[0x5e]	2198	1			T5	95		T8	1		T9	538
valid_sources[0x5f]	2435	1			T5	239		T9	499		T118	1
valid_sources[0x60]	2507	1			T5	156		T9	482		T98	2
valid_sources[0x61]	2520	1			T5	184		T9	473		T42	1
valid_sources[0x62]	2665	1			T5	231		T9	457		T13	1
valid_sources[0x63]	2529	1			T5	129		T9	511		T42	2
valid_sources[0x64]	3137	1			T5	174		T9	490		T98	3
valid_sources[0x65]	1865	1			T5	170		T9	498		T10	2
valid_sources[0x66]	3555	1			T5	113		T9	515		T98	5
valid_sources[0x67]	2131	1			T5	165		T9	500		T13	2
valid_sources[0x68]	2631	1			T5	184		T9	441		T11	657
valid_sources[0x69]	2435	1			T5	122		T9	435		T13	1
valid_sources[0x6a]	1842	1			T5	82		T9	505		T42	2
valid_sources[0x6b]	1819	1			T5	188		T9	496		T123	3
valid_sources[0x6c]	4182	1			T5	136		T9	582		T42	2
valid_sources[0x6d]	2138	1			T5	106		T9	570		T13	1
valid_sources[0x6e]	2446	1			T5	119		T9	494		T42	4
valid_sources[0x6f]	3086	1			T5	172		T9	515		T98	4
valid_sources[0x70]	2114	1			T5	132		T8	1		T9	527
valid_sources[0x71]	3386	1			T5	143		T9	501		T77	1
valid_sources[0x72]	3118	1			T5	147		T9	488		T98	1
valid_sources[0x73]	2024	1			T5	145		T9	452		T10	2
valid_sources[0x74]	2851	1			T5	57		T9	524		T98	4
valid_sources[0x75]	2837	1			T5	92		T9	501		T13	2
valid_sources[0x76]	3332	1			T5	170		T6	1		T8	1
valid_sources[0x77]	2990	1			T5	140		T9	514		T98	1
valid_sources[0x78]	2507	1			T5	117		T9	501		T120	8
valid_sources[0x79]	2887	1			T5	166		T9	559		T13	2
valid_sources[0x7a]	2334	1			T5	94		T9	460		T77	1
valid_sources[0x7b]	1787	1			T5	177		T9	460		T10	1
valid_sources[0x7c]	2071	1			T5	143		T9	435		T120	1
valid_sources[0x7d]	2569	1			T5	161		T9	508		T13	1
valid_sources[0x7e]	2011	1			T5	146		T9	472		T98	1
valid_sources[0x7f]	2520	1			T5	98		T9	458		T11	209
valid_sources[0x80]	2529	1			T5	158		T9	527		T117	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

151683

1

T1

21

T5

9236

T7

16

values[0x0]

all_enables

biggest_size

223946

1

T3

1

T5

13626

T6

1

values[0x1]

all_enables

biggest_size

223488

1

T3

1

T5

13517

T9

43289