Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1434143

1

T1

83

T2

167

T4

78

full_word

904490

1

T1

4

T2

18

T4

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2338343	1			T1	87		T2	185		T4	88
auto[TlIntgErrCmd]	84	1			T59	9		T60	5		T61	5
auto[TlIntgErrData]	92	1			T59	4		T60	6		T61	8
auto[TlIntgErrBoth]	114	1			T59	7		T60	9		T61	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

381172

1

T1

87

T2

185

T4

88

auto[1]

1957461

1

T5

116777

T9

375374

T11

296977

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	166542	1			T1	83		T2	167		T4	78
auto[TlIntgErrNone]	partial	auto[1]	1267329	1			T5	75686		T9	241495		T11	193657
auto[TlIntgErrNone]	full_word	auto[0]	214493	1			T1	4		T2	18		T4	10
auto[TlIntgErrNone]	full_word	auto[1]	689979	1			T5	41091		T9	133879		T11	103320
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T59	2		T60	1		T61	2
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T59	6		T60	4		T61	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T61	1		T103	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T59	1		T109	1		T110	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T59	1		T60	3		T61	5
auto[TlIntgErrData]	partial	auto[1]	43	1			T59	3		T60	2		T61	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T60	1		T61	1		T107	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T107	1		T111	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T59	5		T60	7		T61	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T59	2		T60	2		T61	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T112	1		T104	1		T113	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T61	1		T108	1		T112	1