Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
357155934 |
356980640 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
357155934 |
356980640 |
0 |
0 |
T1 |
132835 |
132659 |
0 |
0 |
T2 |
397705 |
397606 |
0 |
0 |
T3 |
278400 |
278307 |
0 |
0 |
T4 |
17527 |
17476 |
0 |
0 |
T5 |
219732 |
219720 |
0 |
0 |
T6 |
106510 |
106454 |
0 |
0 |
T7 |
639048 |
638895 |
0 |
0 |
T8 |
857760 |
857374 |
0 |
0 |
T9 |
661436 |
661426 |
0 |
0 |
T10 |
34802 |
34668 |
0 |
0 |