Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56041	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1014549

1

T2

11

T3

7

T5

85508

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	291058	1			T2	107		T3	65		T5	22768
values[0x0]	381691	1			T5	32229		T6	15895		T11	42216
values[0x1]	397841	1			T5	33575		T6	16616		T11	44176

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27885	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1042705

1

T2

62

T3

34

T5

86915

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4189	1			T2	1		T5	356		T6	175
valid_sources[0x01]	4056	1			T5	408		T6	174		T14	2
valid_sources[0x02]	7224	1			T2	3		T5	301		T6	177
valid_sources[0x03]	3594	1			T2	1		T5	272		T6	172
valid_sources[0x04]	6102	1			T5	283		T6	199		T14	2
valid_sources[0x05]	3470	1			T5	421		T6	184		T16	2
valid_sources[0x06]	3588	1			T5	207		T6	166		T14	1
valid_sources[0x07]	4708	1			T5	555		T6	190		T14	2
valid_sources[0x08]	4272	1			T2	1		T5	353		T6	162
valid_sources[0x09]	3415	1			T5	225		T6	173		T16	3
valid_sources[0x0a]	3696	1			T5	368		T6	173		T16	1
valid_sources[0x0b]	3006	1			T5	293		T6	159		T16	1
valid_sources[0x0c]	3247	1			T2	1		T5	289		T6	174
valid_sources[0x0d]	4139	1			T5	312		T6	153		T16	1
valid_sources[0x0e]	5663	1			T2	1		T5	277		T6	154
valid_sources[0x0f]	4803	1			T5	273		T6	204		T11	489
valid_sources[0x10]	3752	1			T3	17		T5	363		T6	177
valid_sources[0x11]	4646	1			T2	2		T5	303		T6	188
valid_sources[0x12]	4514	1			T5	367		T6	186		T13	2
valid_sources[0x13]	3933	1			T5	282		T6	195		T14	1
valid_sources[0x14]	4163	1			T2	1		T5	482		T6	172
valid_sources[0x15]	6060	1			T2	1		T5	310		T6	153
valid_sources[0x16]	3302	1			T2	1		T5	398		T6	164
valid_sources[0x17]	3961	1			T2	1		T5	294		T6	169
valid_sources[0x18]	4032	1			T5	352		T6	159		T14	2
valid_sources[0x19]	3748	1			T2	1		T5	170		T6	152
valid_sources[0x1a]	6996	1			T2	2		T5	508		T6	156
valid_sources[0x1b]	3412	1			T5	275		T6	177		T16	2
valid_sources[0x1c]	4171	1			T5	244		T6	196		T16	3
valid_sources[0x1d]	3875	1			T5	491		T6	186		T16	1
valid_sources[0x1e]	4413	1			T2	2		T5	423		T6	163
valid_sources[0x1f]	5394	1			T5	252		T6	176		T11	509
valid_sources[0x20]	3801	1			T5	433		T6	136		T13	8
valid_sources[0x21]	3805	1			T2	3		T5	516		T6	162
valid_sources[0x22]	3282	1			T5	484		T6	207		T16	1
valid_sources[0x23]	4319	1			T5	316		T6	187		T16	3
valid_sources[0x24]	3495	1			T5	249		T6	136		T16	1
valid_sources[0x25]	4741	1			T5	333		T6	194		T13	1
valid_sources[0x26]	4956	1			T5	306		T6	194		T11	470
valid_sources[0x27]	4563	1			T5	299		T6	166		T14	8
valid_sources[0x28]	3620	1			T5	486		T6	172		T15	1
valid_sources[0x29]	3633	1			T5	337		T6	177		T14	1
valid_sources[0x2a]	3147	1			T3	33		T5	339		T6	195
valid_sources[0x2b]	3723	1			T2	1		T5	469		T6	169
valid_sources[0x2c]	3585	1			T5	353		T6	175		T13	6
valid_sources[0x2d]	6005	1			T5	470		T6	170		T14	1
valid_sources[0x2e]	4213	1			T5	351		T6	178		T14	1
valid_sources[0x2f]	4611	1			T2	2		T5	392		T6	144
valid_sources[0x30]	4527	1			T5	434		T6	193		T14	4
valid_sources[0x31]	3374	1			T2	1		T5	333		T6	167
valid_sources[0x32]	3205	1			T5	225		T6	187		T12	9
valid_sources[0x33]	3500	1			T2	2		T5	319		T6	153
valid_sources[0x34]	4496	1			T5	550		T6	198		T58	23
valid_sources[0x35]	4283	1			T5	477		T6	198		T16	1
valid_sources[0x36]	3000	1			T2	1		T5	267		T6	159
valid_sources[0x37]	3590	1			T5	387		T6	162		T8	4
valid_sources[0x38]	4092	1			T2	1		T5	455		T6	182
valid_sources[0x39]	4356	1			T5	150		T6	177		T16	3
valid_sources[0x3a]	3255	1			T5	353		T6	143		T14	4
valid_sources[0x3b]	4302	1			T2	1		T5	535		T6	183
valid_sources[0x3c]	3397	1			T2	3		T5	364		T6	205
valid_sources[0x3d]	4426	1			T5	231		T6	158		T16	2
valid_sources[0x3e]	4378	1			T5	287		T6	155		T16	2
valid_sources[0x3f]	3760	1			T2	1		T5	283		T6	162
valid_sources[0x40]	4238	1			T5	289		T6	170		T14	1
valid_sources[0x41]	3693	1			T5	369		T6	179		T11	423
valid_sources[0x42]	4137	1			T5	328		T6	172		T11	422
valid_sources[0x43]	3571	1			T2	1		T5	229		T6	166
valid_sources[0x44]	4726	1			T5	390		T6	194		T16	3
valid_sources[0x45]	4187	1			T5	410		T6	165		T14	1
valid_sources[0x46]	4064	1			T2	1		T5	409		T6	153
valid_sources[0x47]	4308	1			T5	348		T6	165		T11	482
valid_sources[0x48]	5446	1			T5	299		T6	183		T14	1
valid_sources[0x49]	4388	1			T2	1		T5	224		T6	148
valid_sources[0x4a]	4531	1			T5	312		T6	165		T9	25
valid_sources[0x4b]	4259	1			T2	1		T5	276		T6	156
valid_sources[0x4c]	3701	1			T5	455		T6	150		T16	4
valid_sources[0x4d]	4219	1			T2	1		T5	375		T6	161
valid_sources[0x4e]	5332	1			T2	1		T5	231		T6	152
valid_sources[0x4f]	4912	1			T5	365		T6	199		T12	1
valid_sources[0x50]	4678	1			T5	328		T6	163		T14	1
valid_sources[0x51]	4309	1			T2	1		T5	664		T6	180
valid_sources[0x52]	5330	1			T2	2		T5	443		T6	163
valid_sources[0x53]	3887	1			T5	244		T6	189		T16	1
valid_sources[0x54]	5499	1			T5	449		T6	181		T16	2
valid_sources[0x55]	5043	1			T5	609		T6	193		T68	1
valid_sources[0x56]	3809	1			T5	335		T6	189		T16	3
valid_sources[0x57]	4437	1			T5	337		T6	142		T105	20
valid_sources[0x58]	3501	1			T5	317		T6	171		T16	5
valid_sources[0x59]	4867	1			T5	271		T6	192		T14	1
valid_sources[0x5a]	4467	1			T5	438		T6	155		T16	1
valid_sources[0x5b]	4956	1			T5	331		T6	169		T14	1
valid_sources[0x5c]	3406	1			T2	1		T5	169		T6	164
valid_sources[0x5d]	2882	1			T5	254		T6	164		T8	5
valid_sources[0x5e]	4070	1			T5	354		T6	158		T14	1
valid_sources[0x5f]	5000	1			T5	322		T6	163		T14	1
valid_sources[0x60]	4226	1			T2	1		T5	214		T6	175
valid_sources[0x61]	4305	1			T5	505		T6	163		T68	1
valid_sources[0x62]	4696	1			T5	258		T6	161		T16	1
valid_sources[0x63]	4328	1			T2	1		T5	438		T6	179
valid_sources[0x64]	4514	1			T5	376		T6	163		T8	6
valid_sources[0x65]	4317	1			T5	211		T6	173		T16	2
valid_sources[0x66]	4530	1			T5	253		T6	180		T8	6
valid_sources[0x67]	4338	1			T2	1		T5	350		T6	199
valid_sources[0x68]	5781	1			T5	311		T6	183		T16	1
valid_sources[0x69]	5188	1			T2	1		T5	277		T6	172
valid_sources[0x6a]	3307	1			T5	212		T6	192		T14	1
valid_sources[0x6b]	3491	1			T5	439		T6	177		T16	1
valid_sources[0x6c]	3193	1			T5	261		T6	160		T16	2
valid_sources[0x6d]	6094	1			T5	426		T6	146		T16	1
valid_sources[0x6e]	3828	1			T5	653		T6	154		T14	1
valid_sources[0x6f]	4463	1			T5	193		T6	162		T14	1
valid_sources[0x70]	4421	1			T2	1		T5	495		T6	172
valid_sources[0x71]	4712	1			T5	389		T6	198		T16	2
valid_sources[0x72]	3845	1			T2	1		T5	423		T6	167
valid_sources[0x73]	3935	1			T5	470		T6	164		T16	3
valid_sources[0x74]	4558	1			T2	1		T5	353		T6	167
valid_sources[0x75]	3771	1			T5	390		T6	195		T68	3
valid_sources[0x76]	4769	1			T5	304		T6	159		T16	1
valid_sources[0x77]	4704	1			T5	385		T6	154		T16	2
valid_sources[0x78]	3124	1			T5	269		T6	164		T16	1
valid_sources[0x79]	3236	1			T5	341		T6	174		T16	2
valid_sources[0x7a]	3796	1			T5	389		T6	172		T16	1
valid_sources[0x7b]	5757	1			T5	361		T6	178		T16	1
valid_sources[0x7c]	3989	1			T5	287		T6	162		T16	2
valid_sources[0x7d]	2822	1			T2	1		T3	15		T5	280
valid_sources[0x7e]	3246	1			T5	278		T6	145		T9	66
valid_sources[0x7f]	3610	1			T5	388		T6	198		T16	2
valid_sources[0x80]	3756	1			T5	430		T6	174		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

256087

1

T2

11

T3

7

T5

21510

values[0x0]

all_enables

biggest_size

378303

1

T5

31933

T6

15742

T11

41879

values[0x1]

all_enables

biggest_size

380159

1

T5

32065

T6

15875

T11

42256

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	81358	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

787563

1

T2

27

T3

22

T4

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	221554	1			T1	20		T2	64		T3	32
values[0x0]	299929	1			T4	6		T5	26382		T6	12648
values[0x1]	347438	1			T4	11		T5	30397		T6	14813

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37646	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

831275

1

T1

3

T2

35

T3

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3330	1			T5	286		T6	160		T12	3
valid_sources[0x01]	3304	1			T5	305		T6	179		T69	2
valid_sources[0x02]	3233	1			T5	301		T6	119		T12	1
valid_sources[0x03]	3609	1			T5	325		T6	96		T11	325
valid_sources[0x04]	3306	1			T5	311		T6	116		T69	1
valid_sources[0x05]	3465	1			T5	244		T6	163		T11	455
valid_sources[0x06]	3342	1			T5	300		T6	119		T11	252
valid_sources[0x07]	3592	1			T5	258		T6	138		T13	7
valid_sources[0x08]	3658	1			T5	278		T6	188		T11	285
valid_sources[0x09]	3509	1			T5	347		T6	120		T7	2
valid_sources[0x0a]	3528	1			T5	300		T6	109		T11	318
valid_sources[0x0b]	3189	1			T5	270		T6	126		T10	1
valid_sources[0x0c]	3465	1			T5	289		T6	170		T10	1
valid_sources[0x0d]	3263	1			T3	2		T5	298		T6	144
valid_sources[0x0e]	3418	1			T5	312		T6	150		T54	1
valid_sources[0x0f]	3117	1			T5	291		T6	132		T13	1
valid_sources[0x10]	3864	1			T5	296		T6	195		T120	1
valid_sources[0x11]	3636	1			T5	247		T6	148		T13	3
valid_sources[0x12]	3308	1			T5	288		T6	101		T13	1
valid_sources[0x13]	3529	1			T5	313		T6	152		T120	1
valid_sources[0x14]	3481	1			T3	2		T5	330		T6	164
valid_sources[0x15]	3119	1			T5	282		T6	125		T58	3
valid_sources[0x16]	3441	1			T5	284		T6	144		T120	1
valid_sources[0x17]	3220	1			T5	255		T6	148		T11	456
valid_sources[0x18]	3548	1			T5	230		T6	131		T8	1
valid_sources[0x19]	3166	1			T5	309		T6	127		T15	1
valid_sources[0x1a]	3367	1			T5	224		T6	141		T7	1
valid_sources[0x1b]	3251	1			T5	329		T6	137		T10	1
valid_sources[0x1c]	3291	1			T1	1		T5	305		T6	131
valid_sources[0x1d]	3458	1			T5	323		T6	180		T54	1
valid_sources[0x1e]	3175	1			T5	244		T6	141		T13	3
valid_sources[0x1f]	3181	1			T2	4		T5	313		T6	162
valid_sources[0x20]	3081	1			T5	303		T6	142		T13	2
valid_sources[0x21]	3259	1			T5	254		T6	129		T58	3
valid_sources[0x22]	3608	1			T5	300		T6	134		T107	1
valid_sources[0x23]	3181	1			T5	280		T6	161		T8	1
valid_sources[0x24]	3354	1			T5	302		T6	145		T8	2
valid_sources[0x25]	3248	1			T1	1		T5	320		T6	145
valid_sources[0x26]	3284	1			T5	286		T6	158		T11	288
valid_sources[0x27]	3461	1			T5	264		T6	147		T11	423
valid_sources[0x28]	3516	1			T3	5		T5	318		T6	152
valid_sources[0x29]	3496	1			T5	315		T6	121		T9	3
valid_sources[0x2a]	3467	1			T5	377		T6	189		T11	347
valid_sources[0x2b]	3395	1			T5	305		T6	152		T11	345
valid_sources[0x2c]	3307	1			T5	265		T6	184		T11	320
valid_sources[0x2d]	3592	1			T5	274		T6	164		T11	292
valid_sources[0x2e]	3298	1			T5	258		T6	142		T14	2
valid_sources[0x2f]	3837	1			T5	278		T6	147		T10	1
valid_sources[0x30]	3445	1			T5	335		T6	146		T14	1
valid_sources[0x31]	3300	1			T5	289		T6	113		T17	1
valid_sources[0x32]	3504	1			T5	338		T6	142		T68	2
valid_sources[0x33]	3415	1			T5	299		T6	133		T11	378
valid_sources[0x34]	3179	1			T5	328		T6	124		T8	1
valid_sources[0x35]	3301	1			T5	258		T6	115		T12	2
valid_sources[0x36]	3354	1			T5	283		T6	140		T120	3
valid_sources[0x37]	3492	1			T5	315		T6	161		T107	1
valid_sources[0x38]	3783	1			T5	313		T6	171		T13	1
valid_sources[0x39]	3452	1			T5	306		T6	182		T11	321
valid_sources[0x3a]	3154	1			T5	222		T6	137		T14	2
valid_sources[0x3b]	3560	1			T5	285		T6	154		T7	2
valid_sources[0x3c]	3435	1			T5	313		T6	165		T107	1
valid_sources[0x3d]	3668	1			T1	1		T5	293		T6	178
valid_sources[0x3e]	3322	1			T5	325		T6	139		T58	8
valid_sources[0x3f]	3323	1			T5	295		T6	163		T13	1
valid_sources[0x40]	3339	1			T5	270		T6	160		T107	1
valid_sources[0x41]	3351	1			T1	1		T2	13		T5	279
valid_sources[0x42]	3292	1			T5	326		T6	145		T11	283
valid_sources[0x43]	3247	1			T5	354		T6	151		T11	392
valid_sources[0x44]	3275	1			T5	391		T6	148		T107	1
valid_sources[0x45]	3098	1			T5	242		T6	141		T58	2
valid_sources[0x46]	3530	1			T5	353		T6	144		T11	309
valid_sources[0x47]	3145	1			T5	313		T6	130		T14	1
valid_sources[0x48]	3164	1			T5	223		T6	125		T11	292
valid_sources[0x49]	3571	1			T2	1		T5	281		T6	153
valid_sources[0x4a]	3456	1			T5	294		T6	136		T7	1
valid_sources[0x4b]	3295	1			T5	222		T6	130		T15	1
valid_sources[0x4c]	3564	1			T5	236		T6	172		T10	1
valid_sources[0x4d]	3328	1			T5	325		T6	129		T58	2
valid_sources[0x4e]	3314	1			T5	253		T6	149		T23	1
valid_sources[0x4f]	3221	1			T5	301		T6	149		T8	1
valid_sources[0x50]	3266	1			T5	217		T6	152		T11	354
valid_sources[0x51]	3448	1			T5	305		T6	119		T10	2
valid_sources[0x52]	3540	1			T5	309		T6	125		T7	1
valid_sources[0x53]	3363	1			T5	255		T6	146		T8	1
valid_sources[0x54]	3309	1			T5	304		T6	148		T8	1
valid_sources[0x55]	3261	1			T5	285		T6	101		T11	301
valid_sources[0x56]	3229	1			T3	11		T5	325		T6	161
valid_sources[0x57]	3182	1			T5	270		T6	186		T14	2
valid_sources[0x58]	3257	1			T5	253		T6	167		T10	1
valid_sources[0x59]	3519	1			T5	344		T6	133		T58	1
valid_sources[0x5a]	3679	1			T5	282		T6	150		T9	19
valid_sources[0x5b]	3380	1			T5	276		T6	152		T12	1
valid_sources[0x5c]	3405	1			T5	274		T6	201		T107	1
valid_sources[0x5d]	3802	1			T5	374		T6	147		T58	3
valid_sources[0x5e]	3206	1			T5	271		T6	169		T11	297
valid_sources[0x5f]	3223	1			T5	285		T6	129		T8	1
valid_sources[0x60]	3329	1			T5	306		T6	132		T107	1
valid_sources[0x61]	3721	1			T5	277		T6	166		T7	1
valid_sources[0x62]	3366	1			T5	236		T6	130		T69	1
valid_sources[0x63]	3034	1			T5	291		T6	101		T11	246
valid_sources[0x64]	3448	1			T5	292		T6	175		T8	1
valid_sources[0x65]	3277	1			T2	2		T5	333		T6	133
valid_sources[0x66]	3688	1			T5	327		T6	138		T13	1
valid_sources[0x67]	3570	1			T5	288		T6	149		T9	9
valid_sources[0x68]	3294	1			T5	301		T6	131		T107	2
valid_sources[0x69]	3184	1			T5	313		T6	175		T14	2
valid_sources[0x6a]	3604	1			T5	256		T6	163		T12	1
valid_sources[0x6b]	3228	1			T5	266		T6	187		T11	302
valid_sources[0x6c]	3522	1			T5	308		T6	142		T8	1
valid_sources[0x6d]	3584	1			T5	323		T6	141		T58	2
valid_sources[0x6e]	3410	1			T1	1		T2	1		T5	320
valid_sources[0x6f]	3702	1			T5	258		T6	127		T69	1
valid_sources[0x70]	3512	1			T5	263		T6	168		T15	1
valid_sources[0x71]	3358	1			T1	1		T5	270		T6	180
valid_sources[0x72]	3551	1			T5	308		T6	174		T107	1
valid_sources[0x73]	3557	1			T5	325		T6	130		T68	1
valid_sources[0x74]	3080	1			T5	238		T6	106		T8	1
valid_sources[0x75]	3236	1			T5	280		T6	129		T10	1
valid_sources[0x76]	3272	1			T2	2		T5	234		T6	133
valid_sources[0x77]	3198	1			T5	319		T6	170		T58	5
valid_sources[0x78]	3598	1			T5	364		T6	203		T8	1
valid_sources[0x79]	3116	1			T5	317		T6	89		T9	3
valid_sources[0x7a]	3213	1			T2	3		T5	328		T6	163
valid_sources[0x7b]	3339	1			T2	1		T5	292		T6	140
valid_sources[0x7c]	3434	1			T5	251		T6	177		T11	423
valid_sources[0x7d]	3403	1			T5	336		T6	178		T58	3
valid_sources[0x7e]	3295	1			T5	316		T6	123		T8	1
valid_sources[0x7f]	3692	1			T5	380		T6	128		T58	6
valid_sources[0x80]	3189	1			T5	284		T6	144		T58	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

201179

1

T2

27

T3

22

T5

17679

values[0x0]

all_enables

biggest_size

293335

1

T4

2

T5

25844

T6

12400

values[0x1]

all_enables

biggest_size

293049

1

T4

2

T5

25678

T6

12369